JP4306916B2 - ウェハレベルバーンイン回路を備えた半導体集積回路装置およびウェハレベルバーンイン回路の機能判定方法 - Google Patents

ウェハレベルバーンイン回路を備えた半導体集積回路装置およびウェハレベルバーンイン回路の機能判定方法 Download PDF

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Publication number
JP4306916B2
JP4306916B2 JP2000061024A JP2000061024A JP4306916B2 JP 4306916 B2 JP4306916 B2 JP 4306916B2 JP 2000061024 A JP2000061024 A JP 2000061024A JP 2000061024 A JP2000061024 A JP 2000061024A JP 4306916 B2 JP4306916 B2 JP 4306916B2
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JP
Japan
Prior art keywords
wafer level
level burn
semiconductor integrated
integrated circuit
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2000061024A
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English (en)
Japanese (ja)
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JP2001250398A5 (enExample
JP2001250398A (ja
Inventor
隆 辰巳
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
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Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP2000061024A priority Critical patent/JP4306916B2/ja
Priority to US09/649,078 priority patent/US6437590B1/en
Publication of JP2001250398A publication Critical patent/JP2001250398A/ja
Publication of JP2001250398A5 publication Critical patent/JP2001250398A5/ja
Application granted granted Critical
Publication of JP4306916B2 publication Critical patent/JP4306916B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318505—Test of Modular systems, e.g. Wafers, MCM's
    • G01R31/318511—Wafer Test
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/282—Testing of electronic circuits specially adapted for particular applications not provided for elsewhere
    • G01R31/2831—Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2855—Environmental, reliability or burn-in testing
    • G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
JP2000061024A 2000-03-06 2000-03-06 ウェハレベルバーンイン回路を備えた半導体集積回路装置およびウェハレベルバーンイン回路の機能判定方法 Expired - Fee Related JP4306916B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2000061024A JP4306916B2 (ja) 2000-03-06 2000-03-06 ウェハレベルバーンイン回路を備えた半導体集積回路装置およびウェハレベルバーンイン回路の機能判定方法
US09/649,078 US6437590B1 (en) 2000-03-06 2000-08-28 Integrated semiconductor device with wafer-level burn-in circuit and function decision method of wafer-level burn-in circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000061024A JP4306916B2 (ja) 2000-03-06 2000-03-06 ウェハレベルバーンイン回路を備えた半導体集積回路装置およびウェハレベルバーンイン回路の機能判定方法

Publications (3)

Publication Number Publication Date
JP2001250398A JP2001250398A (ja) 2001-09-14
JP2001250398A5 JP2001250398A5 (enExample) 2006-09-14
JP4306916B2 true JP4306916B2 (ja) 2009-08-05

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000061024A Expired - Fee Related JP4306916B2 (ja) 2000-03-06 2000-03-06 ウェハレベルバーンイン回路を備えた半導体集積回路装置およびウェハレベルバーンイン回路の機能判定方法

Country Status (2)

Country Link
US (1) US6437590B1 (enExample)
JP (1) JP4306916B2 (enExample)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6861860B2 (en) * 2002-05-17 2005-03-01 Stmicroelectronics, Inc. Integrated circuit burn-in test system and associated methods
JP2004152399A (ja) 2002-10-30 2004-05-27 Renesas Technology Corp 半導体記憶装置
KR100624576B1 (ko) * 2004-06-11 2006-09-19 삼성전자주식회사 허브를 갖는 메모리 모듈을 테스트하는 방법 및 이를수행하기 위한 메모리 모듈의 허브
GB0413140D0 (en) * 2004-06-12 2004-07-14 Texas Instruments Ltd Serial burn-in monitor
JP5170395B2 (ja) * 2008-02-21 2013-03-27 日本電気株式会社 ウエハ及びその温度試験方法
US7916519B2 (en) * 2009-02-09 2011-03-29 Vanguard International Semiconductor Corporation Burn-in methods for static random access memories and chips
JP2012252733A (ja) 2011-05-31 2012-12-20 Elpida Memory Inc 半導体装置
KR102125568B1 (ko) * 2014-02-19 2020-06-23 에스케이하이닉스 주식회사 반도체 장치 및 그 테스트 방법

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3734853B2 (ja) 1995-06-27 2006-01-11 株式会社ルネサステクノロジ 半導体記憶装置
US6326800B1 (en) * 1999-06-10 2001-12-04 International Business Machines Corporation Self-adjusting burn-in test
US6184048B1 (en) * 1999-11-03 2001-02-06 Texas Instruments Incorporated Testing method and apparatus assuring semiconductor device quality and reliability

Also Published As

Publication number Publication date
US6437590B1 (en) 2002-08-20
JP2001250398A (ja) 2001-09-14

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