JP2001250398A5 - - Google Patents
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- Publication number
- JP2001250398A5 JP2001250398A5 JP2000061024A JP2000061024A JP2001250398A5 JP 2001250398 A5 JP2001250398 A5 JP 2001250398A5 JP 2000061024 A JP2000061024 A JP 2000061024A JP 2000061024 A JP2000061024 A JP 2000061024A JP 2001250398 A5 JP2001250398 A5 JP 2001250398A5
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000061024A JP4306916B2 (ja) | 2000-03-06 | 2000-03-06 | ウェハレベルバーンイン回路を備えた半導体集積回路装置およびウェハレベルバーンイン回路の機能判定方法 |
| US09/649,078 US6437590B1 (en) | 2000-03-06 | 2000-08-28 | Integrated semiconductor device with wafer-level burn-in circuit and function decision method of wafer-level burn-in circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000061024A JP4306916B2 (ja) | 2000-03-06 | 2000-03-06 | ウェハレベルバーンイン回路を備えた半導体集積回路装置およびウェハレベルバーンイン回路の機能判定方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2001250398A JP2001250398A (ja) | 2001-09-14 |
| JP2001250398A5 true JP2001250398A5 (enExample) | 2006-09-14 |
| JP4306916B2 JP4306916B2 (ja) | 2009-08-05 |
Family
ID=18581238
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000061024A Expired - Fee Related JP4306916B2 (ja) | 2000-03-06 | 2000-03-06 | ウェハレベルバーンイン回路を備えた半導体集積回路装置およびウェハレベルバーンイン回路の機能判定方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (1) | US6437590B1 (enExample) |
| JP (1) | JP4306916B2 (enExample) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6861860B2 (en) * | 2002-05-17 | 2005-03-01 | Stmicroelectronics, Inc. | Integrated circuit burn-in test system and associated methods |
| JP2004152399A (ja) | 2002-10-30 | 2004-05-27 | Renesas Technology Corp | 半導体記憶装置 |
| KR100624576B1 (ko) * | 2004-06-11 | 2006-09-19 | 삼성전자주식회사 | 허브를 갖는 메모리 모듈을 테스트하는 방법 및 이를수행하기 위한 메모리 모듈의 허브 |
| GB0413140D0 (en) * | 2004-06-12 | 2004-07-14 | Texas Instruments Ltd | Serial burn-in monitor |
| JP5170395B2 (ja) * | 2008-02-21 | 2013-03-27 | 日本電気株式会社 | ウエハ及びその温度試験方法 |
| US7916519B2 (en) * | 2009-02-09 | 2011-03-29 | Vanguard International Semiconductor Corporation | Burn-in methods for static random access memories and chips |
| JP2012252733A (ja) | 2011-05-31 | 2012-12-20 | Elpida Memory Inc | 半導体装置 |
| KR102125568B1 (ko) * | 2014-02-19 | 2020-06-23 | 에스케이하이닉스 주식회사 | 반도체 장치 및 그 테스트 방법 |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3734853B2 (ja) | 1995-06-27 | 2006-01-11 | 株式会社ルネサステクノロジ | 半導体記憶装置 |
| US6326800B1 (en) * | 1999-06-10 | 2001-12-04 | International Business Machines Corporation | Self-adjusting burn-in test |
| US6184048B1 (en) * | 1999-11-03 | 2001-02-06 | Texas Instruments Incorporated | Testing method and apparatus assuring semiconductor device quality and reliability |
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2000
- 2000-03-06 JP JP2000061024A patent/JP4306916B2/ja not_active Expired - Fee Related
- 2000-08-28 US US09/649,078 patent/US6437590B1/en not_active Expired - Fee Related