JP4274469B2 - データ取り込みクロック補正回路 - Google Patents

データ取り込みクロック補正回路 Download PDF

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Publication number
JP4274469B2
JP4274469B2 JP2004011477A JP2004011477A JP4274469B2 JP 4274469 B2 JP4274469 B2 JP 4274469B2 JP 2004011477 A JP2004011477 A JP 2004011477A JP 2004011477 A JP2004011477 A JP 2004011477A JP 4274469 B2 JP4274469 B2 JP 4274469B2
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JP
Japan
Prior art keywords
data
data capture
clock
phase
capture clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2004011477A
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English (en)
Japanese (ja)
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JP2005210162A (ja
JP2005210162A5 (https=
Inventor
孝明 平野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Lapis Semiconductor Co Ltd
Original Assignee
Oki Semiconductor Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oki Semiconductor Co Ltd filed Critical Oki Semiconductor Co Ltd
Priority to JP2004011477A priority Critical patent/JP4274469B2/ja
Priority to US11/038,061 priority patent/US7167034B2/en
Publication of JP2005210162A publication Critical patent/JP2005210162A/ja
Publication of JP2005210162A5 publication Critical patent/JP2005210162A5/ja
Application granted granted Critical
Publication of JP4274469B2 publication Critical patent/JP4274469B2/ja
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Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C27/00—Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02—Sample-and-hold arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/042—Detectors therefor, e.g. correlators, state machines

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP2004011477A 2004-01-20 2004-01-20 データ取り込みクロック補正回路 Expired - Fee Related JP4274469B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2004011477A JP4274469B2 (ja) 2004-01-20 2004-01-20 データ取り込みクロック補正回路
US11/038,061 US7167034B2 (en) 2004-01-20 2005-01-21 Arrangement for correcting the phase of a data sampling clock signal during a period of sampling data in a received signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004011477A JP4274469B2 (ja) 2004-01-20 2004-01-20 データ取り込みクロック補正回路

Publications (3)

Publication Number Publication Date
JP2005210162A JP2005210162A (ja) 2005-08-04
JP2005210162A5 JP2005210162A5 (https=) 2006-09-21
JP4274469B2 true JP4274469B2 (ja) 2009-06-10

Family

ID=34747292

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2004011477A Expired - Fee Related JP4274469B2 (ja) 2004-01-20 2004-01-20 データ取り込みクロック補正回路

Country Status (2)

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US (1) US7167034B2 (https=)
JP (1) JP4274469B2 (https=)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060176934A1 (en) * 2005-02-07 2006-08-10 Inova Semiconductors Gmbh Serial transmission of data using spread-spectrum modulation for enhancing electromagnetic compatibility
JP2007067646A (ja) * 2005-08-30 2007-03-15 Oki Electric Ind Co Ltd サンプリングレート変換方法及びその回路
US8428195B2 (en) 2007-12-31 2013-04-23 Agere Systems Llc Methods and apparatus for detecting and decoding adaptive equalization training frames
US8094766B2 (en) * 2008-07-02 2012-01-10 Teradyne, Inc. Tracker circuit and method for automated test equipment systems
JP5418035B2 (ja) * 2009-07-21 2014-02-19 富士ゼロックス株式会社 直列信号の受信装置、直列信号の受信方法、直列伝送システムおよび画像形成装置
JP7148796B2 (ja) * 2018-12-11 2022-10-06 日本電信電話株式会社 伝送装置及び伝送システム
CN112511164B (zh) * 2020-11-25 2023-03-14 中国科学技术大学 基于单比特采样的高速实时弱信号检测方法及装置

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ATE244570T1 (de) * 1993-09-09 2003-07-15 Lorus Therapeutics Inc Immunmodulierende zusammensetzungen aus galle
JPH0898284A (ja) * 1994-07-25 1996-04-12 Nippondenso Co Ltd データ受信装置，送信装置および通信装置
EP0821503B1 (en) * 1996-07-22 2007-01-03 Nippon Telegraph And Telephone Corporation Clock timing recovery circuit
JP3262219B2 (ja) 1998-05-27 2002-03-04 エヌイーシーアクセステクニカ株式会社 無線通信装置及びその同期引き込み方法

Also Published As

Publication number Publication date
JP2005210162A (ja) 2005-08-04
US7167034B2 (en) 2007-01-23
US20050156645A1 (en) 2005-07-21

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