JP4266502B2 - 半導体基板の表面上における銅のデュアル・ダマシン構造体の表面を処理する方法 - Google Patents

半導体基板の表面上における銅のデュアル・ダマシン構造体の表面を処理する方法 Download PDF

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Publication number
JP4266502B2
JP4266502B2 JP2000247159A JP2000247159A JP4266502B2 JP 4266502 B2 JP4266502 B2 JP 4266502B2 JP 2000247159 A JP2000247159 A JP 2000247159A JP 2000247159 A JP2000247159 A JP 2000247159A JP 4266502 B2 JP4266502 B2 JP 4266502B2
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Prior art keywords
layer
dual damascene
copper
metal layer
damascene opening
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Expired - Fee Related
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JP2000247159A
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Japanese (ja)
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JP2001176879A (ja
JP2001176879A5 (https=
Inventor
メイ・シェン・チョウ
ポール・ウォク・キュン・ホー
サブハッシュ・ギュプタ
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チャータード・セミコンダクター・マニュファクチャリング・リミテッド
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/077—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H10P52/40—Chemomechanical polishing [CMP]
    • H10P52/403—Chemomechanical polishing [CMP] of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/062—Manufacture or treatment of conductive parts of the interconnections by smoothing of conductive parts, e.g. by planarisation
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
JP2000247159A 1999-09-07 2000-08-17 半導体基板の表面上における銅のデュアル・ダマシン構造体の表面を処理する方法 Expired - Fee Related JP4266502B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/390783 1999-09-07
US09/390,783 US6251786B1 (en) 1999-09-07 1999-09-07 Method to create a copper dual damascene structure with less dishing and erosion

Publications (3)

Publication Number Publication Date
JP2001176879A JP2001176879A (ja) 2001-06-29
JP2001176879A5 JP2001176879A5 (https=) 2007-10-04
JP4266502B2 true JP4266502B2 (ja) 2009-05-20

Family

ID=23543923

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000247159A Expired - Fee Related JP4266502B2 (ja) 1999-09-07 2000-08-17 半導体基板の表面上における銅のデュアル・ダマシン構造体の表面を処理する方法

Country Status (4)

Country Link
US (1) US6251786B1 (https=)
EP (1) EP1083596B1 (https=)
JP (1) JP4266502B2 (https=)
SG (1) SG121686A1 (https=)

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KR100444301B1 (ko) * 2001-12-29 2004-08-16 주식회사 하이닉스반도체 질화막 ｃｍｐ를 이용한 다마신 금속 게이트 형성 방법
JP4088120B2 (ja) * 2002-08-12 2008-05-21 株式会社ルネサステクノロジ 半導体装置
US6670274B1 (en) 2002-10-01 2003-12-30 Taiwan Semiconductor Manufacturing Company Method of forming a copper damascene structure comprising a recessed copper-oxide-free initial copper structure
US6940108B2 (en) * 2002-12-05 2005-09-06 Taiwan Semiconductor Manufacturing Co., Ltd. Slot design for metal interconnects
US7825516B2 (en) * 2002-12-11 2010-11-02 International Business Machines Corporation Formation of aligned capped metal lines and interconnections in multilevel semiconductor structures
US6975032B2 (en) * 2002-12-16 2005-12-13 International Business Machines Corporation Copper recess process with application to selective capping and electroless plating
KR20040060563A (ko) * 2002-12-30 2004-07-06 동부전자 주식회사 반도체 소자 제조방법 및 구조
US7294241B2 (en) 2003-01-03 2007-11-13 Chartered Semiconductor Manufacturing Ltd. Method to form alpha phase Ta and its application to IC manufacturing
US20040185992A1 (en) * 2003-03-18 2004-09-23 Tisdale Lucien E. Method and apparatus for making a packaging article and packaging article made by the method and apparatus
JP4638140B2 (ja) * 2003-07-09 2011-02-23 マグナチップセミコンダクター有限会社 半導体素子の銅配線形成方法
US20050079703A1 (en) * 2003-10-09 2005-04-14 Applied Materials, Inc. Method for planarizing an interconnect structure
US7183199B2 (en) * 2003-12-01 2007-02-27 Taiwan Semiconductor Manufacturing Co., Ltd. Method of reducing the pattern effect in the CMP process
US20050139292A1 (en) * 2003-12-31 2005-06-30 Suresh Ramarajan Method and apparatus for minimizing thickness-to-planarity and dishing in CMP
US20060113675A1 (en) * 2004-12-01 2006-06-01 Chung-Liang Chang Barrier material and process for Cu interconnect
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US20060205204A1 (en) * 2005-03-14 2006-09-14 Michael Beck Method of making a semiconductor interconnect with a metal cap
US20070080455A1 (en) * 2005-10-11 2007-04-12 International Business Machines Corporation Semiconductors and methods of making
KR100729126B1 (ko) * 2005-11-15 2007-06-14 동부일렉트로닉스 주식회사 반도체 소자의 금속 배선 및 그 형성 방법
US7432205B2 (en) * 2005-12-15 2008-10-07 United Microelectronics Corp. Method for controlling polishing process
CN100477120C (zh) * 2005-12-30 2009-04-08 联华电子股份有限公司 抛光工艺的控制方法
US7863183B2 (en) * 2006-01-18 2011-01-04 International Business Machines Corporation Method for fabricating last level copper-to-C4 connection with interfacial cap structure
US7619310B2 (en) * 2006-11-03 2009-11-17 Infineon Technologies Ag Semiconductor interconnect and method of making same
US7893459B2 (en) * 2007-04-10 2011-02-22 Taiwan Semiconductor Manufacturing Company, Ltd. Seal ring structures with reduced moisture-induced reliability degradation
US20090039512A1 (en) * 2007-08-08 2009-02-12 International Business Machines Corporation Electromigration resistant interconnect structure
US20090200668A1 (en) * 2008-02-07 2009-08-13 International Business Machines Corporation Interconnect structure with high leakage resistance
US9281239B2 (en) * 2008-10-27 2016-03-08 Nxp B.V. Biocompatible electrodes and methods of manufacturing biocompatible electrodes
US8629063B2 (en) 2011-06-08 2014-01-14 International Business Machines Corporation Forming features on a substrate having varying feature densities
KR102085086B1 (ko) 2013-10-29 2020-03-05 삼성전자주식회사 반도체 장치 및 그 제조방법
US10211278B2 (en) * 2017-07-11 2019-02-19 Texas Instruments Incorporated Device and method for a thin film resistor using a via retardation layer
US11018087B2 (en) * 2018-04-25 2021-05-25 International Business Machines Corporation Metal interconnects
US11282788B2 (en) 2019-07-25 2022-03-22 International Business Machines Corporation Interconnect and memory structures formed in the BEOL
US11195751B2 (en) 2019-09-13 2021-12-07 International Business Machines Corporation Bilayer barrier for interconnect and memory structures formed in the BEOL
TW202225649A (zh) * 2020-07-29 2022-07-01 法商林銳股份有限公司 紅外線成像微測輻射熱計及相關形成方法
FR3113125B1 (fr) * 2020-07-29 2022-07-29 Lynred Procede de realisation d’un micro-bolometre d’imagerie infrarouge et micro-bolometre associe
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Also Published As

Publication number Publication date
JP2001176879A (ja) 2001-06-29
SG121686A1 (en) 2006-05-26
EP1083596A1 (en) 2001-03-14
US6251786B1 (en) 2001-06-26
EP1083596B1 (en) 2012-08-22

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