JP4237216B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

Info

Publication number
JP4237216B2
JP4237216B2 JP2006273865A JP2006273865A JP4237216B2 JP 4237216 B2 JP4237216 B2 JP 4237216B2 JP 2006273865 A JP2006273865 A JP 2006273865A JP 2006273865 A JP2006273865 A JP 2006273865A JP 4237216 B2 JP4237216 B2 JP 4237216B2
Authority
JP
Japan
Prior art keywords
film
pattern
semiconductor device
manufacturing
resist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2006273865A
Other languages
English (en)
Japanese (ja)
Other versions
JP2008091824A (ja
JP2008091824A5 (https=
Inventor
雅人 藤田
謙介 谷口
彰 満生
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Priority to JP2006273865A priority Critical patent/JP4237216B2/ja
Priority to US11/600,071 priority patent/US7462566B2/en
Publication of JP2008091824A publication Critical patent/JP2008091824A/ja
Publication of JP2008091824A5 publication Critical patent/JP2008091824A5/ja
Application granted granted Critical
Publication of JP4237216B2 publication Critical patent/JP4237216B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/71—Etching of wafers, substrates or parts of devices using masks for conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01306—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the conductor comprising a layer of silicon contacting the insulator, e.g. polysilicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
JP2006273865A 2006-10-05 2006-10-05 半導体装置の製造方法 Active JP4237216B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2006273865A JP4237216B2 (ja) 2006-10-05 2006-10-05 半導体装置の製造方法
US11/600,071 US7462566B2 (en) 2006-10-05 2006-11-16 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2006273865A JP4237216B2 (ja) 2006-10-05 2006-10-05 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2008091824A JP2008091824A (ja) 2008-04-17
JP2008091824A5 JP2008091824A5 (https=) 2008-08-07
JP4237216B2 true JP4237216B2 (ja) 2009-03-11

Family

ID=39275280

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2006273865A Active JP4237216B2 (ja) 2006-10-05 2006-10-05 半導体装置の製造方法

Country Status (2)

Country Link
US (1) US7462566B2 (https=)
JP (1) JP4237216B2 (https=)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008091825A (ja) * 2006-10-05 2008-04-17 Nec Electronics Corp 半導体装置の製造方法
KR20090077511A (ko) * 2008-01-11 2009-07-15 삼성전자주식회사 콘택홀 형성 방법 및 이를 포함하는 반도체 소자의 제조방법.
JP2009283863A (ja) * 2008-05-26 2009-12-03 Renesas Technology Corp 半導体装置の製造方法
JP5661524B2 (ja) 2011-03-22 2015-01-28 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
JP2014239191A (ja) * 2013-06-10 2014-12-18 富士通セミコンダクター株式会社 半導体装置の製造方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3257593B2 (ja) 1999-02-05 2002-02-18 日本電気株式会社 半導体装置の製造方法
DE19958904C2 (de) * 1999-12-07 2002-01-24 Infineon Technologies Ag Verfahren zur Herstellung einer Hartmaske auf einem Substrat
KR100669862B1 (ko) 2000-11-13 2007-01-17 삼성전자주식회사 반도체 장치의 미세패턴 형성방법
US6656811B2 (en) * 2001-12-21 2003-12-02 Texas Instruments Incorporated Carbide emitter mask etch stop
JP4342767B2 (ja) 2002-04-23 2009-10-14 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
JP4193438B2 (ja) * 2002-07-30 2008-12-10 ソニー株式会社 半導体装置の製造方法
JP2004133384A (ja) 2002-08-14 2004-04-30 Sony Corp レジスト用剥離剤組成物及び半導体装置の製造方法
JP4057972B2 (ja) 2003-07-25 2008-03-05 富士通株式会社 半導体装置の製造方法
JP2005086119A (ja) 2003-09-11 2005-03-31 Matsushita Electric Ind Co Ltd 微細パターンの形成方法
JP2005203672A (ja) * 2004-01-19 2005-07-28 Sony Corp 半導体装置の製造方法
US7115993B2 (en) * 2004-01-30 2006-10-03 Tokyo Electron Limited Structure comprising amorphous carbon film and method of forming thereof
JP2006013190A (ja) * 2004-06-28 2006-01-12 Rohm Co Ltd 半導体装置の製造方法
US7407851B2 (en) * 2006-03-22 2008-08-05 Miller Gayle W DMOS device with sealed channel processing

Also Published As

Publication number Publication date
US7462566B2 (en) 2008-12-09
JP2008091824A (ja) 2008-04-17
US20080085608A1 (en) 2008-04-10

Similar Documents

Publication Publication Date Title
US7989355B2 (en) Method of pitch halving
US20130252429A1 (en) Mask and method for fabricating semiconductor device
KR101169164B1 (ko) 반도체 소자의 형성 방법
US8524604B2 (en) Method for forming fine pattern of semiconductor device
TWI567785B (zh) 半導體裝置圖案化結構之製作方法
JP4342767B2 (ja) 半導体装置の製造方法
US7737016B2 (en) Two-print two-etch method for enhancement of CD control using ghost poly
US20040029021A1 (en) Method of forming a rim phase shifting mask and using the rim phase shifting mask to form a semiconductor device
JP4237216B2 (ja) 半導体装置の製造方法
US10593551B2 (en) Method to increase the process window in double patterning process
JP2004054115A (ja) パターン転写用フォトマスクのパターンレイアウト方法、パターン転写用フォトマスクおよび半導体装置の製造方法
US9230812B2 (en) Method for forming semiconductor structure having opening
JP2010211046A (ja) パターン検証方法およびパターン検証プログラム
US7939227B2 (en) Method and structure for fabricating dark-periphery mask for the manufacture of semiconductor wafers
JP5169575B2 (ja) フォトマスクパターンの作成方法
KR20090000876A (ko) 반도체소자의 위상반전마스크 형성방법
JP2007149768A (ja) 半導体装置の製造方法
US20070105053A1 (en) Method of manufacturing semiconductor device
US9606432B2 (en) Alternating space decomposition in circuit structure fabrication
US9396966B1 (en) Patterning method and semiconductor structure
JP2007180475A (ja) 非晶質カーボンを利用する半導体素子の製造方法
TWI573249B (zh) 半導體佈局圖案之製作方法、半導體元件之製作方法以及半導體元件
US7534727B2 (en) Method for manufacturing semiconductor device
KR100505421B1 (ko) 반도체 소자의 패턴 형성 방법
KR20060069600A (ko) 노광용 마스크의 제조 방법

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20080625

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20080625

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20080625

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20080828

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20080902

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20081023

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20081118

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20081217

R150 Certificate of patent or registration of utility model

Ref document number: 4237216

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111226

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111226

Year of fee payment: 3

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111226

Year of fee payment: 3

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20111226

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121226

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20121226

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20131226

Year of fee payment: 5

S531 Written request for registration of change of domicile

Free format text: JAPANESE INTERMEDIATE CODE: R313531

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350