JP4215571B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP4215571B2
JP4215571B2 JP2003170757A JP2003170757A JP4215571B2 JP 4215571 B2 JP4215571 B2 JP 4215571B2 JP 2003170757 A JP2003170757 A JP 2003170757A JP 2003170757 A JP2003170757 A JP 2003170757A JP 4215571 B2 JP4215571 B2 JP 4215571B2
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JP
Japan
Prior art keywords
semiconductor device
manufacturing
substrate
film
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2003170757A
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English (en)
Japanese (ja)
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JP2004080006A5 (enExample
JP2004080006A (ja
Inventor
崇 野間
裕之 篠木
幸弘 高尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2003170757A priority Critical patent/JP4215571B2/ja
Publication of JP2004080006A publication Critical patent/JP2004080006A/ja
Publication of JP2004080006A5 publication Critical patent/JP2004080006A5/ja
Application granted granted Critical
Publication of JP4215571B2 publication Critical patent/JP4215571B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01014Silicon [Si]

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2003170757A 2002-06-18 2003-06-16 半導体装置の製造方法 Expired - Fee Related JP4215571B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2003170757A JP4215571B2 (ja) 2002-06-18 2003-06-16 半導体装置の製造方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2002176775 2002-06-18
JP2003170757A JP4215571B2 (ja) 2002-06-18 2003-06-16 半導体装置の製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2006088903A Division JP4286264B2 (ja) 2002-06-18 2006-03-28 半導体装置及びその製造方法

Publications (3)

Publication Number Publication Date
JP2004080006A JP2004080006A (ja) 2004-03-11
JP2004080006A5 JP2004080006A5 (enExample) 2006-05-18
JP4215571B2 true JP4215571B2 (ja) 2009-01-28

Family

ID=32032455

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2003170757A Expired - Fee Related JP4215571B2 (ja) 2002-06-18 2003-06-16 半導体装置の製造方法

Country Status (1)

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JP (1) JP4215571B2 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101373747B (zh) * 2004-03-16 2011-06-29 株式会社藤仓 具有通孔互连的装置及其制造方法
JP4746847B2 (ja) * 2004-04-27 2011-08-10 三洋電機株式会社 半導体装置の製造方法
JP4936695B2 (ja) * 2004-09-29 2012-05-23 オンセミコンダクター・トレーディング・リミテッド 半導体装置及びその製造方法
JP4522213B2 (ja) * 2004-09-29 2010-08-11 三洋電機株式会社 半導体装置の製造方法
TWI313914B (en) 2005-01-31 2009-08-21 Sanyo Electric Co Semiconductor device and a method for manufacturing thereof
US20070090156A1 (en) * 2005-10-25 2007-04-26 Ramanathan Lakshmi N Method for forming solder contacts on mounted substrates
US8513789B2 (en) 2006-10-10 2013-08-20 Tessera, Inc. Edge connect wafer level stacking with leads extending along edges
US7901989B2 (en) 2006-10-10 2011-03-08 Tessera, Inc. Reconstituted wafer level stacking
WO2009017758A2 (en) 2007-07-27 2009-02-05 Tessera, Inc. Reconstituted wafer stack packaging with after-applied pad extensions
WO2009154761A1 (en) 2008-06-16 2009-12-23 Tessera Research Llc Stacking of wafer-level chip scale packages having edge contacts

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06326293A (ja) * 1993-05-12 1994-11-25 Hamamatsu Photonics Kk 光検出装置
IL123207A0 (en) * 1998-02-06 1998-09-24 Shellcase Ltd Integrated circuit device
KR100315030B1 (ko) * 1998-12-29 2002-04-24 박종섭 반도체패키지의제조방법
JP3750468B2 (ja) * 2000-03-01 2006-03-01 セイコーエプソン株式会社 半導体ウエハーの製造方法及び半導体装置
JP2001313350A (ja) * 2000-04-28 2001-11-09 Sony Corp チップ状電子部品及びその製造方法、並びにその製造に用いる疑似ウエーハ及びその製造方法
JP4454805B2 (ja) * 2000-07-04 2010-04-21 藤森工業株式会社 保護フィルム及び導体箔積層体
JP2002093942A (ja) * 2000-09-14 2002-03-29 Nec Corp 半導体装置およびその製造方法

Also Published As

Publication number Publication date
JP2004080006A (ja) 2004-03-11

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