JP4204993B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP4204993B2 JP4204993B2 JP2004034506A JP2004034506A JP4204993B2 JP 4204993 B2 JP4204993 B2 JP 4204993B2 JP 2004034506 A JP2004034506 A JP 2004034506A JP 2004034506 A JP2004034506 A JP 2004034506A JP 4204993 B2 JP4204993 B2 JP 4204993B2
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- Prior art keywords
- heat sink
- heat
- semiconductor device
- mold
- lead frame
- Prior art date
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- 239000004065 semiconductor Substances 0.000 title claims description 46
- 230000017525 heat dissipation Effects 0.000 claims description 18
- 230000009471 action Effects 0.000 claims description 2
- 239000011347 resin Substances 0.000 description 25
- 229920005989 resin Polymers 0.000 description 25
- 230000005855 radiation Effects 0.000 description 13
- 238000010586 diagram Methods 0.000 description 9
- 238000009413 insulation Methods 0.000 description 8
- 230000000694 effects Effects 0.000 description 6
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000006866 deterioration Effects 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000035699 permeability Effects 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 230000000191 radiation effect Effects 0.000 description 1
- 238000009423 ventilation Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1305—Bipolar Junction Transistor [BJT]
- H01L2924/13055—Insulated gate bipolar transistor [IGBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Description
<参考例1>
図1は、本発明の参考例1に係る半導体装置の構成を示す図であり、DIP−IPM(Dual-In-Line Package Intelligent Power Module)と呼ばれるトランスファーモールド型のパワーモジュールの断面図である。図1(b)は、図1(a)のA−A線に沿った断面に相当している。当該半導体装置は金属薄板より形成されるリードフレーム11,12を複数個有している。各リードフレーム11上にはIGBT(絶縁ゲート型バイポーラトランジスタ)やFWD(フリーホイールダイオード)等の電力用半導体チップ(以下「パワーチップ」)21がそれぞれ搭載されており、リードフレーム12上にはパワーチップ21を制御するための制御用IC22がそれぞれ搭載されている。パワーチップ21および制御用IC22は、アルミワイヤ4を介して所定のリードフレーム11,12と電気的に接続している。パワーチップ21は発熱量が大きいため、リードフレーム11を介して、銅やアルミニウム等の金属製のヒートシンク3が設けられる。そして、以上の各部品が絶縁性のモールド樹脂5によって一体的に保持されている。
図3は、本発明の参考例2に係る半導体装置の構成を示す図であり、トランスファーモールド型のパワーモジュールの断面図である。図3(b)は、図3(a)のB−B線に沿った断面に相当している。図3において、図1に示したものと同様の機能を有する要素には同一符号を付してあるので、ここでの詳細な説明は省略する。
図4は、本発明の実施の形態1に係る半導体装置の構成を示す図であり、トランスファーモールド型のパワーモジュールの断面図である。図4(b)は、図4(a)のC−C線に沿った断面に相当している。図4において、図3に示したものと同様の機能を有する要素には同一符号を付してあるので、ここでの詳細な説明は省略する。
図5は、本発明の実施の形態2に係る半導体装置の構成を示す図であり、トランスファーモールド型のパワーモジュールの断面図である。図5(b)は、図5(a)のD−D線に沿った断面に相当している。図5において図3に示したものと同様の機能を有する要素には同一符号を付してあるのでここでの詳細な説明は省略する。
Claims (2)
- 複数の半導体チップと、
各々が少なくとも1つの前記半導体チップと電気的に接続する複数のリードフレームと、
各々が少なくとも1つの前記半導体チップに対応して設けられ、放熱作用を有する複数のヒートシンクと、
前記半導体チップ、前記リードフレームおよび前記ヒートシンクに一体的に成形された絶縁性のモールドとを備える半導体装置であって、
それぞれの前記ヒートシンクは、一部が前記モールド内に埋め込まれており、且つ、前記モールド内から突出した突出部を有し、
前記ヒートシンクの前記突出部における隣接する他のヒートシンクに面する方向の厚さは、当該ヒートシンクの前記モールド内部分の同方向の厚さよりも薄い
ことを特徴とする半導体装置。 - 前記突出部間の前記モールド表面に、凹凸部を有する
ことを特徴とする請求項1に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004034506A JP4204993B2 (ja) | 2004-02-12 | 2004-02-12 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004034506A JP4204993B2 (ja) | 2004-02-12 | 2004-02-12 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005228849A JP2005228849A (ja) | 2005-08-25 |
JP4204993B2 true JP4204993B2 (ja) | 2009-01-07 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004034506A Expired - Lifetime JP4204993B2 (ja) | 2004-02-12 | 2004-02-12 | 半導体装置 |
Country Status (1)
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JP (1) | JP4204993B2 (ja) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5674537B2 (ja) * | 2011-04-07 | 2015-02-25 | 新電元工業株式会社 | 電気部品モジュール |
JP2012248774A (ja) * | 2011-05-31 | 2012-12-13 | Denso Corp | 半導体装置およびその製造方法 |
CN104347531A (zh) * | 2013-07-23 | 2015-02-11 | 西安永电电气有限责任公司 | 塑封式智能功率模块及其散热器结构 |
JP2017022209A (ja) * | 2015-07-08 | 2017-01-26 | 三菱電機株式会社 | 半導体モジュール |
JP6289792B1 (ja) * | 2017-09-28 | 2018-03-07 | 三菱電機株式会社 | 半導体装置、および、半導体装置の製造方法 |
CN110289230B (zh) * | 2019-06-17 | 2021-05-28 | 广东美的制冷设备有限公司 | 智能功率模块的制作工装及方法 |
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2004
- 2004-02-12 JP JP2004034506A patent/JP4204993B2/ja not_active Expired - Lifetime
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JP2005228849A (ja) | 2005-08-25 |
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