JP4191740B2 - インプリント法を利用した印刷回路基板の製造方法 - Google Patents
インプリント法を利用した印刷回路基板の製造方法 Download PDFInfo
- Publication number
- JP4191740B2 JP4191740B2 JP2006019262A JP2006019262A JP4191740B2 JP 4191740 B2 JP4191740 B2 JP 4191740B2 JP 2006019262 A JP2006019262 A JP 2006019262A JP 2006019262 A JP2006019262 A JP 2006019262A JP 4191740 B2 JP4191740 B2 JP 4191740B2
- Authority
- JP
- Japan
- Prior art keywords
- insulating layer
- circuit board
- printed circuit
- layer
- molds
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/107—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by filling grooves in the support with conductive material
-
- A—HUMAN NECESSITIES
- A01—AGRICULTURE; FORESTRY; ANIMAL HUSBANDRY; HUNTING; TRAPPING; FISHING
- A01G—HORTICULTURE; CULTIVATION OF VEGETABLES, FLOWERS, RICE, FRUIT, VINES, HOPS OR SEAWEED; FORESTRY; WATERING
- A01G13/00—Protecting plants
- A01G13/02—Protective coverings for plants; Coverings for the ground; Devices for laying-out or removing coverings
- A01G13/0256—Ground coverings
- A01G13/0268—Mats or sheets, e.g. nets or fabrics
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
- H05K3/045—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching by making a conductive layer having a relief pattern, followed by abrading of the raised portions
-
- A—HUMAN NECESSITIES
- A01—AGRICULTURE; FORESTRY; ANIMAL HUSBANDRY; HUNTING; TRAPPING; FISHING
- A01G—HORTICULTURE; CULTIVATION OF VEGETABLES, FLOWERS, RICE, FRUIT, VINES, HOPS OR SEAWEED; FORESTRY; WATERING
- A01G13/00—Protecting plants
- A01G2013/006—Protecting plants with perforations
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09818—Shape or layout details not covered by a single group of H05K2201/09009 - H05K2201/09809
- H05K2201/09972—Partitioned, e.g. portions of a PCB dedicated to different functions; Boundary lines therefore; Portions of a PCB being processed separately or differently
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/01—Tools for processing; Objects used during processing
- H05K2203/0104—Tools for processing; Objects used during processing for patterning or coating
- H05K2203/0108—Male die used for patterning, punching or transferring
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/18—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material
- H05K3/181—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using precipitation techniques to apply the conductive material by electroless plating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K71/00—Manufacture or treatment specially adapted for the organic devices covered by this subclass
- H10K71/821—Patterning of a layer by embossing, e.g. stamping to form trenches in an insulating layer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49126—Assembling bases
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Health & Medical Sciences (AREA)
- General Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Life Sciences & Earth Sciences (AREA)
- Environmental Sciences (AREA)
- Manufacturing Of Printed Wiring (AREA)
Description
120 絶縁層 130、131 無電解銅鍍金層
140、141 電解銅鍍金層 150 回路パターン
201〜209 金型 A 回路パターンの溝
Claims (2)
- (A)それぞれ回路パターンに対応するパターンが形成されている多数の金型および絶縁層が積層されたベース基板を整列させる工程と、
(B)前記絶縁層に前記多数の金型から転写させて、前記絶縁層を硬化させる工程と、
(C)前記絶縁層から前記金型を分離させることで、前記絶縁層に前記回路パターンの溝を形成する工程と、
(D)前記絶縁層及び前記回路パターンの溝内部に無電解導電層を形成する工程と、
(E)前記無電解導電層に電解メッキ層を形成する工程と、及び
(F)前記絶縁層が露出されるまで、前記無電解導電層及び電解メッキ層を研磨する工程を含み、
前記(C)工程の前記絶縁層から前記金型を分離させる工程は前記絶縁層から一つ以上の金型を順次に分離させることを特徴とするインプリント法を利用した印刷回路基板の製造方法。 - 前記(B)工程の前記絶縁層に前記多数の金型から転写させる工程と前記絶縁層を硬化させる工程が同時に成り立つことを特徴とする請求項1に記載のインプリント法を利用した印刷回路基板の製造方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020050032701A KR100632553B1 (ko) | 2005-04-20 | 2005-04-20 | 임프린트법을 이용한 인쇄회로기판의 제조방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006303438A JP2006303438A (ja) | 2006-11-02 |
JP4191740B2 true JP4191740B2 (ja) | 2008-12-03 |
Family
ID=37187356
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006019262A Expired - Fee Related JP4191740B2 (ja) | 2005-04-20 | 2006-01-27 | インプリント法を利用した印刷回路基板の製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7666292B2 (ja) |
JP (1) | JP4191740B2 (ja) |
KR (1) | KR100632553B1 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070200276A1 (en) * | 2006-02-24 | 2007-08-30 | Micron Technology, Inc. | Method for rapid printing of near-field and imprint lithographic features |
CN102265714B (zh) | 2008-12-22 | 2014-05-14 | 富士通株式会社 | 电子部件及其制造方法 |
JP2010171170A (ja) * | 2009-01-22 | 2010-08-05 | Hitachi Cable Ltd | 銅回路配線基板およびその製造方法 |
CN116936470B (zh) * | 2023-09-15 | 2023-12-15 | 季华实验室 | 一种循环印刷式集成电路制备方法 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4912844A (en) * | 1988-08-10 | 1990-04-03 | Dimensional Circuits Corporation | Methods of producing printed circuit boards |
JPH063515A (ja) * | 1992-06-22 | 1994-01-14 | Toppan Printing Co Ltd | 転写箔の製造方法および装置ならびにその転写箔を用いた情報記録媒体の製造方法 |
JP2001230526A (ja) | 2000-02-14 | 2001-08-24 | Sony Corp | 実装基板の製造方法及びそれにより得られた実装基板 |
JP2001320150A (ja) | 2000-02-29 | 2001-11-16 | Mitsui Chemicals Inc | スタンパを使った配線基板の製造方法及び配線基板 |
JP2001347529A (ja) | 2000-06-06 | 2001-12-18 | Mitsui Chemicals Inc | 配線基板製造用スタンパ及びスタンパの製造方法 |
US7211214B2 (en) * | 2000-07-18 | 2007-05-01 | Princeton University | Laser assisted direct imprint lithography |
US6730617B2 (en) * | 2002-04-24 | 2004-05-04 | Ibm | Method of fabricating one or more tiers of an integrated circuit |
JP2004152934A (ja) | 2002-10-30 | 2004-05-27 | Mitsui Chemicals Inc | 回路基板およびその製造方法 |
US7637008B2 (en) * | 2002-12-18 | 2009-12-29 | Intel Corporation | Methods for manufacturing imprinted substrates |
US6974775B2 (en) * | 2002-12-31 | 2005-12-13 | Intel Corporation | Method and apparatus for making an imprinted conductive circuit using semi-additive plating |
JP4317375B2 (ja) * | 2003-03-20 | 2009-08-19 | 株式会社日立製作所 | ナノプリント装置、及び微細構造転写方法 |
JP2004349357A (ja) | 2003-05-21 | 2004-12-09 | Matsushita Electric Works Ltd | 多層プリント配線板の製造方法 |
JP2004356255A (ja) | 2003-05-28 | 2004-12-16 | Cluster Technology Co Ltd | 高密度配線基板の製造方法 |
KR100604819B1 (ko) * | 2003-06-12 | 2006-07-28 | 삼성전자주식회사 | 반도체 패키지용 배선 기판, 그 제조방법 및 이를 이용한반도체 패키지 |
-
2005
- 2005-04-20 KR KR1020050032701A patent/KR100632553B1/ko not_active IP Right Cessation
-
2006
- 2006-01-17 US US11/334,240 patent/US7666292B2/en not_active Expired - Fee Related
- 2006-01-27 JP JP2006019262A patent/JP4191740B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20060240360A1 (en) | 2006-10-26 |
US7666292B2 (en) | 2010-02-23 |
KR100632553B1 (ko) | 2006-10-11 |
JP2006303438A (ja) | 2006-11-02 |
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