JP4169484B2 - 磁気抵抗メモリアレイの自己試験システム - Google Patents

磁気抵抗メモリアレイの自己試験システム Download PDF

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Publication number
JP4169484B2
JP4169484B2 JP2001028595A JP2001028595A JP4169484B2 JP 4169484 B2 JP4169484 B2 JP 4169484B2 JP 2001028595 A JP2001028595 A JP 2001028595A JP 2001028595 A JP2001028595 A JP 2001028595A JP 4169484 B2 JP4169484 B2 JP 4169484B2
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test
circuit
memory
array
coupled
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Japanese (ja)
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JP2001273799A5 (enExample
JP2001273799A (ja
Inventor
フレデリック・エー・ペルナー
ケネス・ジェイ・エルドレッジ
ラング・ティ・トラン
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50Marginal testing, e.g. race, voltage or current testing
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/02Detection or location of defective auxiliary circuits, e.g. defective refresh counters
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/44Indication or identification of errors, e.g. for repair
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C27/00Electric analogue stores, e.g. for storing instantaneous values
    • G11C27/02Sample-and-hold arrangements

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  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Tests Of Electronic Circuits (AREA)
JP2001028595A 2000-02-04 2001-02-05 磁気抵抗メモリアレイの自己試験システム Expired - Fee Related JP4169484B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/498588 2000-02-04
US09/498,588 US6584589B1 (en) 2000-02-04 2000-02-04 Self-testing of magneto-resistive memory arrays

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JP2001273799A JP2001273799A (ja) 2001-10-05
JP2001273799A5 JP2001273799A5 (enExample) 2005-07-21
JP4169484B2 true JP4169484B2 (ja) 2008-10-22

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JP2001028595A Expired - Fee Related JP4169484B2 (ja) 2000-02-04 2001-02-05 磁気抵抗メモリアレイの自己試験システム

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US (1) US6584589B1 (enExample)
EP (1) EP1132924A3 (enExample)
JP (1) JP4169484B2 (enExample)
CN (1) CN1252724C (enExample)
HK (1) HK1041361A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8496091B2 (en) 2008-07-23 2013-07-30 Mitsubishi Electric Corporation Elevator car layout information editing system, destination information input device, display device and edition operating device

Families Citing this family (64)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002299575A (ja) * 2001-03-29 2002-10-11 Toshiba Corp 半導体記憶装置
US7079130B2 (en) * 2001-05-09 2006-07-18 Clare Micronix Integrated Systems, Inc. Method for periodic element voltage sensing to control precharge
US6594606B2 (en) * 2001-05-09 2003-07-15 Clare Micronix Integrated Systems, Inc. Matrix element voltage sensing for precharge
US7079131B2 (en) * 2001-05-09 2006-07-18 Clare Micronix Integrated Systems, Inc. Apparatus for periodic element voltage sensing to control precharge
DE10133689C2 (de) * 2001-07-11 2003-12-18 Infineon Technologies Ag Testverfahren und Testvorrichtung für elektronische Speicher
US7036068B2 (en) 2001-07-25 2006-04-25 Hewlett-Packard Development Company, L.P. Error correction coding and decoding in a solid-state storage device
US20030023922A1 (en) * 2001-07-25 2003-01-30 Davis James A. Fault tolerant magnetoresistive solid-state storage device
US6574130B2 (en) 2001-07-25 2003-06-03 Nantero, Inc. Hybrid circuit having nanotube electromechanical memory
US6981196B2 (en) 2001-07-25 2005-12-27 Hewlett-Packard Development Company, L.P. Data storage method for use in a magnetoresistive solid-state storage device
US20030169241A1 (en) * 2001-10-19 2003-09-11 Lechevalier Robert E. Method and system for ramp control of precharge voltage
WO2003034391A2 (en) * 2001-10-19 2003-04-24 Clare Micronix Integrated Systems, Inc. Method and system for adjusting the voltage of a precharge circuit
WO2003034390A2 (en) * 2001-10-19 2003-04-24 Clare Micronix Integrated Systems, Inc. Precharge circuit and method for passive matrix oled display
JP4073690B2 (ja) 2001-11-14 2008-04-09 株式会社ルネサステクノロジ 薄膜磁性体記憶装置
JP4698715B2 (ja) * 2002-02-04 2011-06-08 ルネサスエレクトロニクス株式会社 薄膜磁性体記憶装置
WO2003069293A1 (de) * 2002-02-14 2003-08-21 Siemens Aktiengesellschaft Verfahren zur bestimmung des elektrischen widerstands einer elektrischen zuleitung zu sensorelementen sowie sensoranordnung
US6801471B2 (en) * 2002-02-19 2004-10-05 Infineon Technologies Ag Fuse concept and method of operation
US6973604B2 (en) 2002-03-08 2005-12-06 Hewlett-Packard Development Company, L.P. Allocation of sparing resources in a magnetoresistive solid-state storage device
US7058849B2 (en) * 2002-07-02 2006-06-06 Micron Technology, Inc. Use of non-volatile memory to perform rollback function
JP2004055001A (ja) 2002-07-18 2004-02-19 Renesas Technology Corp 記憶装置
US6954392B2 (en) 2003-03-28 2005-10-11 Micron Technology, Inc. Method for reducing power consumption when sensing a resistive memory
US6870784B2 (en) * 2003-05-28 2005-03-22 Micron Technology, Inc. Integrated charge sensing scheme for resistive memories
US7042783B2 (en) * 2003-06-18 2006-05-09 Hewlett-Packard Development Company, L.P. Magnetic memory
JP3866701B2 (ja) * 2003-08-25 2007-01-10 株式会社東芝 磁気ランダムアクセスメモリ及びそのテスト方法
US7031866B1 (en) * 2003-11-05 2006-04-18 Virage Logic Corp. System and method for testing a memory
US7472330B2 (en) * 2003-11-26 2008-12-30 Samsung Electronics Co., Ltd. Magnetic memory which compares compressed fault maps
US6999366B2 (en) * 2003-12-03 2006-02-14 Hewlett-Packard Development Company, Lp. Magnetic memory including a sense result category between logic states
US7370260B2 (en) * 2003-12-16 2008-05-06 Freescale Semiconductor, Inc. MRAM having error correction code circuitry and method therefor
US7085183B2 (en) * 2004-07-13 2006-08-01 Headway Technologies, Inc. Adaptive algorithm for MRAM manufacturing
US7360112B2 (en) * 2005-02-07 2008-04-15 International Business Machines Corporation Detection and recovery of dropped writes in storage devices
GB0507912D0 (en) * 2005-04-20 2005-05-25 Ibm Disk drive and method for protecting data writes in a disk drive
US8281221B2 (en) * 2005-10-18 2012-10-02 Nec Corporation Operation method of MRAM including correcting data for single-bit error and multi-bit error
US7260004B2 (en) * 2006-01-12 2007-08-21 International Busniess Machines Corporation Method and apparatus for increasing yield in a memory circuit
US7562273B2 (en) * 2006-06-02 2009-07-14 International Business Machines Corporation Register file cell with soft error detection and circuits and methods using the cell
US7872645B2 (en) * 2006-12-28 2011-01-18 Aptina Imaging Corporation On-chip test system and method for active pixel sensor arrays
WO2008133087A1 (ja) * 2007-04-17 2008-11-06 Nec Corporation 半導体記憶装置及びその動作方法
US7778070B2 (en) * 2007-06-29 2010-08-17 Qimonda Ag Memory with dynamic redundancy configuration
US7898885B2 (en) * 2007-07-19 2011-03-01 Micron Technology, Inc. Analog sensing of memory cells in a solid state memory device
US20090103350A1 (en) * 2007-10-18 2009-04-23 Michael Kund Method of Testing an Integrated Circuit, Method of Manufacturing an Integrated Circuit, and Integrated Circuit
US7609579B2 (en) * 2007-11-21 2009-10-27 Etron Technology Inc. Memory module with failed memory cell repair function and method thereof
US7639527B2 (en) * 2008-01-07 2009-12-29 Macronix International Co., Ltd. Phase change memory dynamic resistance test and manufacturing methods
WO2010125941A1 (ja) * 2009-04-28 2010-11-04 日本電気株式会社 磁気抵抗記憶装置のスクリーニング方法
US8329480B2 (en) * 2010-09-28 2012-12-11 Macronix International Co., Ltd. Test pattern for detecting piping in a memory array
US8750031B2 (en) * 2011-12-16 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Test structures, methods of manufacturing thereof, test methods, and MRAM arrays
JP5727948B2 (ja) * 2012-01-16 2015-06-03 株式会社東芝 半導体記憶装置
US9069719B2 (en) 2012-02-11 2015-06-30 Samsung Electronics Co., Ltd. Method and system for providing a smart memory architecture
US9679664B2 (en) 2012-02-11 2017-06-13 Samsung Electronics Co., Ltd. Method and system for providing a smart memory architecture
CN102818985B (zh) * 2012-09-10 2014-09-24 中国航空工业集团公司第六三一研究所 多路地/开离散量输入信号的bit测试电路
US8929167B2 (en) * 2013-01-31 2015-01-06 Qualcomm Incorporated MRAM self-repair with BIST logic
US9875810B2 (en) * 2013-07-24 2018-01-23 Microsoft Technology Licensing, Llc Self-identifying memory errors
US9348697B2 (en) 2013-09-10 2016-05-24 Kabushiki Kaisha Toshiba Magnetic random access memory
US9455014B1 (en) 2015-03-19 2016-09-27 Qualcomm Incorporated Adjusting resistive memory write driver strength based on write error rate (WER) to improve WER yield, and related methods and systems
WO2018005187A1 (en) * 2016-07-01 2018-01-04 Nantero, Inc. Methods for error correction with resistive change element arrays
US10387244B2 (en) 2016-07-01 2019-08-20 Nantero, Inc. Methods for error correction with resistive change element arrays
CN110082672B (zh) * 2018-01-25 2020-09-11 大唐移动通信设备有限公司 一种芯片内逻辑模型的测试方法及装置
CN112041928B (zh) 2018-04-30 2025-01-28 慧与发展有限责任合伙企业 忆阻器交叉杆阵列中模型/权重编程的加速
CN111223518B (zh) * 2018-11-27 2021-08-20 中电海康集团有限公司 用于阻性存储单元的测试结构及耐久性测试方法
US11862271B2 (en) * 2018-12-17 2024-01-02 Arm Limited Memory testing techniques
CN112230112B (zh) * 2019-06-28 2024-08-23 中电海康集团有限公司 测试结构和测试方法
CN112259151B (zh) * 2019-07-22 2022-06-24 中电海康集团有限公司 Mram阵列的测试电路
CN112259153B (zh) * 2019-07-22 2022-06-24 中电海康集团有限公司 Mram阵列的测试电路
KR20210109085A (ko) 2020-02-26 2021-09-06 삼성전자주식회사 메모리 장치에 대한 테스트 방법, 메모리 장치를 테스트하는 테스트 장치의 동작 방법, 및 셀프-테스트 기능을 구비한 메모리 장치
CN114267405B (zh) * 2020-09-16 2023-08-22 长鑫存储技术有限公司 电流测试电路、装置、方法及存储介质
US11482295B2 (en) * 2020-09-25 2022-10-25 Infinitum Solutions, Inc. Testing magnetoresistive random access memory for low likelihood failure
CN112767989A (zh) * 2021-01-06 2021-05-07 波平方科技(杭州)有限公司 新型存储器测试结构

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2061674A1 (de) 1969-12-30 1971-07-01 Honeywell Inf Systems Prufschaitung zum Überprüfen von elektronischen Speichern
US3655959A (en) 1970-08-17 1972-04-11 Computer Test Corp Magnetic memory element testing system and method
US4236231A (en) * 1979-10-09 1980-11-25 Harris Corporation Programmable threshold switchable resistive memory cell array
JPS57191900A (en) 1981-05-22 1982-11-25 Hitachi Ltd Method for junction destructive prom test
US4718042A (en) 1985-12-23 1988-01-05 Ncr Corporation Non-destructive method and circuit to determine the programmability of a one time programmable device
JP2558904B2 (ja) * 1990-01-19 1996-11-27 株式会社東芝 半導体集積回路
US5117426A (en) * 1990-03-26 1992-05-26 Texas Instruments Incorporated Circuit, device, and method to detect voltage leakage
US5233614A (en) * 1991-01-07 1993-08-03 International Business Machines Corporation Fault mapping apparatus for memory
US5420819A (en) * 1992-09-24 1995-05-30 Nonvolatile Electronics, Incorporated Method for sensing data in a magnetoresistive memory using large fractions of memory cell films for data storage
US5640343A (en) * 1996-03-18 1997-06-17 International Business Machines Corporation Magnetic memory array using magnetic tunnel junction devices in the memory cells
US5952833A (en) 1997-03-07 1999-09-14 Micron Technology, Inc. Programmable voltage divider and method for testing the impedance of a programmable element
US6259644B1 (en) * 1997-11-20 2001-07-10 Hewlett-Packard Co Equipotential sense methods for resistive cross point memory cell arrays
US5930164A (en) 1998-02-26 1999-07-27 Motorola, Inc. Magnetic memory unit having four states and operating method thereof
US6115763A (en) * 1998-03-05 2000-09-05 International Business Machines Corporation Multi-core chip providing external core access with regular operation function interface and predetermined service operation services interface comprising core interface units and masters interface unit
US6097625A (en) * 1998-07-16 2000-08-01 International Business Machines Corporation Magnetic random access memory (MRAM) array with magnetic tunnel junction (MTJ) cells and remote diodes

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8496091B2 (en) 2008-07-23 2013-07-30 Mitsubishi Electric Corporation Elevator car layout information editing system, destination information input device, display device and edition operating device

Also Published As

Publication number Publication date
EP1132924A3 (en) 2002-12-04
JP2001273799A (ja) 2001-10-05
CN1252724C (zh) 2006-04-19
US6584589B1 (en) 2003-06-24
EP1132924A2 (en) 2001-09-12
HK1041361A1 (zh) 2002-07-05
CN1317797A (zh) 2001-10-17

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