JP4168532B2 - PLL signal processing circuit and digital video tape recording / reproducing apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a PLL signal processing circuit and the digital video tape recording and reproducing apparatus, further in particular, PLL signal processing circuit satisfying both stability during high-speed pull-in property and constant during the transition and such PLL signal processing The present invention relates to a digital video tape recording / reproducing apparatus having a circuit .
[0002]
[Prior art]
A digital VTR is a circuit that combines a phase comparator and a voltage-controlled oscillator to obtain an output that is phase-synchronized with an input wave using a negative feedback loop of integral control type with respect to frequency, and a phase locked loop (PLL). A synchronization loop) is provided in the signal processing unit, and a signal synchronized with an external video signal is output.
[0003]
Here, a circuit configuration of the PLL provided in the signal processing unit of the digital VTR will be described with reference to FIG. FIG. 3 is a block diagram showing a circuit configuration of the PLL.
As shown in FIG. 3, the internal synchronization signal generator (hereinafter referred to as PLL) 10 includes an externally input synchronization reference signal (1-a) and an internal frame reference signal (1-d) output from the PLL 10. And a phase comparison unit 12 that compares the phases with each other and outputs an initial phase error (1-b), and calculates and outputs a phase difference correction value (1-c) based on the initial phase error signal (1-b). An error calculating unit 14 that generates the internal frame reference signal (1-d) from the phase difference correction value (1-c) output from the error calculating unit 14 and outputs the internal frame reference signal (1-d). Yes.
[0004]
FIG. 4 shows waveforms of the synchronization reference signal (1-a) input from the outside and the internal frame reference signal (1-d) output to the outside, respectively. As shown in FIG. 4, when the rising edges of the pulses coincide with each other, the phase is in the locked state, and the PLL operates so as to maintain the state.
The PLL 10 described above operates so as to output the frame reference signal (1-d) whose phase is locked to the synchronous reference signal (1-a). The configuration of one period of the frame reference signal (1-d) is as shown in FIG.
In other words, the standard frame period (NTSC: 33.3 ms / PAL: 40 ms), which is a fixed part, is added with a phase difference correction value (1-c), which is a fluctuation part.
[0005]
Here, with reference to FIG. 6, the structure and function of the conventional error calculation unit 14 provided in the PLL will be described. FIG. 6 is a circuit diagram showing a configuration of the error calculation unit 14 provided in the conventional PLL 10.
A conventional error calculation unit 14 provided in the PLL performs digital signal processing using a microcomputer. As shown in FIG. 6, a limiter 18, two first processing systems 20 following the limiter 18, and The second processing system 22, an adder 24 for adding the data of the first and second processing systems 20 and 22, and a limiter 26 are provided, and an initial phase error signal (1-b) output from the phase comparator 12 is provided. ), That is, the phase difference data is calculated and the phase difference correction value (1-c) is output.
[0006]
The first processing system 20 is configured as an integral term calculation system, and includes an amplifier 28 with a gain adjuster, adjusts the gain, adds the data one sample before, and performs an integral calculation to obtain integral term data ( 2-a) is output. The second processing system 22 is configured as a proportional term calculation system performs gain adjustment comprises a gain adjuster with an amplifier 30, and outputs a proportional term data (2-b).
And integral term data output from the first processing system 20 (2-a), outputted proportional term data from the second processing system 22 (2-b) are added by the adder 24, a further limiter 26 After that, the phase difference correction value (1-c) is output.
[0007]
[Problems to be solved by the invention]
By the way, there are analog (line input) and digital VTR digital (IEEE 1394 input) for video signal input, and a large memory such as a shuffling memory is provided in the analog input unit so that synchronization is not possible. It doesn't matter so much.
[0008]
However, since there is no large-capacity memory in the digital input unit, there is little circuit block margin in the signal processing unit, so that signal processing does not fail, that is, in a synchronized state, that is, an external frame reference signal and an internal frame The required specifications for the phase difference from the reference signal are strict. In other words, it is difficult to display a normal image unless it is closer to the lock point than analog input.
Therefore, in the conventional digital VTR, because the pull-in time of the synchronous PLL is long when the video signal is input or when the video signal appears again after being interrupted once, the digital input side is Compared to the analog input side, it takes more time to output a normal image.
[0009]
Therefore, an object of the present invention is a PLL that can maintain the stability at the steady state and reduce the pull-in time at the transition time, and the digital that can quickly output the image at the transition time while maintaining the stability at the steady time. It is to provide a VTR.
[0010]
[Means for Solving the Problems]
The present inventor studied the problems of the conventional PLL and found the following.
That is, the PLL having the error calculation unit as described above exhibits a stable behavior if the gain is appropriately selected. However, for the following reasons, when a signal or data is drawn from a state in which the phase is greatly shifted, a wasteful operation may occur.
That is, because of the extra data accumulated in the integral term calculation system of the two processing systems, the frequency of the reference signal deviates, and even if it approaches the lock point, it does not converge as it is, and after passing once A so-called overshoot phenomenon that locks occurs. As a result, it takes extra time for the pull-in.
In order to solve this problem, it is sufficient that extra data is not accumulated in the integral term calculation system. However, the configuration becomes unnecessarily complicated, and there is a risk of affecting the performance in the steady state.
[0011]
Therefore, the present inventor has two systems of an error calculation system for locking at normal time and an error calculation system of “proportional term + difference between reference and reference frequency” format for pulling in at transition, depending on conditions, The present invention has been completed through repeated research with the idea of switching between these two systems to achieve both high-speed pull-in during transition and stability during steady-state.
[0012]
In order to achieve the above object, a PLL signal processing circuit according to the present invention includes an error calculation processing circuit that calculates and outputs a phase difference correction value based on phase difference data, and outputs a signal output from the error calculation processing circuit. In a PLL signal processing circuit that generates and outputs an internal frame reference signal based on a phase difference correction value,
Error calculation processing circuit
An integral term arithmetic circuit that outputs integral term data of phase difference data ;
A proportional term calculation circuit for outputting a proportional term data of the phase difference data,
A difference calculation circuit for calculating and outputting difference data between the synchronization reference signal and the reference frequency of the TV signal;
A changeover switch for switching between the integral term arithmetic circuit and the difference arithmetic circuit ;
Depending on the switching of the changeover switch, the integral term calculation circuit is integral term data and adds the outputted proportional term data from the proportional term calculation circuit output from or proportional term and the differential data output from the difference calculation circuit by adding the proportional term data output from the arithmetic circuit, and an adder for outputting the phase difference correction value,
The changeover switch switches to the integral term arithmetic circuit when the phase difference between the synchronization reference signal and the internal frame reference signal is smaller than the set value, and when the phase difference between the synchronization reference signal and the internal frame reference signal is larger than the set value, the difference It is characterized by switching to an arithmetic circuit .
[0013]
In the present invention, a PLL signal processing circuit that achieves both fast pull-in at transition and stability at steady state by switching between an integral term arithmetic circuit and a difference arithmetic circuit according to the magnitude of the phase difference using a changeover switch. Can be realized.
The changeover switch may be a soft switch formed on a microcomputer software program.
[0014]
By providing the signal processing unit with the PLL signal processing circuit according to the present invention, it is possible to realize a digital videotape recording / reproducing apparatus capable of quickly outputting an image even during transition while maintaining stability in a steady state.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described specifically and in detail with reference to the accompanying drawings.
Embodiment Example This embodiment example is an example of an embodiment of a PLL according to the present invention, and FIG. 1 is a circuit showing a configuration of an error calculation unit provided in the PLL of the embodiment.
In addition to the configuration of the conventional error calculation unit 14 shown in FIG. 6, the error calculation unit 40 provided in the PLL of this embodiment example includes a difference calculation system 42 and a phase difference between the synchronization reference signal and the internal frame reference signal. The first changeover switch (SW1) 44 and the second changeover switch (switching from the first processing system 20 (see FIG. 6) to the difference calculation system 42 or from the difference calculation system 42 to the first processing system 20 according to the size of SW2) 46 is provided.
[0016]
The difference calculation system 42 is a calculation system that calculates a difference between the synchronization reference signal and the reference frequency of the TV signal (NTSC: 33.3 msec, PAL: 40 msec) and outputs difference data (2-c).
The first change-over switch (SW1) 44 and the second change-over switch (SW2) 46 are soft switches formed on the software program of the microcomputer, and the error calculation unit 40 operates under the first condition in FIG. Is configured such that the difference data (2-c) is input from the difference calculation system 42 to the adder 24 under the second condition.
[0017]
In the error calculation unit 40 of the present embodiment, first, a window having a predetermined phase difference is provided with respect to the synchronization reference signal, and whether the frame reference signal output from the PLL is in that window, that is, the synchronization reference signal. The phase difference between the signal and the internal frame reference signal is smaller than the set value, or the output frame reference signal is outside the window, that is, the phase difference between the synchronization reference signal and the internal frame reference signal is greater than the set value. The processing system is switched by the first and second change-over switches 44 and 46 depending on whether it is larger.
More specifically, as shown in FIGS. 2A and 2B, whether the rising edge of the frame reference signal is located with respect to the rising edge of the synchronous reference signal determines whether it is inside or outside the window.
[0018]
The first condition refers to a state in which the phase is locked. As shown in FIG. 2A, the frame reference signal is in the window, and includes a first changeover switch (SW1) 44, and a second changeover switch. Both (SW2) 46 are turned on to the first processing system 20 side so as to constitute the conventional error calculation unit 14.
Next, when the phase of the synchronization reference signal suddenly changes for some reason, the rising edge of the frame reference signal goes out of the window as shown in FIG. This state is referred to as a second condition.
Under this second condition, the first changeover switch (SW1) 44 and the second changeover switch (SW2) 46 both fall to the opposite side and turn on not on the first processing system 20 but on the difference calculation system 20 side. Then, difference data (2-c) between the period of the synchronous reference signal and the standard frame period of the TV signal is added to the data (2-b) of the proportional term calculation system.
[0019]
By doing so, the pull-in operation is quickly performed only by the second processing system which is a proportional term calculation system, and does not include a slow-tracking component of the integral term calculation system like the first processing system 20. Thus, no large overshoot phenomenon occurs, and the internal frame reference signal is immediately pulled into the window.
When the internal frame reference signal is drawn into the window, the first changeover switch (SW1) 44 and the second changeover switch (SW2) 46 are turned on to the first processing system 20 side, and the stable lock state is maintained as it is. To do.
At this time, since the first changeover switch (SW1) 44 has been turned on to the side of the difference calculation system 42 so far, the same value is inherited as the integral term data, and the state transition is smoothly performed.
As can be seen from FIG. 5, when the frequency of the synchronization reference and the frequency of the frame reference signal are matched, the phase difference correction value (1-c) and the difference data (2-c) have the same value. Therefore, the validity of replacing with the difference data (2-c) from the standard signal instead of the integral term during the transition is clear.
[0020]
【The invention's effect】
According to the present invention, there are two systems of an error calculation system for locking at normal time and an error calculation system of “proportional term + difference between reference and reference frequency” for pulling in at the time of transition, and the phase difference can be increased or decreased. Accordingly, by switching these two systems, the pull-in time at the transition can be shortened while maintaining the stability at the steady state only by making a slight change to the conventional synchronous PLL.
In addition, by providing the digital video tape recording / reproducing apparatus with the PLL signal processing circuit according to the present invention, the rise of the synchronous system can be accelerated even in the digital input system. For example, an image is displayed at the moment when the signal is input. Will be able to.
[Brief description of the drawings]
FIG. 1 is a circuit illustrating a configuration of an error calculation unit provided in a PLL according to an embodiment.
FIGS. 2A and 2B are schematic diagrams illustrating window settings, respectively.
FIG. 3 is a block diagram showing a circuit configuration of a PLL.
FIG. 4 is a waveform diagram showing waveforms of a synchronization reference signal (1-a) input from the outside and an internal frame reference signal (1-d) output to the outside.
FIG. 5 is a schematic diagram showing a configuration of one period of a frame reference signal.
FIG. 6 is a circuit diagram showing a configuration of an error calculation unit provided in a conventional PLL.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 ... Internal synchronizing signal generation part, PLL, 12 ... Phase comparison part, 14 ... Conventional error calculation part, 16 ... Frame reference pulse generation part, 18 ... Limiter, 20 ... First processing system, 22 ...... Second processing system, 24 ...... Adder, 26 ...... Limiter, 28, 30... Amplifier with gain adjuster, 40 ....... Error calculation unit provided in PLL of embodiment, 42. 44... First changeover switch (SW1), 46... Second changeover switch (SW2).

Claims (2)

It calculates a phase difference correction value based on the phase difference data, includes an error processing circuit for outputting, to generate an internal frame reference signal based on the phase difference correction value output from the error processing circuit, and outputs, In the PLL signal processing circuit ,
The error calculation processing circuit is
An integral term arithmetic circuit that outputs integral term data of the phase difference data ;
A proportional term calculation circuit for outputting a proportional term data of the phase difference data,
A difference calculation circuit for calculating and outputting difference data between the synchronization reference signal and the reference frequency of the TV signal;
A changeover switch for switching between the difference arithmetic circuit and the integral term calculation circuit,
Depending on the switching of the changeover switch, the output outputted from the integral term calculation circuit was the integral term data from the proportional term calculation circuit a ratio by adding the Examples section data, or output from the difference calculation circuit difference data and the proportional term calculation circuit adds the outputted proportional term data from, and an adder for outputting the phase difference correction value,
The switching switch, wherein when the phase difference between the sync reference signal and the internal frame reference signal is less than the set value is switched to the integral term calculation circuit, the phase difference between the synchronous reference signal and the internal frame reference signal is the when larger than the set value, PLL signal processing circuit, characterized in that switching to the difference calculation circuit. A digital videotape recording / reproducing apparatus comprising the PLL signal processing circuit according to claim 1 in a signal processing unit.

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