JP2805069B2 - AFC circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an AFC circuit.

[Summary of the Invention]

The present invention relates to an AFC circuit for controlling a voltage controlled oscillator by an output signal of a phase comparator, a reference signal generation circuit for generating a reference signal having a level corresponding to a tape speed, and a level of an output signal of the phase comparator. A circuit for comparing the level of the reference signal, and switching means for selectively inputting the output signal of the phase comparator and the reference signal to the voltage-controlled oscillator based on the result of the comparison. It is possible to suppress the disturbance of the screen during the period from the start to the return, and to quickly return.

[Conventional technology]

For example, a reproduced video signal from a VTR includes a time axis error, and a time axis correction device is used to remove the error. 7 to 10 show the configuration and operation of a conventional time axis correction device.

FIG. 7 shows an outline of a time axis correction device, in which a reproduced video signal SV through an input terminal 101 is converted by an A / D converter 102.
Is converted into a digital video signal. Since this digital video signal is synchronized with the reproduced video signal SV, the write clock signal having the same time axis error as the reproduced video signal SV
The data is written to the memory 103 by WCK (FIG. 8D).

The written digital video signal is a read clock signal from the read clock generating circuit 104 which has the same frequency as the write clock signal WCK but has no time axis error.
By RCK, the time axis error is read out from the memory 103 and removed.

The digital video signal having no time axis error is converted into an analog video signal by the D / A converter 105. Since the analog video signal does not include the synchronization signal and the burst signal,
After the synchronizing signal and the burst signal are added by the synchronizing signal and burst signal adding circuit 106, the signal is output to an output terminal 107.

The formation circuit 108 of the write clock signal WCK is configured by an AFC circuit. That is, the reproduced video signal SV from the input terminal 101
Is supplied to a sync separation circuit 109 to obtain a reproduced horizontal synchronization signal. The reproduced horizontal synchronization signal is supplied to a phase comparator 110.

The voltage controlled oscillator 111 is for obtaining an oscillation output of a frequency of N × f _H (f _H is a reproduction horizontal synchronization frequency), and the oscillation output is supplied to a frequency divider 112 (1 / N). Divided by The output signal CH (FIG. 8A) of the frequency divider 112 is supplied to the phase comparator 110 and compared with the reproduced horizontal synchronizing signal. Then, the error voltage Ver is supplied to the voltage controlled oscillator 111 through the low-pass filter 113, and the oscillation output is controlled so as to be locked with the reproduced horizontal synchronization signal. That is, the output signal of the voltage controlled oscillator 111 includes the same phase error as the time axis error included in the reproduced video signal SV. The output signal of the voltage controlled oscillator 111 becomes the write clock signal WCK.

A reset type AFC circuit is often used as the write clock signal WCK forming circuit 108 as described above, and a so-called trapezoidal wave sample-and-hold type can be used as a phase comparator of the AFC circuit.

In the case of the phase comparison of the trapezoidal wave sample and hold method, the phase comparator 110 based on the signal CH (FIG. 8A) from the frequency divider 112 is used.
, A trapezoidal wave SL (FIG. 8B) is formed.

On the other hand, the slope portion of the trapezoidal wave SL is sampled by the sampling pulse SP (FIG. 8C) formed based on the horizontal synchronization signal. Then, this sampling value is supplied to the voltage controlled oscillator 111 via the low-pass filter 113, and the oscillation frequency is controlled.

The pulse SP is supplied to the voltage controlled oscillator 111 and the frequency divider 112 as a reset pulse. The voltage controlled oscillator 111
During the pulse width period of the reset pulse, the oscillation output is stopped and reset, and the counter of the frequency divider 112 is reset.

[Problems to be solved by the invention]

By the way, when a high-speed reproduction such as ± 35 times speed is demanded recently, a change in the frequency of the reproduced horizontal synchronizing signal is widened to 6 to 22 MHz, and a pseudo lock may occur.

Pseudo-locking occurs when the recording part is rushed at the highest speed during fast-forwarding or when returning from being disturbed by disturbance. For example, when there is no signal in the normal mode, the output signal CH shown in FIG. 9A is supplied from the frequency divider 112 to the phase comparator 110, where
When the trapezoidal wave SL shown in FIG. B is formed, the fast forward mode is set, and the pulse shown in FIG.
When SP is supplied from the sync separation circuit 109 to the phase comparator 110, every other pulse SP samples the slope portion of the trapezoidal wave SL, and a pseudo lock occurs.

Also, when the recording portion is rushed at the highest speed during rewinding or when the oscillation frequency of the oscillator 111 becomes low due to disturbance, the output signal CH for phase comparison of the AFC circuit is used because the frequency divider 112 is of a reset type. Is reset by the pulse SP before rising, and the pseudo lock continues. For example, when there is no signal in the normal mode, an output signal CH as shown in FIG. 10A is supplied from the frequency divider 112 to the phase comparator 110, and here, FIG.
When the trapezoidal wave SL as shown in Fig. 10 is formed, the pulse is switched to the rewind mode and the cycle is short as shown in Fig. 10C.
When SP is supplied from the synchronization separation circuit 109 to the phase comparator 110, the first pulse of the pulse SP samples the slope portion of the trapezoidal wave SL, and this sampled value is supplied to the voltage controlled oscillator 111, and the voltage controlled oscillator 111 Outputs a clock signal WCK as shown in FIG. 10D.

However, the second pulse of the pulse SP is shown in FIG.
10 As shown in FIG. B, the high-level portion of the trapezoidal wave SL sampled by the first pulse is sampled, and the sampled value is supplied to the voltage-controlled oscillator 111. As a result, the interval of the clock signal WCK gradually increases as shown in FIG. 10D. The frequency divider 112 counts, for example, 910 pulses (clock signal WCK) in 1H, counts 455 pulses, and outputs a high level, and further counts 435 pulses to output a low level output signal CH. When the second pulse (reset pulse) of the pulse SP is generated, it is just before reaching 455 and is reset in that state, so that the output signal CH maintains the low level as shown in FIG. 10E. Remains.

Therefore, a trapezoidal wave formed based on this output signal CH
SL also maintains the high level as shown in FIG. 10F. Next, the third pulse of the pulse SP samples the high-level portion of the trapezoidal wave SL in FIG. 10F, so that the oscillation frequency further decreases, and as a result, the clock signal WCK becomes the first pulse.
0 As shown in FIG. Hereinafter, the same operation is repeated, and the oscillation frequency is gradually reduced, and the oscillation frequency is settled at the limit frequency, that is, where the oscillation frequency does not change even if the voltage is changed any more, and pseudo-locking occurs.

A technology for preventing such a false lock is disclosed in Japanese Patent Application
62-143778.

According to the technology described above, although the pseudo lock is prevented, when the lock is released, the error voltage Ver output from the phase comparator 110 is replaced with a fixed reference voltage, so that the lock during the high-speed reproduction is In the case of departure, rush from a no-signal state, or the like, there is a problem that image shrinkage (at the time of REW), image expansion (at the time of FF), and the like occur until locking again. Further, there is a problem that it takes a certain amount of time to return.

Then, at the time of high-speed reproduction, there is a problem that the above-mentioned disturbed screen continues to be displayed when the phase cannot be compared due to lack of the horizontal synchronizing signal for the phase comparison and cannot be restored.

Further, in consideration of the frequency lock range, the conventional technology has a problem that the reference voltage is fixed, so that the frequency lock range is naturally limited to a narrow range.

Accordingly, an object of the present invention is to prevent the occurrence of image shrinkage and image expansion during high-speed playback, and to achieve an AF that can recover in a short time.
It is to provide a C circuit.

[Means for solving the problem]

The present invention relates to a voltage controlled oscillator that generates a signal having a frequency corresponding to an input voltage, an output signal of the voltage controlled oscillator or a regular phase separated from a reproduced video signal and a phase of a signal formed based on the output signal. A phase comparator for comparing the phase of a signal, wherein in an AFC circuit configured to control a voltage controlled oscillator by an output signal of the phase comparator, a reference for generating a reference signal having a level corresponding to a tape speed. A signal generating circuit, a circuit for comparing the level of the output signal of the phase comparator with the level of the reference signal, and selectively inputting the output signal of the phase comparator and the reference signal to the voltage controlled oscillator based on the result of the comparison Switching means.

[Action]

From the reference signal generation circuit, a reference signal having a level corresponding to the tape speed is supplied to a comparison circuit. On the other hand, in the phase comparator, the horizontal synchronizing signal separated from the video signal and the oscillation output from the voltage controlled oscillator are compared in phase, and the error voltage is supplied to a comparison circuit.

The level of the error voltage is compared with the level of the reference signal. Based on the comparison result, one of the output signal and the reference signal is selectively switched by switching means and input to the voltage controlled oscillator. That is, when the level of the output signal is determined to be abnormal, the reference signal is replaced with an error signal and input to the voltage controlled oscillator.

Since the level of the above-mentioned reference signal changes according to the tape speed and is close to the VCO control error voltage, a high return speed can be realized. Further, in the case of unlocking during high-speed reproduction, entry from a no-signal state, etc., it is possible to prevent image shrinkage, image elongation, and the like from occurring until locking again.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to FIGS. The description of this embodiment is made in the following order.

(A) First Embodiment (A-1) Configuration (A-2) Circuit Operation of Pseudo Lock Correction Circuit (B) Second Embodiment (B-1) Configuration (B-2) Pseudo Lock Correction Circuit (A) First Embodiment FIGS. 1 to 4 are diagrams for explaining the first embodiment.

(A-1) Configuration FIG. 1 is a block diagram of an AFC circuit, FIG. 2 is a timing chart, FIG. 3 is a circuit diagram of a pseudo lock correction circuit, and FIG. Each is shown.

As shown in FIG. 1, the AFC circuit is a horizontal synchronizing signal f _H and the output signal obtained by dividing the oscillation output of the voltage controlled oscillator
This is a PLL that compares phases of f _H ′. The AFC circuit uses two voltage controlled oscillators [described later] for normal speed reproduction and for high speed reproduction (± 15 times or more) in order to reduce frequency fluctuation. Separated from the reproduced video signal horizontal sync signal f _H is supplied to the phase comparator 2 via the terminal 1.

The phase comparator 2 compares the phase of the horizontal synchronizing signal f _H with the output signal f _H ′ from a frequency divider, which will be described later, and supplies the comparison output to the low-pass filter 3.
Error voltage Ver from normal voltage controlled oscillator 4 for normal speed
[Hereinafter referred to as “VCO”], respectively.
Supplied.

VCO4 is used when the tape speed is low, and has little frequency fluctuation and is stable. In this VCO4 for normal speed, the oscillation output (N ·
f _H ') are formed, the oscillation output is supplied to one input terminal of the switch 6 switch.

The pseudo-lock correction circuit 5 detects the loss of lock by comparing the above-described error voltage Ver with the reference voltage Verf. When the error voltage Ver is determined to be abnormal, that is, when the lock is released, the error voltage Ver is replaced with a preset reference voltage Vref. This reference voltage Vref is supplied to the VCO 7 for high-speed reproduction.

The VCO 7 is used at tape speeds of. +-. 15.times. Speed or more, has a wide frequency change range, and switches the VF characteristics according to the tape moving direction as shown in FIG. In VCO7, the oscillation output (N ·
f _H ') are formed, the oscillation output is supplied to the other input terminal of the switch 6 switch.

The changeover switch 6 controls the control signal SNO shown in FIG.
Is high, the VCO 4 is connected to the frequency divider 8, and at the time of high-speed reproduction, the VCO 7 is connected to the frequency divider 8. The oscillation output from the VCO 4 or VCO 7 is supplied from the changeover switch 6 to the frequency divider 8 and taken out from the terminal 9.

The frequency divider 8 divides the above-mentioned oscillation output by (1 / N). The frequency-divided output signal f _H ′ is supplied to the phase comparator 2. The frequency division ratio N is 910 in the case of the NTSC system and 908 in the case of the PAL system.

FIG. 2A shows the tape moving direction and the speed ratio (double speed). In this embodiment, the sign of the speed ratio is + on the fast-forward (FF) side and-on the rewind (REW) side.

FIG. 3 shows an example of the pseudo lock correction circuit 5.

In the configuration shown in FIG. 3, the analog tape speed signal STP supplied from the terminal 11 is supplied to the negative terminals of the comparators 12, 13, 14, 15 via the resistors R1, R2, R3, R4. The tape speed signal STP is formed from a servo signal for controlling the rotation of the reel. The + terminals of the comparators 12 to 15 have comparison voltage forming circuits 16, 17, 1
The comparison voltages Vc1, Vc2, Vc3 and Vc4 are supplied from 8 and 19.

The comparison voltage forming circuit 16 includes a resistor R5 between the terminal 20 and the ground.
R6 are connected in series, and the comparison voltage Vc1 is formed by dividing the power supply voltage Vs (for example, +5 V) applied to the terminal 20 by the resistance ratio. Other comparison voltage forming circuit 1
7, 18, and 19 have the same configuration. The comparison voltage forming circuits 17, 18, and 19 have terminals 21, 22, and 23 and resistors R7, R8, and R, respectively.
The reference voltages Vc2, Vc3, and Vc4 are formed from 9, R10, R11, and R12.

The output signals of comparators 12 and 13 are AND gates 24 and 25
The tape moving direction signal SDR is supplied from the terminal 26 via the inverter 27 to the other terminals of the AND gates 24 and 25. The output signals of AND gates 24 and 25 are connected to transistors Q1 and Q2 via resistors R25 and R26, respectively.
Is supplied to the base.

The output signals of comparators 14 and 15 are connected to transistor Q4,
Supplied to the base of Q5.

The above-described tape moving direction signal SDR is supplied from the terminal 26 to the resistor R13.
To the base of the transistor Q3 and to the other terminal of the EXOR gate 29 of the unlock detection circuit 28. The base terminal of the transistor Q3 and the resistor R1
Between 3, the resistor R14 and the terminal 30 are connected in series,
For example, a power supply voltage Vs of −5 V is applied to the terminal 30.

A power supply voltage Vs (for example, 12 V) is supplied to the terminal 31, and this power supply voltage Vs is supplied to the transistor via a resistor R15 and resistors R16 to R21 connected in parallel to the other end of the resistor R15.
It is supplied to the collectors of Q1 to Q5 respectively. The emitters of the transistors Q1 to Q5 and the other end of the resistor R16 are grounded.

The reference voltage Vref is extracted from the connection point P1 of the above-described resistors R15 and R20. This reference voltage Vref is equal to VC shown in FIG.
A value that is close to the VF characteristic of O7 is selected. For example, when fast-forwarding, if the speed is 35 times faster, information about the horizontal synchronization signal is insufficient, so phase comparison is impossible and locking becomes difficult.In such a case, an image as if locked is projected even in such a case Level to obtain. The reference voltage Vref is supplied to the + terminal of the comparator 32 and the terminal 33b of the changeover switch 33, respectively. On the other hand, the error voltage Ver is supplied from the terminal 38 to the minus terminal of the comparator 32 and the terminal 33a of the changeover switch 33. Negative feedback is applied from the output terminal to the negative terminal of the comparator 32, and a terminal 37 and a resistor R27 are connected in series to the output terminal.

The output signal of the comparator 32 is supplied to one terminal of the EXOR gate 29. The other terminal of the EXOR gate 29 is supplied with a tape moving direction signal SDR. The output signal of the EXOR gate 29 is supplied to one terminal of the AND gate 34, and the other terminal of the AND gate 34 is supplied from the terminal 35 with a speed control signal Ssp which becomes a high level at ± 15 times or more speed. .
The changeover switch 33 is controlled by the output signal of the AND gate 34.

The switch 33 connects the terminals 33c and 33b to take out the reference voltage Vref from the terminal 36 when the output signal of the AND gate 34 is at a high level, and outputs the terminal 33 when the output signal is at a low level.
c, 33a are connected to take out the error voltage Ver from the terminal 36.
(A-2) Regarding the Circuit Operation of the Pseudo-Lock Correction Circuit As shown in FIG. 4, in the range of high-speed reproduction where the tape speed is ± 15 times or more, the error voltage Ver and the reference voltage Vref are generated by the pseudo-lock correction circuit 5. And the detection of loss of lock is performed. When the lock is released, the error voltage Ver is replaced with a preset reference voltage Vref, and the reference voltage Vref is supplied to the VCO 7.

Hereinafter, the reference voltage Vref on the fast-forward side shown in FIG. 4 and the reference voltage Vr on the rewind side shown in FIG.
ef will be described.

An analog tape speed signal STP is supplied from terminals 11 to comparators 12 to 15. In the comparators 12 to 15, the level of the tape speed signal STP and the comparison voltage Vc1
A comparison of the level with Vc4 is performed.

When the tape speed is, for example, near 30 times speed, the output signals of the comparators 12 to 15 are all at the high level. As a result, the transistors Q4 and Q5 are turned on. Also, the terminal
Since the tape moving direction signal SDR supplied from 26 is fast-forwarding, it goes high, and the transistor Q3 is also turned on. On the other hand, transistors Q1 and Q2
It is turned off because the 25 output signals are set to low level.

Therefore, the power supply voltage Vs applied to the terminal 31 is
, A current flows through the resistors R16, R19, R20, and R21. As a result, a voltage drop defined by the product of the parallel composite value of the resistors R16 and R19 to R21 and the current is extracted as the reference voltage Vref1. The reference voltage Vref is set stepwise according to the actual VF characteristic as shown in FIG. 4, and the above-described reference voltage Vref1 is set in the comparator 32 and the changeover switch 33.
Is supplied to the terminal 33b.

When the tape speed is, for example, near +24 times speed, the output signals of the comparators 12, 13, and 15 are all high level, and the output signal of the comparator 14 is low level. As a result, the transistor Q4 is turned on. Also, the transistor Q3 is turned on from the level of the tape movement direction signal SDR.
On the other hand, the transistor Q5 is off because the output signal of the comparator 14 is at low level, and the transistors Q1 and Q2 are off because the output signals of the AND gates 24 and 25 are at low level.

Therefore, the voltage drop caused by the parallel combined value of the resistors R16, R19 and R20 is taken out as the reference voltage Vref2.

When the tape speed is around +5 times speed, the comparator 1
The output signals of 2 and 13 are at high level, and the output signals of comparators 14 and 15 are at low level. As a result, the transistor
Q4 and Q5 are off. Further, the transistors Q1 and Q2 are turned off because the output signals of the AND gates 24 and 25 are at a low level. Only the transistor Q3 is turned on from the level of the tape movement direction signal SDR.

Therefore, a voltage drop caused by the parallel combined value of the resistors R16 and R19 is taken out as the reference voltage Vref3.

When the tape speed is, for example, near -5 times speed, the output signals of the comparators 12 and 13 are high level,
The output signals of 4 and 15 become low level. As a result, the transistors Q4 and Q5 are turned off. Tape movement direction signal S
Since DR is set to the high level by the inverter 27, the output signals of the AND gates 24 and 25 are set to the high level, and the transistors Q1 and Q2 are turned on. The transistor Q3 is turned off because the tape movement direction signal SDR is at a low level.

Therefore, the voltage drop caused by the parallel combination of the resistors R16 to R18 is taken out as the reference voltage Vref4.

When the tape speed is, for example, near -24 times speed, the output signal of the comparator 12 is high level, and the comparators 13 to 15
Is low level. As a result, the transistors Q4 and Q5 are turned off. Since the output signal of the AND gate 24 is at the high level, only the transistor Q1 is on, and the transistor Q2 is off because the output signal of the AND gate 25 is at the low level. Transistor Q3 is
Since the tape movement direction signal SDR is at a low level, the signal is turned off.

Therefore, the voltage drop caused by the parallel combined value of the resistors R16 and R17 is taken out as the reference voltage Vref5.

When the tape speed is near, for example, -30 times speed, the output signals of the comparators 12 to 15 are all at the low level.
As a result, the transistors Q1, Q2, Q4, and Q5 are all turned off. Further, since the tape movement direction signal SDR is at a low level, the transistor Q3 is also turned off.

Therefore, a voltage generated by dividing the power supply voltage Vs by the resistors R15 and R16 is extracted as the reference voltage Vref6.

The situation in which the reference voltage Vref is formed has been described above. However, the reference voltages Vref1 to Vref6 are set stepwise so as to approximate the VF characteristic of the VCO 7 as shown in FIG. . For this reason, at the time of high-speed playback, even if the lock is unlocked, the disturbance of the screen can be suppressed, and the time required to return from the unlocked state can be greatly reduced. And
The frequency lock range expands. Further, in the case of an AFC circuit that resets each H, if the reset criterion (for example, the synchronization signal of the Y signal) is only taken, an image as if the frequency lock due to the loss of H information is impossible or locked. Can be projected.

The comparison / selection of the reference voltage Vref and the error voltage Ver described above is performed as follows.

First, unlock detection is performed based on a comparison between the reference voltage Vref and the error voltage Ver. That is, the comparator
32, the error voltage Ver is supplied, and the reference voltage Vref
Is compared with the error voltage Ver.

In the case of fast-forward, when the error voltage Ver ≧ the reference voltage Vref, it is determined that the lock is lost, and the output signal from the comparator 32 is supplied to the EXOR gate 29. Since the tape movement direction signal SDR is at a high level, the output signal of the EXOR gate 29 is at a high level and supplied to the AND gate 34.

The AND gate 34 outputs a high-level output signal because the high-level output signal is supplied from the EXOR gate 29 and the high-level speed control signal Ssp from the terminal 35, and controls the changeover switch 33. That is, the switch 33 connects the terminals 33b and 33c, and the reference voltage Vref is supplied to the terminal. If the error voltage Ver is smaller than the reference voltage Vref, it is determined that the error voltage Ver is normal.
Is supplied to the terminal 36 as it is.

On the other hand, in the case of rewinding, the error voltage Ver <the reference voltage Vre
At the time of f, it is determined that the lock is released, and the output signal from the comparator 32 is supplied to the EXOR gate 29. Since the tape movement direction signal SDR is at a low level, the output signal of the EXOR gate 29 is at a high level and supplied to the AND gate.

The AND gate supplies a high-level output signal to control the changeover switch 33 as in the case of the fast-forward.
That is, the terminals 33b and 33c of the switch 33 are connected, and the reference voltage Vref is supplied to the terminal 36. In addition, error voltage Ver ≧
In the case of the reference voltage Vref, it is determined to be normal, so the error voltage Ver is supplied to the terminal 36 as it is via the changeover switch 33.

(B) Second Embodiment FIGS. 5 and 6 are diagrams for explaining a second embodiment.
FIG. 5 is a circuit diagram of the pseudo lock correction circuit, and FIG.
The figure shows a correction explanatory diagram of the pseudo lock correction circuit.

(B-1) Configuration The difference between the second embodiment and the first embodiment is that
A linear approximation is made to the VF characteristic curve to set a continuously changing reference voltage Vref, and an allowable range (window) is provided on both sides of the reference voltage Vref. When the voltage Ver exceeds the allowable range, the above-described reference voltage Vref is used instead of the error voltage Ver. The other configurations of the AFC circuit are the same as those of the first embodiment.

FIG. 5 is a circuit diagram of the pseudo lock correction circuit.

In the configuration shown in FIG. 5, the tape moving direction signal SDR supplied from the terminal 40 is supplied to offset voltage forming circuits 41 and 42.

The level of the tape moving direction signal SDR supplied to the offset voltage forming circuit 41 is inverted by the inverter 43, and is supplied to the base of the transistor Q8 via the resistor R30. On the other hand, the power supply voltage Vs applied to the terminal 44 is
The voltage is supplied to the resistors R32 and R33 and the + terminal of the buffer 68 via the resistor R31. This resistor R32 is connected to the collector of the transistor Q8, and the emitter of the transistor Q8 and the other end of the resistor R33 are grounded.

The output terminal of the buffer 68 is connected to the + terminal of the amplifier 46 constituting the non-inverting addition circuit 45 via the resistor R34. When a high-level voltage is applied to the base of the transistor Q8, the level of the output signal supplied to the + terminal of the buffer 68 decreases because the voltage drop in the resistor R31 increases. That is, the phase of the output signal of the buffer 68 is inverted with respect to the phase of the output signal of the inverter 43. Therefore, the phase of the output signal of the offset voltage forming circuit 41 is positive.

The tape moving direction signal SDR supplied to the offset voltage forming circuit 42 is supplied to the base of the transistor Q9 via the resistor R35. A resistor R36 is connected between the base terminal of the transistor Q9 and the resistor R35, and the other end of the resistor R36 is grounded.

On the other hand, the terminal 47 to which the power supply voltage Vs (for example, 5 V) is applied.
Is connected to the resistor R38, the collector of the transistor Q9, and the + terminal of the buffer 48 via the resistor R37. resistance
The other end of R38 and the emitter of transistor Q9 are grounded. The output terminal of the buffer 48 is connected to the negative terminal of the amplifier 49 via the resistor R39. When a high-level voltage is applied to the base of the transistor Q9, the level of the output signal supplied to the + terminal of the buffer 48 decreases because the voltage drop in the resistor R37 increases. That is, the phase of the output signal of the offset voltage forming circuit 42 is inverted.

The tape speed signal STP is supplied to the terminal 50, and the tape speed signal STP is supplied to the minus terminal of the amplifier 51 via the resistor R40. The + terminal of the amplifier 51 is grounded, the output terminal is connected to the-terminal via a resistor R41, and negative feedback is applied. This amplifier 51
Thus, an output signal which is inverted with respect to the tape speed signal STP is obtained, and this output signal is supplied to the next-stage inversion adding circuit 52 via the resistor R42.

The inverting and adding circuit 52 includes an amplifier 49 and resistors R39, R42, and R43, and obtains an output signal inverted from the output signal from the amplifier 51 and the buffer 48. This output signal is connected to resistor R44
To the + terminal of the amplifier 46. Since the ratio of the above-described resistors R39 and R42 and the resistor R43 is, for example, 1: 3,
At the output terminal of the amplifier 49, an output signal whose level is three times the sum of the signals supplied from the amplifier 51 and the buffer 48 is obtained. Since the output signals from the amplifier 51 and the buffer 48 are both inverted in phase, they are re-inverted by the inverting and adding circuit 52 to have a positive phase.

The amplifier 46 constitutes a non-inverting addition circuit 45 together with the resistors R34, R44, R45, and R46, and adds and outputs the output signals from the buffer 48 and the inverting addition circuit 52 with a coefficient determined by the ratio of the resistors R34, R44 to R46. The signal is amplified and supplied to the amplifiers 54 and 55 via the terminal 53b of the changeover switch 53 and the resistors R54 and R55. still,
Since the ratios of the resistors R34 and R44 to R46 are all equal,
The sum of the levels of the output signals of the offset voltage forming circuit 41 and the inverting and adding circuit 52 becomes the output signal.

The comparison voltage forming circuit 56 includes a terminal 57 and resistors R47 and R48, and supplies the power supply voltage Vs supplied to the terminal 57 to the resistors R47 and R48.
To form the comparison voltage Vc5. The comparison voltage Vc5 is supplied to the + terminal of the amplifier 58. The amplifier 58 receives negative feedback from the output terminal to the negative terminal. The output signal from the amplifier 58 is supplied to the + terminal of the amplifier 54 via the resistor R56, and is supplied to the-terminal of the amplifier 59 via the resistor R49. Supplied.

The amplifier 59 has the + terminal grounded, and the output terminal is negatively fed back to the − terminal via the resistor R50. This amplifier 59 forms an inverting amplifier circuit 60 together with the resistors R50 and R49. Since the values of the resistors R50 and R49 are equal, the amplifier circuit 60 forms a signal having the opposite polarity to the amplifier 58 and the same absolute value level. The output signal of the amplifier 59 is supplied to the + terminal of the amplifier 55 via the resistor R51.

The amplifier 54 is negatively fed back from the output terminal to the negative terminal via a resistor R52.
Is connected, and the other end of the resistor R53 is grounded. The output signal of the amplifier 54 is
It is supplied to the terminal. Amplifier 54 includes resistors R52, R53, R5
4, a non-inverting addition circuit 62 is configured together with R56, and output signals from the non-inverting addition circuit 45 and the amplifier 58 are connected to resistors R52 and R52.
The signal is added and amplified by a coefficient determined by the ratio of 53, R54, and R56 and supplied to the + terminal of the comparator 61. In this case, since the values of the resistors R52, R53, R54, and R56 are all equal, the sum of the levels of the output signals of the non-inverting addition circuit 45 and the amplifier 58 is used as the output signal.

The amplifier 55 is negatively fed back from the output terminal to the negative terminal via a resistor R57.
Is connected, and the other end of the resistor R58 is grounded. The output signal of this amplifier 55 is
It is supplied to the terminal. Amplifier 55 includes resistors R51, R55, R5
7.A non-inverting addition circuit 64 is configured together with R58, and the output signals from the non-inverting addition circuit 45 and the inverting amplification circuit 60 are
The signal is added and amplified by a coefficient determined by the ratio of R51, R55, R57, and R58 and supplied to the + terminal of the comparator 63. In this case, since the values of the resistors R51, R55, R57, and R58 are all equal, the sum of the levels of the output signals of the non-inverting addition circuit 45 and the inverting amplification circuit 60 is used as the output signal.

A window W is formed by the two non-inverting addition circuits 62 and 64.

The error voltage Ver supplied from the terminal 65 is supplied to the terminal 53a of the changeover switch 53 and the negative terminals of the comparators 61 and 63.

In the comparators 61 and 63, the level of the output signal of the non-inverting addition circuits 62 and 64 is compared with the error voltage Ver, and the output signal is supplied to one terminal of the AND gate 67 via the inverter 66. The other terminal of the AND gate 67 has
From the terminal 69, for example, a speed control signal Ssp which becomes a high level when the speed is set to 15 times or more is supplied. And Gate 67
The switch 53 is controlled by this output signal.
A terminal 71 and a resistor R59 are connected to the output terminals of the comparators 61 and 63.

When the output signal of the AND gate 67 is at a high level, the changeover switch 53 connects the terminals 53b and 53c to connect the reference voltage
When Vref is taken out from the terminal 70 and the output signal of the AND gate 67 is at the low level, the terminals 53c and 53a are connected to connect the error voltage Ver
From the terminal 70.

(B-2) Circuit Operation of Pseudo-Lock Correction Circuit As shown in FIG. 6, in the range of high-speed reproduction where the tape speed is ± 15 times or more, the pseudo-lock correction circuit 5 sets the error voltage Ver and the reference voltage Vref. When the error voltage Ver comes out of the window W provided on both the upper and lower sides of the reference voltage Vref, this error voltage Ver is
Replace with a preset reference voltage Vref
Vref is supplied to VCO7.

 Hereinafter, description will be made from the fast-forward side in FIG.

A tape moving direction signal SDR is supplied from a terminal 40 to an offset voltage forming circuit 42. In this case, since the signal in the fast-forward mode is set to the high level, the transistor Q9 is turned on, and the current from the power supply voltage Vs is changed to the resistances R37 and R38 and the resistance
7. The current flows through both paths of the transistor Q9. As a result,
The offset level supplied to the + terminal of the amplifier 48 is set to 0V.

The tape speed signal STP is supplied to an inverting and adding circuit 52 via an amplifier 51. In the inverting and adding circuit 52, the above-mentioned offset level and the level of the tape speed signal STP are added, and in this embodiment, the amplified signal is amplified three times. Then, this output signal is supplied to the non-inverting addition circuit 45.

On the other hand, the tape moving direction signal SDR supplied from the terminal 40
Are supplied to the offset voltage forming circuit 41. in this case,
Since the signal in the fast-forward mode is set to the low level by the inverter 43, the transistor Q8 is turned off, and the power supply voltage Vs
Flows through the path of the resistors R31 and R33. As a result,
For example, an offset level of 1.5 V is supplied to the + terminal of the non-inverting addition circuit 45.

The above-mentioned state will be described with reference to FIG. 6 as an example. Only the inclination of the straight line of the tape speed signal STP is tripled. Next, this straight line is shifted upward on the vertical axis by an offset level, for example, +
Move 1.5V. As a result, the fast-forward reference voltage Vref
Is performed.

From the non-inverting addition circuit 45, the above-described reference voltage Vref is supplied to the terminal 53b of the changeover switch 53 and the non-inverting addition circuits 62 and 64, respectively.
Supplied.

By the way, the comparison voltage formed by the comparison voltage forming circuit 56
Vc5 is supplied to the amplifier 58. The output signal of the amplifier 58 defines an upper allowable range of the reference voltage Vref. This output signal is supplied to the + terminal of the amplifier 54 and the inverting amplifier circuit 60 via the resistor R56.

The inverting amplifier circuit 60 forms an output signal having an opposite polarity to the amplifier 58 and an equal absolute value level. This output signal defines the lower allowable range of the reference voltage Vref. The output signal of the amplifier 59 is supplied to the + terminal of the amplifier 55 via the resistor R51.

The non-inverting addition circuit 62 adds the reference voltage Vref supplied from the non-inverting addition circuit 45 and the output signal from the amplifier 58. Therefore, in the non-inverting addition circuit 62, the reference voltage
An upper allowable level is defined based on Vref, and the output signal is supplied to the comparator 61.

The non-inverting addition circuit 64 adds the reference voltage Vref supplied from the non-inverting addition circuit 45 and the output signal from the amplifier 59. Therefore, in the non-inverting addition circuit 64, the reference voltage
The level of the lower allowable range is defined based on Vref, and the output signal is supplied to the comparator 63.

As a result, a predetermined allowable range, that is, a window W is formed on both the upper and lower sides of the reference voltage Vref approximated to a straight line.

The comparator 61 compares the error voltage Ver with the level of the output signal from the amplifier 54, and when the error voltage Ver ≧ the reference voltage Vref is within the upper allowable range, the low level,
Otherwise, a high level output signal is supplied. The comparator 63 compares the above-mentioned error voltage Ver with the level of the output signal from the amplifier 55, and when the error voltage Ver ≧ the reference voltage Vref falls within a lower allowable range, the error level is low, and in other cases, Supplies a high level output signal.

As a result, when the level of one of the output signals of the comparators 61 and 63 becomes low level, it is inverted by the inverter 66 to be high level, and the changeover switch 53 is controlled. That is, the reference voltage Vref is taken out to the terminal 70 via the changeover switch 53. On the other hand, when the levels of the output signals of the comparators 61 and 63 coincide with the high level, the output is inverted by the inverter 66 to the low level and the error voltage Ver
Is taken out to the terminal 70.

 Hereinafter, the rewind side in FIG. 6 will be described.

A tape moving direction signal SDR is supplied from a terminal 40 to an offset voltage forming circuit 42. In this case, since the signal in the rewind mode is at the low level, the transistor Q9 is turned off, and the current from the power supply voltage Vs flows through the path of the resistors R37 and R38. As a result, the offset level supplied to the + terminal of the amplifier 48 is, for example, 2.5V.

The tape speed signal STP is supplied to an inverting and adding circuit 52 via an amplifier 51. In the inverting and adding circuit 52, the above-mentioned offset level and the level of the tape speed signal STP are added, and in this embodiment, the amplified signal is amplified three times. Then, this output signal is supplied to the non-inverting addition circuit 45.

On the other hand, the tape moving direction signal SDR supplied from the terminal 40
Is supplied to the offset voltage forming circuit 41. in this case,
Since the signal in the rewind mode is set to the high level by the inverter 43, the transistor Q8 is turned on, and the power supply voltage
The current from Vs flows through the paths of the resistors R31 and R33, the resistor R31, and the transistor Q8. As a result, for example, an offset level of 0.5 V is supplied to the + terminal of the non-inverting addition circuit 45.

The above state will be described with reference to FIG. 6 as an example. The straight line of the tape speed signal STP is shifted downward by an offset level, for example,
Move by 2.5V, and in this state, triple the inclination. This straight line is further added upward on the vertical axis by an offset level, for example, + 0.5V. As a result, linear approximation of the rewind-side reference voltage Vref is performed.

The reference voltage Vref is supplied from the non-inverting addition circuit 45 to the terminal 53b of the changeover switch 53 and the non-inverting addition circuits 62 and 64, respectively.

As described above, the output signal from the amplifier 58, which defines the upper allowable range of the reference voltage Vref, is supplied to the + terminal of the amplifier 54 via the resistor R56. The output signal of the inverting amplifier 60, which defines the lower allowable range of the reference voltage Vref, is connected to the resistor R5.
It is supplied to the + terminal of the amplifier 55 via 1.

The non-inverting addition circuit 62 adds the reference voltage Vref supplied from the non-inverting addition circuit 45 and the output signal from the amplifier 58, and determines the upper allowable level based on the reference voltage Vref. On the other hand, the non-inverting addition circuit 64 adds the reference voltage Vref supplied from the non-inverting addition circuit 45 and the output signal from the amplifier 59, and determines the level of the lower allowable range based on the reference voltage Vref. I have.

As a result, a predetermined allowable range, that is, a window W is formed on both the upper and lower sides of the reference voltage Vref approximated to a straight line.

Comparator 61 performs the same comparison as during fast-forward,
A low-level output signal is supplied when the error voltage Ver ≧ the reference voltage Vref is within an upper allowable range, and otherwise a high-level output signal is supplied. The comparator 63 also performs the same comparison as during fast-forward, and supplies a low-level output signal when the error voltage Ver ≦ the reference voltage Vref is within a lower allowable range, and otherwise supplies a high-level output signal.

As a result, when the level of the output signal of at least one of the comparators 61 and 63 becomes low level, the output signal is inverted by the inverter 66 to be high level, and the reference voltage Vref is output from the terminal 70 via the switch 53. Be taken out. On the other hand, when the levels of the output signals of the comparators 61 and 63 coincide with the high level, they are inverted by the inverter 66 to be at the low level, the changeover switch 53 is controlled, and the error voltage Vre is taken out from the terminal 70.

By adopting such a configuration, it is possible to quickly perform the pull-in operation even in the case of a rush from a no-signal during high-speed playback or when re-locking from an unlocked state, and the occurrence of image shrinkage, image expansion, etc. Can be prevented.

〔The invention's effect〕

According to the present invention, a reference signal having a level corresponding to the tape speed is compared with the error voltage, and when the lock is released, the error voltage corresponds to the tape speed and a reference signal having a level close to the VCO control error voltage. In the case of loss of lock during high-speed playback, entry from a no-signal state, etc., image shrinkage until locking again (at the time of REW)
This has the effect of preventing the occurrence of image elongation (at the time of FF) or the like and suppressing the disturbance of the screen. At the same time, there is an effect that the return speed can be increased.

Even if the horizontal synchronization signal for phase comparison is lost and locking is impossible, in the case of an AFC circuit that resets every H, if the reset reference (for example, SYNC of the Y signal) can be obtained, the locking is performed. This has the effect of obtaining an image as if it were a dolphin.

Further, since the frequency lock is performed based on the reference signal of the level corresponding to the tape speed, there is an effect that the frequency lock range can be further widened.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of the present invention, and FIG.
FIG. 3 is a timing chart for explaining the embodiment, and FIG.
FIG. 4 is a circuit diagram of the pseudo lock correction circuit, FIG. 4 is an explanatory diagram for explaining the circuit operation, FIG. 5 is a circuit diagram of the pseudo lock correction circuit of the second embodiment, and FIG. 6 describes the circuit operation. FIG. 7 is a block diagram for explaining a conventional example, and FIGS. 8 to 10 are timing charts for explaining the conventional example. Description of main symbols in the drawings 2, 110: phase comparator, 4, 7, 111: voltage controlled oscillator, 5:
Pseudo-lock correction circuit.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H04N 5/95

Claims (1)

(57) [Claims] A voltage-controlled oscillator for generating a signal having a frequency corresponding to an input voltage, and an output signal of the voltage-controlled oscillator or a regular phase separated from a reproduced video signal and a phase of a signal formed based on the output signal. And a phase comparator for comparing the phases of different signals, and in the AFC circuit configured to control the voltage-controlled oscillator by the output signal of the phase comparator, generate a reference signal having a level corresponding to the tape speed. A reference signal generation circuit, a circuit for comparing the level of the output signal of the phase comparator with the level of the reference signal, and selectively outputting the output signal of the phase comparator and the reference signal based on a result of the comparison. A switching means for inputting the voltage-controlled oscillator to the voltage-controlled oscillator.