JP4150396B2 - リジッドフレキシブル基板の製造方法 - Google Patents
リジッドフレキシブル基板の製造方法 Download PDFInfo
- Publication number
- JP4150396B2 JP4150396B2 JP2005311668A JP2005311668A JP4150396B2 JP 4150396 B2 JP4150396 B2 JP 4150396B2 JP 2005311668 A JP2005311668 A JP 2005311668A JP 2005311668 A JP2005311668 A JP 2005311668A JP 4150396 B2 JP4150396 B2 JP 4150396B2
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- Prior art keywords
- region
- rigid
- flexible
- copper plate
- circuit pattern
- Prior art date
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- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4688—Composite multilayer circuits, i.e. comprising insulating layers having different properties
- H05K3/4691—Rigid-flexible multilayer circuits comprising rigid and flexible layers, e.g. having in the bending regions only flexible layers
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/04—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed mechanically, e.g. by punching
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09009—Substrate related
- H05K2201/09127—PCB or component having an integral separable or breakable part
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
- H05K3/4652—Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49147—Assembling terminal to base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49156—Manufacturing circuit on or in base with selective destruction of conductive paths
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
- Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base
Description
上述したように、ポリイミドフィルム20を用いてフレキシブル領域に対するカバーレイ成形を行った後、フレキシブル領域の残部にレジストカバー30を形成する(図1C参照)。
その後、前記ポリイミド銅張積層板10の中でもリジッド領域が形成されるべき部分に機械的強度及び接着力を提供するために、プリプレグ40とベース銅板50をベース基板の上下に相互対向させて積層させる。
上述したように、プリプレグ40及びベース銅板50を積層させた後、プレスを用いて圧縮成形し、前記回路パターンが前記プリプレグに含浸された形で構成されたリジッド領域と、前記回路パターンが前記カバーレイに被覆された形で構成されたフレキシブル領域を形成する(図1D参照)。
次いで、基板の内・外層間の導通接続のための導通孔60を形成した後、ベース銅板50及び導通孔60に銅メッキ70を施すと同時に、所定の形状の外層回路パターンを形成する(図1E参照)。
上述したように所定の形状の外層回路パターンを形成した後、レジストカバー30を除去する。
この際、前記レジストカバーがピーラブルインクで形成された場合、ピーラブルインクの除去を容易にするために、ピーラブルインクを2次塗布して所定の厚さにした後、除去する(図1F参照)。
その後、PSRインク(Photo Imageable Solder Resist Mask Ink)を塗布させた後、表面処理を施すことにより、フレキシブル領域がポリイミドフィルム及びレジストカバーによってカバーレイ成形されたフライングテールタイプのリジッドフレキシブル基板を最終的に完成した(図1G参照)。
さらに、耐熱テープまたはピーラブルインクを使用することにより、残渣による汚染などに起因した不良が発生して信頼性を大幅低下させるという問題点があった。
その後、図2Hに示すように、前記導通孔160及びベース銅板150上に銅メッキ170を施す。
ここで、導通孔160に施された銅メッキ170は内・外層間を電気的に接続させ、ベース銅板150上に施された銅メッキ170はベース銅板150と共にメッキ層180を成して後述の外層回路パターンを形成する。
上述したように、銅メッキ170を施した後、図2Iに示すように、前記メッキ層180上にドライフィルムを用いてフォトエッチング処理した後、外層回路パターンを形成する。
111 ポリイミド層
112 銅箔層
120 エッチングレジストフィルム
130 カバーレイ
140 プリプレグ
150 ベース銅板
160 導通孔
170 銅メッキ
180 メッキ層
Claims (4)
- ポリイミドフィルムの少なくとも一面に内層回路パターンが形成されたベース基板を提供する工程と、
前記内層回路パターンのうち端子部を除いたフレキシブル領域に対応する内層回路パターンを保護するように、カバー層を成形する工程と、
リジッド領域に対応する前記ベース基板の上下面にプリプレグを配列し、前記プリプレグの上面にリジッド領域及びフレキシブル領域に対応するベース銅板を配列して一括積層することにより、リジッド領域とフレキシブル領域を形成する工程と、
前記フレキシブル領域に対応するベース銅板は保護しながら、前記リジッド領域には電気的に相互接続される外層回路パターンを形成する工程と、
前記フレキシブル領域に対応するベース銅板を除去する工程とを備え、
前記フレキシブル領域は端子部を含み、前記フレキシブル領域に対応するベース銅板を前記フレキシブル領域より0.05mm〜5mmさらに大きくすることを特徴とする、リジッドフレキシブル基板の製造方法。 - 前記端子部は、外部端子及び実装パッドのための領域であることを特徴とする、請求項1に記載のリジッドフレキシブル基板の製造方法。
- 前記ベース銅板を除去する工程は、
前記フレキシブル領域と前記リジッド領域との境界に対応するベース銅板にCNCドリルまたは抜き型を使って成形加工し、物理的な方法によって除去することを特徴とする、請求項1に記載のリジッドフレキシブル基板の製造方法。 - 前記外層回路パターンを形成する工程は、
前記リジッド領域に導通孔を形成する工程と、
前記導通孔を有するリジッド領域及び前記フレキシブル領域のベース銅板上に銅メッキを施してメッキ層を形成する工程と、
前記フレキシブル領域に対応するベース銅板は保護されるように、前記リジッド領域にのみ、前記ベース銅板及び前記メッキ層を一部除去して外層回路パターンを形成する工程とを含んでなることを特徴とする、請求項1に記載のリジッドフレキシブル基板の製造方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020040086731A KR100619347B1 (ko) | 2004-10-28 | 2004-10-28 | 리지드-플렉서블 기판의 제조 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006128686A JP2006128686A (ja) | 2006-05-18 |
JP4150396B2 true JP4150396B2 (ja) | 2008-09-17 |
Family
ID=36384592
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005311668A Expired - Fee Related JP4150396B2 (ja) | 2004-10-28 | 2005-10-26 | リジッドフレキシブル基板の製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US7281328B2 (ja) |
JP (1) | JP4150396B2 (ja) |
KR (1) | KR100619347B1 (ja) |
CN (1) | CN1780532A (ja) |
TW (1) | TWI298991B (ja) |
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KR100701641B1 (ko) * | 2004-08-02 | 2007-03-30 | 도레이새한 주식회사 | 진공증착에 의해 구리도금층을 형성하는 연성회로기판용 적층구조체의 제조방법 및 그 장치 |
KR100701645B1 (ko) * | 2004-08-02 | 2007-03-30 | 도레이새한 주식회사 | 연성회로기판용 적층구조체의 제조방법 |
KR100754080B1 (ko) * | 2006-07-13 | 2007-08-31 | 삼성전기주식회사 | 리지드-플렉서블 인쇄회로기판 및 그 제조방법 |
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JP2010021297A (ja) * | 2008-07-10 | 2010-01-28 | Compeq Manufacturing Co Ltd | 剥離可能な保護層を有するリジッドフレックス回路基板及びその製造方法 |
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CN102469699B (zh) * | 2010-11-12 | 2014-05-21 | 富葵精密组件(深圳)有限公司 | 软硬结合电路板的制作方法 |
CN102487577B (zh) * | 2010-12-01 | 2014-02-05 | 富葵精密组件(深圳)有限公司 | 软硬结合电路板的制作方法 |
KR101228888B1 (ko) * | 2011-05-31 | 2013-02-01 | 김선기 | 탄성단자 모듈과 그 제조장치 및 제조방법 |
CN102523683B (zh) * | 2011-11-16 | 2014-11-26 | 深圳崇达多层线路板有限公司 | 一种刚挠结合板及其制作方法 |
KR101905879B1 (ko) * | 2011-12-15 | 2018-11-28 | 엘지이노텍 주식회사 | 인쇄회로기판 및 그의 제조 방법 |
KR101387313B1 (ko) * | 2012-02-21 | 2014-04-18 | 삼성전기주식회사 | 플라잉테일 형태의 경연성 인쇄회로기판 제조 방법 및 이에 따라 제조된 플라잉테일 형태의 경연성 인쇄회로기판 |
KR101319808B1 (ko) | 2012-02-24 | 2013-10-17 | 삼성전기주식회사 | 경연성 인쇄회로기판 제조 방법 |
KR101462724B1 (ko) * | 2012-09-27 | 2014-11-17 | 삼성전기주식회사 | 리지드 플렉시블 인쇄회로기판 제조방법 |
CN103118505A (zh) * | 2013-01-25 | 2013-05-22 | 景旺电子(深圳)有限公司 | 一种软硬结合板的制作方法及软硬结合板 |
JP5900664B2 (ja) * | 2013-07-30 | 2016-04-06 | 株式会社村田製作所 | 多層基板および多層基板の製造方法 |
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TWI578868B (zh) * | 2016-01-13 | 2017-04-11 | 摩爾創新科技股份有限公司 | 曲面電路基板之製造方法 |
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CN105704940B (zh) * | 2016-04-21 | 2018-10-19 | 浪潮电子信息产业股份有限公司 | 一种控制管理pcba dip生产不良治具的方法 |
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KR101700161B1 (ko) | 2016-05-17 | 2017-01-26 | 이오에스(주) | 리지드-플렉서블 기판 제조방법 및 이에 사용되는 동박판-테이프 |
US10712398B1 (en) | 2016-06-21 | 2020-07-14 | Multek Technologies Limited | Measuring complex PCB-based interconnects in a production environment |
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-
2004
- 2004-10-28 KR KR1020040086731A patent/KR100619347B1/ko active IP Right Grant
-
2005
- 2005-10-17 TW TW094136181A patent/TWI298991B/zh not_active IP Right Cessation
- 2005-10-18 US US11/253,973 patent/US7281328B2/en not_active Expired - Fee Related
- 2005-10-26 JP JP2005311668A patent/JP4150396B2/ja not_active Expired - Fee Related
- 2005-10-27 CN CNA2005101147875A patent/CN1780532A/zh active Pending
Also Published As
Publication number | Publication date |
---|---|
TWI298991B (en) | 2008-07-11 |
CN1780532A (zh) | 2006-05-31 |
US20060101640A1 (en) | 2006-05-18 |
TW200631476A (en) | 2006-09-01 |
JP2006128686A (ja) | 2006-05-18 |
US7281328B2 (en) | 2007-10-16 |
KR100619347B1 (ko) | 2006-09-13 |
KR20060037698A (ko) | 2006-05-03 |
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