JP4149634B2 - 分周回路 - Google Patents
分周回路 Download PDFInfo
- Publication number
- JP4149634B2 JP4149634B2 JP2000112792A JP2000112792A JP4149634B2 JP 4149634 B2 JP4149634 B2 JP 4149634B2 JP 2000112792 A JP2000112792 A JP 2000112792A JP 2000112792 A JP2000112792 A JP 2000112792A JP 4149634 B2 JP4149634 B2 JP 4149634B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- signal
- flip
- dff
- timing chart
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000010355 oscillation Effects 0.000 claims description 11
- 230000001360 synchronised effect Effects 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 11
- 230000000630 rising effect Effects 0.000 description 7
- 239000013078 crystal Substances 0.000 description 6
- 238000005259 measurement Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 230000009471 action Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 239000013589 supplement Substances 0.000 description 1
Images
Landscapes
- Electric Clocks (AREA)
- Manipulation Of Pulses (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000112792A JP4149634B2 (ja) | 2000-04-14 | 2000-04-14 | 分周回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2000112792A JP4149634B2 (ja) | 2000-04-14 | 2000-04-14 | 分周回路 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2001298358A JP2001298358A (ja) | 2001-10-26 |
| JP2001298358A5 JP2001298358A5 (enExample) | 2007-04-05 |
| JP4149634B2 true JP4149634B2 (ja) | 2008-09-10 |
Family
ID=18624888
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2000112792A Expired - Fee Related JP4149634B2 (ja) | 2000-04-14 | 2000-04-14 | 分周回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP4149634B2 (enExample) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8355478B1 (en) * | 2009-05-29 | 2013-01-15 | Honeywell International Inc. | Circuit for aligning clock to parallel data |
| JP2024061521A (ja) | 2022-10-21 | 2024-05-07 | キオクシア株式会社 | 判定装置、試験システムおよび生成装置 |
-
2000
- 2000-04-14 JP JP2000112792A patent/JP4149634B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2001298358A (ja) | 2001-10-26 |
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