JP4149634B2 - Frequency divider circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a configuration of a frequency dividing circuit used in an electronic timepiece or the like, and more particularly to a frequency dividing circuit of low power and frequency dividing accuracy technology.
[0002]
[Prior art]
Frequency divider circuits are used in various electronic devices. Particularly in electronic watches, the frequency divider plays a central role.
[0003]
The current electronic timepiece divides the frequency until 1 second based on a clock pulse generated from a crystal oscillator circuit of about 32 KHz and displays the time in seconds.
Frequency division is performed by a frequency dividing circuit, and the frequency dividing circuit can perform fine adjustment to absorb frequency deviation due to manufacturing variations in addition to frequency division.
[0004]
The circuit diagram of FIG. 9 shows a conventional binary counter type frequency divider circuit, which is composed of a first data type flip-flop circuit (DFF circuit) 901 to a fifteenth DFF circuit 915.
[0005]
In FIG. 9, the DFF circuit 901 is a DFF circuit with a set for inputting the S1 signal 917, and is divided by 1/2 in synchronization with the falling edge of the CK signal 916 having a period of 32 KHz generated from the crystal oscillator. The Q1 signal 921 is output.
[0006]
The DFF circuit 902 is a DFF circuit with a set for inputting the S2 signal 918, and outputs a Q2 signal 922 divided by 1/2 in synchronization with the falling of the Q1 signal 921 generated from the DFF circuit 901. Circuit.
[0007]
The DFF circuit 903 is a data type flip-flop circuit, and outputs a Q3 signal 923 divided by 1/2 in synchronization with the fall of the Q2 signal 922 generated from the DFF circuit 902. The DFF circuit 904 This is a data type flip-flop circuit, and outputs a Q4 signal 924 divided by 1/2 in synchronization with the fall of the Q3 signal 923 generated from the DFF circuit 903.
[0008]
Thereafter, the frequency is similarly divided, and the DFF circuit 915 outputs a Q15 signal 935 of about 1 Hz.
[0009]
FIG. 10 is a waveform diagram showing a timing chart for explaining fine adjustment of the frequency division accuracy by setting the DFF circuit 901 and the DFF circuit 902.
[0010]
In FIG. 10, a CK timing chart 1001 shows the timing of the CK signal 916, and an S timing chart 1002 shows the timing of the S1 signal 917 and the S2 signal 918.
[0011]
The no-set timing chart 1003 shows the timing of the Q1 signal 921 and the Q2 signal 922 when there is no set, and the S1 set timing chart 1004 shows the Q1 signal 921 when the S1 signal 917 sets the DFF circuit 901 according to the S timing chart 1002 The timing of the Q2 signal 922 is shown.
[0012]
The S2 set timing chart 1005 shows the timing of the Q1 signal 921 and the Q2 signal 922 when the S2 signal sets the DFF circuit 902 according to the S timing chart 1002, and the S1-2 set timing chart 1006 sets the S1 signal 917 and S2 The timing of the Q1 signal 921 and the Q2 signal 922 when the signal 918 is generated in the DFF circuit 901 and the DFF circuit 902 according to the S timing chart 1002 is shown.
[0013]
In the case of the no-set timing chart 1003, the first fall of the Q1 signal 921 falls in synchronization with the second fall of the CK signal 916 on the basis of the set timing shown in the S timing chart 1002, and the Q2 signal 922 The first falling edge is synchronized with the fourth falling edge of the CK signal 916.
[0014]
Further, in the case of the S1 set timing chart 1004, the first fall of the Q1 signal 921 falls in synchronization with the first fall of the CK signal 916 on the basis of the set timing shown in the S timing chart 1002, and the Q2 signal The first falling edge of 922 falls in synchronization with the third falling edge of CK signal 916.
[0015]
In the case of the S2 set timing chart 1005, the first fall of the Q1 signal 921 falls in synchronization with the second fall of the CK signal 916 based on the set timing shown in the S timing chart 1002, and Q2 The first falling edge of the signal 922 falls in synchronization with the second falling edge of the CK signal 916.
[0016]
In the case of the S1-2 set timing chart 1006, the first fall of the Q1 signal 921 falls in synchronization with the first fall of the CK signal 916 on the basis of the set timing shown in the S timing chart 1002, and the Q2 signal The first falling edge of 922 falls in synchronization with the first falling edge of CK signal 916.
[0017]
That is, by inputting S1 and S2 and changing the timing of the Q2 signal 922, the period of the finally generated Q15 signal 935 can be finely adjusted.
[0018]
[Problems to be solved by the invention]
In the frequency divider circuit of the electronic timepiece as shown in FIG. 9 using only the binary counter type frequency divider circuit, there are many gates driven at a high frequency, and thus there is a limit to the reduction in power consumption.
[0019]
(Object of invention)
In order to solve the above problems, an object of the present invention is to devise the form of a frequency dividing circuit, and to propose a frequency dividing circuit including a frequency dividing circuit that can finely adjust the frequency division with low power.
[0020]
[Means for Solving the Problems]
In order to achieve the above object, the present invention is a frequency dividing circuit for inputting a clock signal having a predetermined frequency generated from an oscillation circuit , dividing the clock signal, and outputting a signal having a predetermined frequency dividing ratio.
A synchronous front-end circuit that includes a plurality of flip-flop circuits having either a set function or a reset function and that divides the frequency based on the clock signal ;
Have a, and the rear portion circuit asynchronous for dividing based on the divided signal outputted as a result of the front stage circuit with the flip-flop circuit comprising a plurality of stages,
In a frequency divider circuit that enables fine adjustment of the predetermined frequency division ratio by enabling the set function or the reset function by inputting a predetermined adjustment signal,
The pre-stage circuit is connected so as to transfer the capacitance of the clock input gate to the capacitance Cout constituting the oscillation circuit by directly inputting the clock signal as a clock input,
The pre-stage circuit divides the clock signal up to at least 1/4 frequency division based on the clock signal,
The first part circuit, when provided with the set function and a flip-flop circuit at least Kumisonae, to the first stage of the flip-flop circuit having a flip-flop circuit and reset function having a set function, other of the flip-flop circuit with the reset function, when provided with the reset function to the first stage of the flip-flop circuit, another one of the flip-flop circuit comprises a set of functions,
The adjustment signal is two signals of a set signal for enabling the set function and a reset signal for enabling the reset function,
The pre-stage circuit changes the start timing of the output signal of the first flip-flop circuit in synchronization with the fall or rise of the clock signal by the combination of the two signals that are the adjustment signals .
[0021]
[Action]
Usually, the preceding stage of the frequency dividing circuit in the timepiece circuit is an oscillation circuit as shown in FIG. Therefore, the clock input of the frequency divider circuit is the power consumption of the inverter circuit in the oscillation circuit 130.
[0022]
By the way, Cout 131 is originally required for transmission, and even if a part of the capacity of the clock input gate of the frequency divider circuit is transferred to Cout, the power consumption of the oscillation circuit 130 does not change.
[0023]
Therefore, the power can be reduced by using a synchronous counter type frequency dividing circuit such as a Johnson counter that can lower the gate driving frequency other than the clock gate driven by the CK signal 116 from the oscillation circuit 130 of the frequency dividing circuit.
[0024]
The above effect is more effective at high frequencies. However, the Johnson counter type circuit requires a larger circuit area than the binary counter type frequency dividing circuit in the same frequency dividing function, and further, there is a limit to supplement a part of Cout 131. And the ratio of the number of stages of the Johnson counter type frequency dividing circuit needs to be balanced appropriately.
[0025]
Further, the fine adjustment function, which is another role of the frequency dividing circuit, can be easily realized by using a DFF circuit with a set and a reset in the Johnson counter unit.
[0026]
DETAILED DESCRIPTION OF THE INVENTION
(Reference Example: FIGS. 1 and 2)
Hereinafter, the configuration of the frequency dividing circuit which is a premise of the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing the configuration of the frequency dividing circuit. The frequency dividing circuit is formed of two parts, a Johnson counter unit 110 and a binary counter unit 111.
[0027]
The Johnson counter portion 110 is a Johnson counter circuit composed of two well-known DFF circuits, a DFF circuit 101 and a DFF circuit 102, and a CK signal that is a clock signal of about 32 KHz generated from the crystal oscillation circuit 130. This is a circuit that outputs the Q1 signal 121 and the Q2 signal 122 that have been divided by ¼ in synchronization with the fall of 916.
[0028]
The binary counter portion 111 is a binary counter circuit composed of four DFF circuits, which are generally well-known DFF circuit 103, DFF circuit 104, DFF circuit 105, and DFF circuit 106.
[0029]
The DFF circuit 103 is a circuit that outputs a Q3 signal 123 divided by 1/2 in synchronization with the fall of the Q1 signal 121 generated from the DFF circuit 101, and the DFF circuit 104 is a Q3 signal generated from the DFF circuit 103. This is a circuit that outputs the Q4 signal 124 divided by 1/2 in synchronization with the falling edge of the signal 123.
[0030]
The DFF circuit 105 and the DFF circuit 106 are also frequency divider circuits that output the Q6 signal 126 in the same manner and finally divide the frequency by 1/64.
[0031]
FIG. 2 shows a current measurement result of the above-described frequency dividing circuit according to the present invention for performing 1/64 frequency division manufactured by a predetermined C-MOS process and a binary counter type frequency dividing circuit (not shown) in the prior art. Indicates.
In FIG. 2, the points indicated by squares indicate the current measurement results of the binary counter type frequency divider circuit in the prior art, and the points indicated by circles indicate the current measurement results of the frequency divider circuit according to the present invention.
[0032]
FIG. 2A shows the frequency dependence at a constant voltage (0.7 V). The characteristics of any of the frequency dividing circuits are substantially proportional to the frequency, but the frequency dividing circuit 201 according to the present invention has a lower current than the binary counter type frequency dividing circuit 202 in the prior art.
[0033]
FIG. 2B shows the voltage dependence at a constant frequency (32 KHz). Although the characteristics of any of the frequency divider circuits are substantially proportional to the voltage, the frequency divider circuit 203 according to the present invention has a lower current than the binary counter frequency divider circuit 204 in the prior art.
[0034]
In the conventional binary counter type frequency divider circuit, the Q1 signal divided by 1/2 is input to the second stage DFF circuit, whereas in the Johnson counter unit 110, the Q1 signal 121 and the Q2 signal 122 are This is because the signal is divided by 1/4 and driven at a relatively low frequency.
[0035]
The driving power by the CK 116 to the Johnson counter unit 110 is consumed as the inverter current of the preceding oscillation circuit 131, but is not increased because it is incorporated in the capacitor Cout 131.
[0036]
In this way, a low-power frequency divider circuit can be manufactured. Of course, it is possible to further reduce the power by increasing the number of stages of the Johnson counter system 110. However, the gate capacity that is larger than the optimum value of the capacity Cout131 is in terms of total power and stability. It is not preferable.
[0037]
Further, the binary counter type frequency dividing circuit has a frequency dividing function of 1 / n 2 for n DFF circuits, whereas the Johnson counter type frequency dividing circuit has a frequency dividing function of 1 / 2n. However, the area is required accordingly.
For this reason, it is desirable to make the circuit well balanced with the binary counter type frequency dividing circuit. In particular, when the Johnson type counter unit 110 is composed of two stages of DFF circuits, the number of DFF circuits is the same as the number of binary counter type frequency divider circuits.
[0038]
In this example, the Johnson counter type circuit has been described, but the same effect can be obtained with a synchronous circuit.
[0039]
(First Embodiment: FIGS. 3 and 4)
Next, the configuration of the frequency divider in the first embodiment will be described with reference to FIG. A circuit in which a fine adjustment function is added to the low power divider circuit shown in the reference example will be described.
[0040]
FIG. 3 shows a low-power frequency divider circuit with a fine adjustment function according to the present invention, which includes a first DFF circuit 301 to a fifteenth DFF circuit 315.
[0041]
In FIG. 3, a DFF circuit 301 is a DFF circuit with a set for inputting an S signal 317, and is divided by ¼ in synchronization with a falling edge of a CK signal 916 that is a clock signal generated from a crystal oscillator. This is a circuit for outputting the Q1 signal 321.
[0042]
The DFF circuit 302 is a DFF circuit with a reset for inputting the R signal 318, and is a circuit that outputs a Q2 signal 322 that is divided by ¼ in synchronization with the falling edge of the CK signal 916.
[0043]
The DFF circuit 303 is a circuit that outputs a Q3 signal 323 divided by 1/2 in synchronization with the fall of the Q1 signal 321 generated from the DFF circuit 301, and the DFF circuit 304 is a Q3 signal generated from the DFF circuit 303. This is a circuit that outputs a Q4 signal 324 divided by 1/2 in synchronization with the falling edge of the signal 323.
[0044]
Thereafter, the DFF circuit 315 outputs a Q15 signal 335 of about 1 Hz in the same manner.
[0045]
FIG. 4 is a timing chart for explaining fine adjustment of the frequency division accuracy by setting the DFF circuit 301 and resetting the DFF circuit 302.
[0046]
In the figure, a CK timing chart 401 shows the timing of the CK signal 916, and an SR timing chart 402 shows the timing of the set of the DFF circuit 301 and the reset signal of the DFF circuit 302.
[0047]
The SR-less timing chart 403 shows the timing of the Q1 signal 321 and the Q2 signal 322 when there is no set. The set timing chart 404 shows the Q1 signal 321 when the S signal 317 sets the DFF circuit 301 according to the SR timing chart 402. And the timing of the Q2 signal 322.
[0048]
The reset timing chart 405 shows the timing of the Q1 signal 321 and the Q2 signal 322 when the R signal 318 resets the DFF circuit 302 according to the SR timing chart 402, and the SR set timing chart 406 shows the S timing according to the SR timing chart 402. The timing of the Q1 signal 321 and the Q2 signal 322 when the signal 317 sets the DFF circuit 301 and the R signal 318 is generated in the DFF circuit 302 is shown.
[0049]
In the case of the timing chart 403 without SR, the first falling edge of the Q1 signal 321 falls in synchronization with the fourth falling edge of the CK signal 916 with reference to the set timing shown in the SR timing chart 402.
[0050]
In the case of the set timing chart 404, the first fall of the Q1 signal 321 falls in synchronization with the first fall of the CK signal 916 with reference to the set timing shown in the SR timing chart 402.
[0051]
In the case of the reset timing chart 405, the first falling edge of the Q1 signal 321 falls in synchronization with the third falling edge of the CK signal 916 based on the reset timing shown in the SR timing chart 402.
[0052]
In the case of the set reset timing chart 406, the first fall of the Q1 signal 321 falls in synchronization with the second fall of the CK signal 916 based on the set reset timing shown in the SR timing chart 402.
[0053]
That is, the period of the Q15 signal 335 finally generated can be finely adjusted by inputting the S signal 317 and the R signal 318 and changing the timing of the Q1 signal 321.
[0054]
In addition, when replacing the circuit so far, it is possible to easily replace it by changing the input by decoding the set and reset inputs.
[0055]
(Second Embodiment: FIGS. 5 and 6)
Next, the configuration of the frequency divider in the second embodiment will be described with reference to FIG. A circuit in the case where the low power divider circuit with a fine adjustment function shown in the first embodiment is in synchronization with rising is described.
[0056]
FIG. 5 shows a low-power frequency divider circuit with a fine adjustment function according to the present invention, which includes a first DFF circuit 501 to a fifteenth DFF circuit 515.
[0057]
In FIG. 5, a DFF circuit 501 is a DFF circuit with a reset for inputting an R signal 517, and is divided by ¼ in synchronization with the rising edge of a CK signal 916 that is a clock pulse generated from a crystal oscillator. This is a circuit for outputting the Q1 signal 521.
[0058]
The DFF circuit 502 is a DFF circuit with a set for inputting the S signal 518, and is a circuit that outputs a Q2 signal 522 that is divided by ¼ in synchronization with the rising edge of the CK signal 916.
[0059]
The DFF circuit 503 is a circuit that outputs a Q3 signal 523 divided by 1/2 in synchronization with the rise of the Q1 signal 521 generated from the DFF circuit 501, and the DFF circuit 504 is a Q3 signal generated from the DFF circuit 503. This is a circuit that outputs a Q4 signal 524 divided by 1/2 in synchronization with the rise of 523.
[0060]
Thereafter, the DFF circuit 515 outputs a Q15 signal 535 of about 1 Hz in the same manner.
[0061]
FIG. 6 is a timing chart for explaining fine adjustment of the frequency division accuracy by resetting the DFF circuit 501 and setting the DFF circuit 502.
[0062]
In FIG. 6, a CK timing chart 601 shows the timing of the CK signal 916, and an RS timing chart 602 shows the reset of the DFF circuit 501 and the timing of the set signal of the DFF circuit 502.
[0063]
The RS-less timing chart 603 shows the timing of the Q1 signal 521 and the Q2 signal 522 when there is no set, and the reset timing chart 604 shows the Q1 signal 521 when the R signal 517 resets the DFF circuit 901 according to the SR timing chart 602. And the timing of the Q2 signal 522.
[0064]
The set timing chart 605 shows the timing of the Q1 signal 521 and the Q2 signal 522 when the S signal 518 sets the DFF circuit 502 according to the SR timing chart 602. The RS set timing chart 606 shows the R signal 517 and the SR timing chart. The timing of the Q1 signal 521 and the Q2 signal 522 when the DFF circuit 501 is reset according to 602 and the S signal 518 sets the DFF circuit 502 according to the SR timing chart 602 is shown.
[0065]
In the case of the timing chart 603 without RS, the first rising edge of the Q1 signal 521 rises in synchronization with the fourth rising edge of the CK signal 916 with reference to the set timing shown in the RS timing chart 602.
[0066]
In the case of the set timing chart 604, the first rise of the Q1 signal 521 rises in synchronization with the first rise of the CK signal 916 based on the set timing shown in the RS timing chart 602.
[0067]
In the case of the reset timing chart 605, the first rise of the Q1 signal 521 rises in synchronization with the third rise of the CK signal 916 based on the reset timing shown in the RS timing chart 602.
[0068]
In the case of the reset set timing chart 606, the first rise of the Q1 signal 521 rises in synchronization with the second rise of the CK signal 916 with reference to the reset set timing shown in the RS timing chart 602.
[0069]
That is, the period of the Q15 signal 535 that is finally generated can be finely adjusted by inputting the R signal 517 and the S signal 518 and changing the timing of the Q1 signal 521.
[0070]
In addition, when replacing the circuit so far, it is possible to easily replace it by changing the input by decoding the set and reset inputs.
[0071]
( Third embodiment: FIGS. 7 and 8)
Then the frequency divider of the structure in the third embodiment will be described with reference to FIG. DFF circuit number of Johnson counter part of the fine adjustment function Low power divider circuit shown in the first exemplary type state is illustrating a circuit in the case of 4 stages.
[0072]
FIG. 7 shows a low-power frequency divider circuit with a fine adjustment function according to the present invention, which is composed of a first DFF circuit 701 to a 17th DFF circuit 717.
[0073]
In FIG. 7, a DFF circuit 701 is a DFF circuit with a set for inputting an S signal 730, and is divided by 1/8 in synchronization with the falling edge of the CK signal 916, which is a clock pulse generated from a crystal oscillator. The Q1 signal 721 is output.
[0074]
The DFF circuit 702 is a DFF circuit with a reset for inputting the R1 signal 731, and is a circuit that outputs a Q1 signal 721 that has been divided by 1/8 in synchronization with the falling edge of the CK signal 916.
[0075]
Similarly, the DFF circuit 703 is a DFF circuit with reset for inputting the R2 signal 732, and is a circuit that outputs a Q3 signal 723 divided by 1/8 in synchronization with the falling edge of the CK signal 916. The DFF circuit 704 is a DFF circuit with a reset for inputting the R3 signal 733, and outputs a Q4 signal 724 that has been divided by 1/8 in synchronization with the falling edge of the CK signal 916.
[0076]
The DFF circuit 705 is a circuit that outputs a Q5 signal 725 divided by 1/2 in synchronization with the falling edge of the Q1 signal 721 generated from the DFF circuit 701, and the DFF circuit 706 is the Q5 signal generated from the DFF circuit 705. This is a circuit that outputs a Q6 signal 726 divided by 1/2 in synchronization with the falling edge of the signal 725.
[0077]
Thereafter, the DFF circuit 717 outputs a Q17 signal 737 of about 1 Hz in the same manner.
[0078]
FIG. 8 is a timing chart for explaining fine adjustment of frequency division accuracy by setting the DFF circuit 701 and resetting the DFF circuit 702 and resetting the DFF circuit 703 and the DFF circuit 704.
[0079]
In FIG. 8, a CK timing chart 801 shows the timing of the CK signal 916, and an SR timing chart 802 shows a set of the DFF circuit 701 and reset signal timing of the DFF circuit 702, the DFF circuit 703, and the DFF circuit 704.
[0080]
The SR-free timing chart 803 shows the timing of the Q1 signal 721, the Q2 signal 722, the Q3 signal 723, and the Q4 signal 724 when there is no set.
The R1R2 timing chart 804 is the timing of the Q1 signal 721, Q2 signal 722, Q3 signal 723 and Q4 signal 724 when the R1 signal 731 resets the DFF circuit 702 and the R2 signal 732 resets the DFF circuit 703 according to the SR timing chart 802. Indicates.
[0081]
In the case of the timing chart 803 without SR, the first falling edge of the Q1 signal 821 falls in synchronization with the eighth falling edge of the CK signal 916 with reference to the timing of the set shown in the SR timing chart 802.
[0082]
In the case of the R1R2 reset timing chart 804, the first falling edge of the Q1 signal 721 falls in synchronization with the sixth falling edge of the CK signal 916 with reference to the set timing shown in the SR timing chart 802.
[0083]
Hereinafter, by combining one set and three resets, the first falling edge of the Q1 signal 721 is synchronized with the first to eighth falling edges of the CK signal 916 with reference to the timing of the set shown in the SR timing chart 802. It is possible to fall.
[0084]
That is, the period of the Q15 signal 735 finally generated can be finely adjusted by inputting the S signal 730, the R1 signal 731, the R2 signal 732, and the R3 signal 733 and changing the timing of the Q1 signal 721.
[0085]
Of course, fine adjustment is possible even if the number of DFF circuits with reset in the Johnson counter portion is increased.
In addition, when replacing the circuit so far, it is possible to easily replace it by changing the input by decoding the set and reset inputs.
[0086]
【The invention's effect】
As is clear from the above description, it is possible to divide an electronic device using a frequency dividing circuit such as an electronic timepiece with low power while maintaining accuracy by the frequency dividing circuit of the present invention.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a configuration including an oscillation circuit of a frequency divider as a reference example .
FIG. 2 is a graph showing a current measurement result of a frequency divider circuit in the example of FIG.
FIG. 3 is a circuit diagram showing a configuration of a frequency dividing circuit with a fine adjustment function in the embodiment of the present invention.
FIG. 4 is a diagram showing a timing chart by the frequency divider circuit in the embodiment of the present invention.
FIG. 5 is a circuit diagram showing a rising synchronization time by a frequency divider in an embodiment of the present invention.
FIG. 6 is a diagram showing a timing chart by the frequency divider circuit in the embodiment of the present invention.
FIG. 7 is a circuit diagram showing a rising synchronization time by a frequency divider in the embodiment of the present invention.
FIG. 8 is a drawing showing a timing chart based on 1/8 frequency division by a frequency divider circuit in an embodiment of the present invention.
FIG. 9 is a circuit diagram showing a frequency dividing circuit in the prior art.
FIG. 10 is a diagram showing a timing chart by a frequency dividing circuit in the prior art.
[Explanation of symbols]
110: Johnson counter unit 111: Binary counter unit 116: CK signal 131: Capacitance Cout
201: Current-frequency characteristics of a circuit according to the present invention 203: Current-voltage characteristics of a circuit according to the present invention 321: Q1 signal 404: Set timing chart 604: Reset timing chart 804: R2R3 timing chart

Claims (1)

A frequency dividing circuit for inputting a clock signal having a predetermined frequency generated from an oscillation circuit, dividing the clock signal and outputting a signal having a predetermined frequency dividing ratio,
A synchronous front-end circuit that includes a plurality of flip-flop circuits having either a set function or a reset function and that divides the frequency based on the clock signal ;
Have a, and the rear portion circuit asynchronous for dividing based on the divided signal outputted as a result of the front stage circuit with the flip-flop circuit comprising a plurality of stages,
In a frequency divider circuit that enables fine adjustment of the predetermined frequency division ratio by enabling the set function or the reset function by inputting a predetermined adjustment signal,
The pre-stage circuit is connected so as to transfer the capacitance of the clock input gate to the capacitance Cout constituting the oscillation circuit by directly inputting the clock signal as a clock input,
The pre-stage circuit divides the clock signal up to at least 1/4 frequency division based on the clock signal,
The first part circuit, when provided with the set function and a flip-flop circuit at least Kumisonae, to the first stage of the flip-flop circuit having a flip-flop circuit and reset function having a set function, other of the flip-flop circuit with the reset function, when provided with the reset function to the first stage of the flip-flop circuit, another one of the flip-flop circuit comprises a set of functions,
The adjustment signal is two signals of a set signal for enabling the set function and a reset signal for enabling the reset function,
The pre-stage circuit changes the start timing of the output signal of the flip-flop circuit in the first stage in synchronization with the fall or rise of the clock signal by a combination of the two signals as the adjustment signal. Dividing circuit to do.

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