JP4137782B2 - リードフレーム、このリードフレームを用いた面実装型半導体装置およびこの面実装型半導体装置を回路基板上に搭載した電子機器 - Google Patents
リードフレーム、このリードフレームを用いた面実装型半導体装置およびこの面実装型半導体装置を回路基板上に搭載した電子機器 Download PDFInfo
- Publication number
- JP4137782B2 JP4137782B2 JP2003422979A JP2003422979A JP4137782B2 JP 4137782 B2 JP4137782 B2 JP 4137782B2 JP 2003422979 A JP2003422979 A JP 2003422979A JP 2003422979 A JP2003422979 A JP 2003422979A JP 4137782 B2 JP4137782 B2 JP 4137782B2
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- JP
- Japan
- Prior art keywords
- tie bar
- lead
- semiconductor device
- lead frame
- lead terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
図1は、本発明のリードフレームの一実施例およびこのリードフレームを用いた面実装型半導体装置の製造工程の一例を示す平面図であり、同図(a)はタイバーカット前の状態、同図(b)はタイバーカット後の状態を示している。また、同図(c)はタイバー部分の拡大図である。
次に、本発明の参考例1について、図3を参照して説明する。
次に、本発明の参考例2について、図4を参照して説明する。
次に、本発明の参考例3について、図5を参照して説明する。
2 載置片
3 リード端子
4 リードフレーム
5 封止樹脂部
6 横枠
8 ボンディングワイヤ
9 タイバー
10 半導体装置
11 回路基板
12 部品ランド
19,29 タイバー根元
9a1,9b1 タイバーの一方の端部(左側端部)
9a2,9b2 タイバーの他方の端部(右側端部)
Claims (3)
- 封止樹脂部より突出した複数のリード端子を備えた面実装型半導体装置用のリードフレームであって、
各リード端子間に架けられた複数のタイバーが、互いに平行に、かつ、リード端子の幅方向に対して傾斜して設けられており、前記タイバーの一端部のリード端子接続位置と他端部のリード端子接続位置とがリード端子の幅方向から見たときに重ならないように、タイバーの傾斜角度が設定されていることを特徴とするリードフレーム。 - 前記請求項1記載のリードフレームを用いて製造されたことを特徴とする面実装型半導体装置。
- 前記請求項2記載の面実装型半導体装置を回路基板上に搭載したことを特徴とする電子機器。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003422979A JP4137782B2 (ja) | 2003-12-19 | 2003-12-19 | リードフレーム、このリードフレームを用いた面実装型半導体装置およびこの面実装型半導体装置を回路基板上に搭載した電子機器 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003422979A JP4137782B2 (ja) | 2003-12-19 | 2003-12-19 | リードフレーム、このリードフレームを用いた面実装型半導体装置およびこの面実装型半導体装置を回路基板上に搭載した電子機器 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005183695A JP2005183695A (ja) | 2005-07-07 |
JP4137782B2 true JP4137782B2 (ja) | 2008-08-20 |
Family
ID=34783667
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2003422979A Expired - Fee Related JP4137782B2 (ja) | 2003-12-19 | 2003-12-19 | リードフレーム、このリードフレームを用いた面実装型半導体装置およびこの面実装型半導体装置を回路基板上に搭載した電子機器 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP4137782B2 (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN105845816A (zh) | 2010-11-02 | 2016-08-10 | 大日本印刷株式会社 | 附有树脂引线框及半导体装置 |
JP7304830B2 (ja) * | 2020-02-12 | 2023-07-07 | 三菱電機株式会社 | トランスファーモールド型パワーモジュール、リードフレーム、およびトランスファーモールド型パワーモジュールの製造方法 |
-
2003
- 2003-12-19 JP JP2003422979A patent/JP4137782B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2005183695A (ja) | 2005-07-07 |
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