JP4125485B2 - 新規なパッシベーション構造とその製造方法 - Google Patents

新規なパッシベーション構造とその製造方法 Download PDF

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Publication number
JP4125485B2
JP4125485B2 JP2000526974A JP2000526974A JP4125485B2 JP 4125485 B2 JP4125485 B2 JP 4125485B2 JP 2000526974 A JP2000526974 A JP 2000526974A JP 2000526974 A JP2000526974 A JP 2000526974A JP 4125485 B2 JP4125485 B2 JP 4125485B2
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Japan
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dielectric
capped
dielectric constant
layer
hard mask
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JP2000526974A
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Japanese (ja)
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JP2002500445A5 (https=
JP2002500445A (ja
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ボーア，マーク・ティ
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Intel Corp
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Intel Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6548—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by forming intermediate materials, e.g. capping layers or diffusion barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/668—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials
    • H10P14/6681—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si
    • H10P14/6682—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound being a silane, e.g. disilane, methylsilane or chlorosilane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/69215—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/694—Inorganic materials composed of nitrides
    • H10P14/6943—Inorganic materials composed of nitrides containing silicon
    • H10P14/69433—Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/137—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being directly on the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/536—Shapes of wire connectors the connected ends being ball-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/59—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/934—Cross-sectional shape, i.e. in side view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/981—Auxiliary members, e.g. spacers
    • H10W72/983—Reinforcing structures, e.g. collars

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)
  • Formation Of Insulating Films (AREA)
JP2000526974A 1997-12-31 1998-12-15 新規なパッシベーション構造とその製造方法 Expired - Lifetime JP4125485B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/001,551 1997-12-31
US09/001,551 US6143638A (en) 1997-12-31 1997-12-31 Passivation structure and its method of fabrication
PCT/US1998/026689 WO1999034442A1 (en) 1997-12-31 1998-12-15 A novel passivation structure and its method of fabrication

Publications (3)

Publication Number Publication Date
JP2002500445A JP2002500445A (ja) 2002-01-08
JP2002500445A5 JP2002500445A5 (https=) 2006-02-02
JP4125485B2 true JP4125485B2 (ja) 2008-07-30

Family

ID=21696634

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000526974A Expired - Lifetime JP4125485B2 (ja) 1997-12-31 1998-12-15 新規なパッシベーション構造とその製造方法

Country Status (5)

Country Link
US (2) US6143638A (https=)
JP (1) JP4125485B2 (https=)
KR (1) KR100360387B1 (https=)
AU (1) AU1917299A (https=)
WO (1) WO1999034442A1 (https=)

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* Cited by examiner, † Cited by third party
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US6049135A (en) 1996-05-28 2000-04-11 Kabushiki Kaisha Toshiba Bed structure underlying electrode pad of semiconductor device and method for manufacturing same
US6875681B1 (en) * 1997-12-31 2005-04-05 Intel Corporation Wafer passivation structure and method of fabrication
US6965165B2 (en) 1998-12-21 2005-11-15 Mou-Shiung Lin Top layers of metal for high performance IC's
US6372621B1 (en) * 1999-04-19 2002-04-16 United Microelectronics Corp. Method of forming a bonding pad on a semiconductor chip
US6423628B1 (en) * 1999-10-22 2002-07-23 Lsi Logic Corporation Method of forming integrated circuit structure having low dielectric constant material and having silicon oxynitride caps over closely spaced apart metal lines
US6350695B1 (en) * 2000-06-16 2002-02-26 Chartered Semiconductor Manufacturing Ltd. Pillar process for copper interconnect scheme
DE10118422B4 (de) * 2001-04-12 2007-07-12 Infineon Technologies Ag Verfahren zur Herstellung einer strukturierten metallhaltigen Schicht auf einem Halbleiterwafer
US6660661B1 (en) * 2002-06-26 2003-12-09 Cypress Semiconductor Corporation Integrated circuit with improved RC delay
US7018942B1 (en) 2002-06-26 2006-03-28 Cypress Semiconductor Corporation Integrated circuit with improved RC delay
US7142416B2 (en) * 2002-12-20 2006-11-28 Hewlett-Packard Development Company, L.P. Method and apparatus for determining the physical configuration of a multi-component system
US7186637B2 (en) * 2003-07-31 2007-03-06 Intel Corporation Method of bonding semiconductor devices
US7262123B2 (en) * 2004-07-29 2007-08-28 Micron Technology, Inc. Methods of forming wire bonds for semiconductor constructions
US7316971B2 (en) * 2004-09-14 2008-01-08 International Business Machines Corporation Wire bond pads
US7348210B2 (en) * 2005-04-27 2008-03-25 International Business Machines Corporation Post bump passivation for soft error protection
JP2008294123A (ja) * 2007-05-23 2008-12-04 Nec Electronics Corp 半導体装置及び半導体装置の製造方法
US7612457B2 (en) 2007-06-21 2009-11-03 Infineon Technologies Ag Semiconductor device including a stress buffer
TWI409919B (zh) * 2010-06-04 2013-09-21 財團法人工業技術研究院 真空氣密之有機構裝載體與感測器元件構裝
US9343651B2 (en) * 2010-06-04 2016-05-17 Industrial Technology Research Institute Organic packaging carrier
CN102280434B (zh) * 2010-06-12 2014-07-30 财团法人工业技术研究院 真空气密的有机封装载体与传感器组件封装结构
US8685778B2 (en) 2010-06-25 2014-04-01 International Business Machines Corporation Planar cavity MEMS and related structures, methods of manufacture and design structures
KR102462134B1 (ko) * 2015-05-19 2022-11-02 삼성전자주식회사 배선 구조물, 배선 구조물 형성 방법, 반도체 장치 및 반도체 장치의 제조 방법
US9691723B2 (en) * 2015-10-30 2017-06-27 Taiwan Semiconductor Manufacturing Company, Ltd. Connector formation methods and packaged semiconductor devices
US10325870B2 (en) * 2017-05-09 2019-06-18 International Business Machines Corporation Through-substrate-vias with self-aligned solder bumps

Family Cites Families (10)

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Publication number Priority date Publication date Assignee Title
JPH0691126B2 (ja) * 1987-06-11 1994-11-14 日本電気株式会社 半導体装置
US5565378A (en) * 1992-02-17 1996-10-15 Mitsubishi Denki Kabushiki Kaisha Process of passivating a semiconductor device bonding pad by immersion in O2 or O3 solution
US5463225A (en) * 1992-06-01 1995-10-31 General Electric Company Solid state radiation imager with high integrity barrier layer and method of fabricating
JP2611615B2 (ja) * 1992-12-15 1997-05-21 日本電気株式会社 半導体装置の製造方法
US5661082A (en) * 1995-01-20 1997-08-26 Motorola, Inc. Process for forming a semiconductor device having a bond pad
US5534462A (en) * 1995-02-24 1996-07-09 Motorola, Inc. Method for forming a plug and semiconductor device having the same
US5728631A (en) * 1995-09-29 1998-03-17 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming a low capacitance dielectric layer
US5923179A (en) * 1996-03-29 1999-07-13 Intel Corporation Thermal enhancing test/burn in socket for C4 and tab packaging
JP3305211B2 (ja) * 1996-09-10 2002-07-22 松下電器産業株式会社 半導体装置及びその製造方法
US5985765A (en) * 1998-05-11 1999-11-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method for reducing bonding pad loss using a capping layer when etching bonding pad passivation openings

Also Published As

Publication number Publication date
KR100360387B1 (ko) 2002-11-13
JP2002500445A (ja) 2002-01-08
WO1999034442A1 (en) 1999-07-08
US20020064929A1 (en) 2002-05-30
AU1917299A (en) 1999-07-19
KR20010033663A (ko) 2001-04-25
US6143638A (en) 2000-11-07
US6566737B2 (en) 2003-05-20

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