JP4072965B2 - Pfetビットスイッチを使用するdramの直接書き込みシステムおよび方法 - Google Patents
Pfetビットスイッチを使用するdramの直接書き込みシステムおよび方法 Download PDFInfo
- Publication number
- JP4072965B2 JP4072965B2 JP2004243931A JP2004243931A JP4072965B2 JP 4072965 B2 JP4072965 B2 JP 4072965B2 JP 2004243931 A JP2004243931 A JP 2004243931A JP 2004243931 A JP2004243931 A JP 2004243931A JP 4072965 B2 JP4072965 B2 JP 4072965B2
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- Prior art keywords
- pfet
- bit line
- true
- bit
- complementary
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1096—Write circuits, e.g. I/O line write drivers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/229—Timing of a write operation
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
Description
202 論理入力ノード
204 タイミング図
102 センス増幅器
104 センス増幅器
106 センス増幅器
108 センス増幅器
Claims (2)
- 1つまたは複数のメモリ・セルを有するメモリ・アレイ・デバイスの制御回路であって、
前記メモリ・セルの各々に結合された真ビットライン(BT)および相補ビットライン(BC)と、
前記真ビットライン(BT)および相補ビットライン(BC)に結合されたセンス増幅器と、
前記メモリ・セルに書き込みデータを送り又は前記メモリ・セルから読出しデータを受け取る論理入力回路であって、真データ・ライン(FT)、相補データ・ライン(FC)、書込み制御信号(WRN)送信用バス、ゲートが前記真データ・ライン(FT)に接続され且つソースが電源電圧に接続されたPFET(FT第1PFET)、ゲートが前記相補データ・ライン(FC)に接続され且つソースが電源電圧に接続されたPFET(FC第1PFET)、前記FT第1PFETのセンス増幅器側に、前記FT第1PFETと直列に接続され且つゲートが前記書込み制御信号(WRN)送信用バスに接続されたPFET(FT第2PFET)、及び、前記FC第1PFETのセンス増幅器側に、前記FC第1PFETと直列に接続され且つゲートが前記書込み制御信号(WRN)送信用バスに接続されたPFET(FC第2PFET)、を備える、論理入力回路と、
前記真ビットライン(BT)を、前記FC第2PFETのソースに接続された相補ローカル・データ・ラインに選択的に結合するためのPFETビットスイッチ(BTPFET)であって、ドレインが前記相補ローカル・データ・ラインに且つソースが前記真ビットライン(BT)に接続された、PFETビットスイッチ(BTPFET)と、
相補ビットライン(BC)を、前記FT第2PFETのソースに接続された真ローカル・データ・ライン(FT)に選択的に結合するためのPFETビットスイッチ(BCPFET)であって、ドレインが前記真ローカル・データ・ラインに且つソースが前記相補ビットライン(BC)に接続された、PFETビットスイッチ(BCPFET)と、
前記真ビットライン(BT)および相補ビットライン(BC)を接地レベルにプリチャージするためのプリチャージ回路であって、ゲートがプリチャージ制御信号(EQP)送信用バスに、前記真ビットライン(BT)及び前記相補ビットライン(BC)にソース及びドレインが夫々接続されたNFETと、
を備え、
前記PFETビットスイッチ(BCPFET)及びPFETビットスイッチ(BTPFET)は、前記真ビットライン(BT)および相補ビットライン(BC)上の信号形成の終了前であって前記センス増幅器の活性化前に、列選択信号により活性化され、前記選択されたメモリ・セルへの前記書き込み動作が開始される制御回路。 - 請求項1記載の制御回路を備える、ダイナミック・ランダム・アクセス・メモリ・アレイ。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/604,909 US6788591B1 (en) | 2003-08-26 | 2003-08-26 | System and method for direct write to dynamic random access memory (DRAM) using PFET bit-switch |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005071589A JP2005071589A (ja) | 2005-03-17 |
JP4072965B2 true JP4072965B2 (ja) | 2008-04-09 |
Family
ID=32927850
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004243931A Expired - Fee Related JP4072965B2 (ja) | 2003-08-26 | 2004-08-24 | Pfetビットスイッチを使用するdramの直接書き込みシステムおよび方法 |
Country Status (2)
Country | Link |
---|---|
US (1) | US6788591B1 (ja) |
JP (1) | JP4072965B2 (ja) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7286385B2 (en) * | 2005-07-27 | 2007-10-23 | International Business Machines Corporation | Differential and hierarchical sensing for memory circuits |
US20090073786A1 (en) * | 2007-09-14 | 2009-03-19 | United Memories, Inc. | Early write with data masking technique for integrated circuit dynamic random access memory (dram) devices and those incorporating embedded dram |
FR2935064B1 (fr) * | 2008-08-18 | 2011-04-29 | St Microelectronics Crolles 2 | Memoire a circuits de lecture/ecriture partage |
US11023171B2 (en) * | 2019-07-17 | 2021-06-01 | Micron Technology, Inc. | Performing a refresh operation based on a write to read time difference |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5249159A (en) * | 1987-05-27 | 1993-09-28 | Hitachi, Ltd. | Semiconductor memory |
JP2876830B2 (ja) * | 1991-06-27 | 1999-03-31 | 日本電気株式会社 | 半導体記憶装置 |
JP2001101863A (ja) * | 1999-09-27 | 2001-04-13 | Fujitsu Ltd | 半導体集積回路およびその制御方法 |
US6400629B1 (en) | 2001-06-29 | 2002-06-04 | International Business Machines Corporation | System and method for early write to memory by holding bitline at fixed potential |
-
2003
- 2003-08-26 US US10/604,909 patent/US6788591B1/en not_active Expired - Lifetime
-
2004
- 2004-08-24 JP JP2004243931A patent/JP4072965B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US6788591B1 (en) | 2004-09-07 |
JP2005071589A (ja) | 2005-03-17 |
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