FR2935064B1 - Memoire a circuits de lecture/ecriture partage - Google Patents

Memoire a circuits de lecture/ecriture partage

Info

Publication number
FR2935064B1
FR2935064B1 FR0855604A FR0855604A FR2935064B1 FR 2935064 B1 FR2935064 B1 FR 2935064B1 FR 0855604 A FR0855604 A FR 0855604A FR 0855604 A FR0855604 A FR 0855604A FR 2935064 B1 FR2935064 B1 FR 2935064B1
Authority
FR
France
Prior art keywords
read
memory
write circuits
circuits sharing
sharing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0855604A
Other languages
English (en)
Other versions
FR2935064A1 (fr
Inventor
Marc Vernet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Crolles 2 SAS
Original Assignee
STMicroelectronics Crolles 2 SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Crolles 2 SAS filed Critical STMicroelectronics Crolles 2 SAS
Priority to FR0855604A priority Critical patent/FR2935064B1/fr
Priority to US12/540,784 priority patent/US7948811B2/en
Publication of FR2935064A1 publication Critical patent/FR2935064A1/fr
Application granted granted Critical
Publication of FR2935064B1 publication Critical patent/FR2935064B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1096—Write circuits, e.g. I/O line write drivers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/002—Isolation gates, i.e. gates coupling bit lines to the sense amplifier
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
FR0855604A 2008-08-18 2008-08-18 Memoire a circuits de lecture/ecriture partage Expired - Fee Related FR2935064B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0855604A FR2935064B1 (fr) 2008-08-18 2008-08-18 Memoire a circuits de lecture/ecriture partage
US12/540,784 US7948811B2 (en) 2008-08-18 2009-08-13 Memory with shared read/write circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0855604A FR2935064B1 (fr) 2008-08-18 2008-08-18 Memoire a circuits de lecture/ecriture partage

Publications (2)

Publication Number Publication Date
FR2935064A1 FR2935064A1 (fr) 2010-02-19
FR2935064B1 true FR2935064B1 (fr) 2011-04-29

Family

ID=40527631

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0855604A Expired - Fee Related FR2935064B1 (fr) 2008-08-18 2008-08-18 Memoire a circuits de lecture/ecriture partage

Country Status (2)

Country Link
US (1) US7948811B2 (fr)
FR (1) FR2935064B1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8873314B2 (en) 2010-11-05 2014-10-28 Micron Technology, Inc. Circuits and methods for providing data to and from arrays of memory cells

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10121837C1 (de) * 2001-05-04 2002-12-05 Infineon Technologies Ag Speicherschaltung mit mehreren Speicherbereichen
JP2004234810A (ja) * 2003-02-03 2004-08-19 Renesas Technology Corp 半導体記憶装置
US6788591B1 (en) * 2003-08-26 2004-09-07 International Business Machines Corporation System and method for direct write to dynamic random access memory (DRAM) using PFET bit-switch
US7684263B2 (en) * 2008-01-17 2010-03-23 International Business Machines Corporation Method and circuit for implementing enhanced SRAM write and read performance ring oscillator

Also Published As

Publication number Publication date
US7948811B2 (en) 2011-05-24
US20100039874A1 (en) 2010-02-18
FR2935064A1 (fr) 2010-02-19

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Legal Events

Date Code Title Description
ST Notification of lapse

Effective date: 20130430