JP4032317B2 - チップ実装法 - Google Patents

チップ実装法 Download PDF

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Publication number
JP4032317B2
JP4032317B2 JP20687696A JP20687696A JP4032317B2 JP 4032317 B2 JP4032317 B2 JP 4032317B2 JP 20687696 A JP20687696 A JP 20687696A JP 20687696 A JP20687696 A JP 20687696A JP 4032317 B2 JP4032317 B2 JP 4032317B2
Authority
JP
Japan
Prior art keywords
substrate
chip
electrode
adhesive
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP20687696A
Other languages
English (en)
Japanese (ja)
Other versions
JPH1050930A5 (https=
JPH1050930A (ja
Inventor
功 塚越
宏治 小林
和也 松田
直樹 福嶋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Hitachi Chemical Co Ltd
Showa Denko Materials Co Ltd
Resonac Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd, Showa Denko Materials Co Ltd, Resonac Corp filed Critical Hitachi Chemical Co Ltd
Priority to JP20687696A priority Critical patent/JP4032317B2/ja
Publication of JPH1050930A publication Critical patent/JPH1050930A/ja
Publication of JPH1050930A5 publication Critical patent/JPH1050930A5/ja
Application granted granted Critical
Publication of JP4032317B2 publication Critical patent/JP4032317B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/303—Assembling printed circuits with electric components, e.g. with resistors with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/328—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by welding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07125—Means for controlling the bonding environment, e.g. valves or vacuum pumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques

Landscapes

  • Wire Bonding (AREA)
JP20687696A 1996-08-06 1996-08-06 チップ実装法 Expired - Fee Related JP4032317B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP20687696A JP4032317B2 (ja) 1996-08-06 1996-08-06 チップ実装法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP20687696A JP4032317B2 (ja) 1996-08-06 1996-08-06 チップ実装法

Related Child Applications (3)

Application Number Title Priority Date Filing Date
JP2003199806A Division JP2004031975A (ja) 2003-07-22 2003-07-22 接続装置
JP2006257284A Division JP4563362B2 (ja) 2006-09-22 2006-09-22 チップ実装法
JP2007101704A Division JP4780023B2 (ja) 2007-04-09 2007-04-09 マルチチップモジュールの実装方法

Publications (3)

Publication Number Publication Date
JPH1050930A JPH1050930A (ja) 1998-02-20
JPH1050930A5 JPH1050930A5 (https=) 2004-08-12
JP4032317B2 true JP4032317B2 (ja) 2008-01-16

Family

ID=16530517

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20687696A Expired - Fee Related JP4032317B2 (ja) 1996-08-06 1996-08-06 チップ実装法

Country Status (1)

Country Link
JP (1) JP4032317B2 (https=)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11688716B2 (en) 2020-05-12 2023-06-27 Samsung Electronics Co., Ltd. Semiconductor chip mounting tape and method of manufacturing semiconductor package using the tape

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1030349B2 (de) 1999-01-07 2013-12-11 Kulicke & Soffa Die Bonding GmbH Verfahren und Vorrichtung zum Behandeln von auf einem Substrat angeordneten elektronischen Bauteilen, insbesondere von Halbleiterchips
JP4513235B2 (ja) * 2001-05-31 2010-07-28 ソニー株式会社 フリップチップ実装装置
JP4710205B2 (ja) * 2001-09-06 2011-06-29 ソニー株式会社 フリップチップ実装方法
JP2008098608A (ja) * 2006-09-15 2008-04-24 Lintec Corp 半導体装置の製造方法
EP2063465A4 (en) 2006-09-15 2012-08-08 Lintec Corp PROCESS FOR MANUFACTURING A SEMICONDUCTOR CONSTRUCTION ELEMENT
JP2008159820A (ja) 2006-12-22 2008-07-10 Tdk Corp 電子部品の一括実装方法、及び電子部品内蔵基板の製造方法
JP2008159819A (ja) * 2006-12-22 2008-07-10 Tdk Corp 電子部品の実装方法、電子部品内蔵基板の製造方法、及び電子部品内蔵基板
JP4959527B2 (ja) * 2007-11-30 2012-06-27 リンテック株式会社 半導体装置の製造方法
JP4360446B1 (ja) * 2008-10-16 2009-11-11 住友ベークライト株式会社 半導体装置の製造方法及び半導体装置
JP2010007076A (ja) * 2009-08-07 2010-01-14 Hitachi Chem Co Ltd 異方導電性接着フィルム
JP5421157B2 (ja) * 2010-03-12 2014-02-19 日東シンコー株式会社 半導体モジュールの製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11688716B2 (en) 2020-05-12 2023-06-27 Samsung Electronics Co., Ltd. Semiconductor chip mounting tape and method of manufacturing semiconductor package using the tape

Also Published As

Publication number Publication date
JPH1050930A (ja) 1998-02-20

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