JP3978207B2 - 低誘電率絶縁膜の形成方法 - Google Patents
低誘電率絶縁膜の形成方法 Download PDFInfo
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- JP3978207B2 JP3978207B2 JP2004375428A JP2004375428A JP3978207B2 JP 3978207 B2 JP3978207 B2 JP 3978207B2 JP 2004375428 A JP2004375428 A JP 2004375428A JP 2004375428 A JP2004375428 A JP 2004375428A JP 3978207 B2 JP3978207 B2 JP 3978207B2
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- Prior art keywords
- dielectric constant
- insulating film
- low dielectric
- fine particles
- constant insulating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05075—Plural internal layers
- H01L2224/0508—Plural internal layers being stacked
- H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
- H01L2224/05089—Disposition of the additional element
- H01L2224/05093—Disposition of the additional element of a plurality of vias
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0102—Calcium [Ca]
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Description
以下、本発明の第1の参考例について図1を参照しながら説明する。第1の参考例は、溶液よりなる低誘電率絶縁膜形成用材料である。
以下、本発明の第2の参考例について、図2(a) 及び(b) を参照しながら説明する。第2の参考例は、微粒子よりなる低誘電率絶縁膜形成用材料である。
以下、本発明の第3の参考例について、図3(a) 及び(b) を参照しながら説明する。第3の参考例は、微粒子8よりなる低誘電率絶縁膜形成用材料である。
以下、本発明の第4の参考例について、図4(a) 〜(c) を参照しながら説明する。第4の参考例は、化学反応により合成される微粒子よりなる低誘電率絶縁膜形成材料である。
以下、本発明の第5の実施形態について図5(a) 〜(e) を参照しながら説明する。第5の実施形態は、第1の参考例に係る溶液を用いる低誘電率絶縁膜及びその形成方法である。
以下、本発明の第6の実施形態について図6(a) 、(b) 及び図7(a) 、(b) を参照しながら説明する。第6の実施形態も、第1の参考例に係る溶液を用いる低誘電率絶縁膜及びその製造方法である。
以下、本発明の第7の参考例について図8を参照しながら説明する。第7の参考例は、低誘電率絶縁膜を有する半導体装置である。
2 シリコンレジン
3 空孔を有する微粒子
4 溶媒
5 ポーラス構造体
6 微粒子
7 ポーラス構造体
8 微粒子
9a 微粒子
10A 第1の微粒子
10B 第2の微粒子
10C 第3の微粒子
10a 有機ポリマー
10b 有機ポリマー
11 スピンドル
12 半導体ウェハ
13 薬液供給管
14 溶液
15 薄膜
15A 低誘電率絶縁膜
16 ホットプレート
17 ホットプレート
18 電気炉
20 半導体ウェハ
21 低誘電率絶縁膜
22 シリコンレジンからなる構造体
23 微粒子
24 シリコンレジンからなる構造体
30 半導体ウェハ
Claims (7)
- シリコン原子と酸素原子の結合を含み且つ空孔を有するゼオライト結晶よりなる微粒子と、樹脂と、前記樹脂と前記微粒子との結合を強化するジメチルジメトキシシランと、溶媒とを含む溶液を基板上に塗布して薄膜を形成する工程と、前記基板を加熱することにより低誘電率絶縁膜を形成する工程とを備えていることを特徴とする低誘電率絶縁膜の形成方法。
- 前記微粒子のサイズは、1nm以上で且つ30nm以下であることを特徴とする請求項1に記載の低誘電率絶縁膜の形成方法。
- 前記微粒子の空孔のサイズは、0.5nm以上で且つ3nm以下であることを特徴とする請求項1に記載の低誘電率絶縁膜の形成方法。
- 前記樹脂はシリコンレジンであることを特徴とする請求項1に記載の低誘電率絶縁膜の形成方法。
- 前記シリコンレジンは有機シリコンを含むことを特徴とする請求項4に記載の低誘電率絶縁膜の形成方法。
- 前記樹脂は有機ポリマーであることを特徴とする請求項1に記載の低誘電率絶縁膜の形成方法。
- 前記基板を加熱する工程は、前記微粒子と前記樹脂とを結合させる工程を含むことを特徴とする請求項1に記載の低誘電率絶縁膜の形成方法。
Priority Applications (1)
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JP2004375428A JP3978207B2 (ja) | 2004-12-27 | 2004-12-27 | 低誘電率絶縁膜の形成方法 |
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JP2004375428A JP3978207B2 (ja) | 2004-12-27 | 2004-12-27 | 低誘電率絶縁膜の形成方法 |
Related Parent Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2002137893A Division JP3859540B2 (ja) | 2002-05-14 | 2002-05-14 | 低誘電率絶縁膜形成用材料 |
Related Child Applications (1)
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JP2006112979A Division JP2006210947A (ja) | 2006-04-17 | 2006-04-17 | 低誘電率絶縁膜及びその形成方法、並びに半導体装置 |
Publications (2)
Publication Number | Publication Date |
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JP2005167266A JP2005167266A (ja) | 2005-06-23 |
JP3978207B2 true JP3978207B2 (ja) | 2007-09-19 |
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JP2004375428A Expired - Lifetime JP3978207B2 (ja) | 2004-12-27 | 2004-12-27 | 低誘電率絶縁膜の形成方法 |
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Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4950136B2 (ja) * | 2008-06-18 | 2012-06-13 | 信越ポリマー株式会社 | 低誘電率絶縁膜 |
CN102471590B (zh) | 2009-07-14 | 2015-05-20 | 花王株式会社 | 低介电树脂组合物 |
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- 2004-12-27 JP JP2004375428A patent/JP3978207B2/ja not_active Expired - Lifetime
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