JP3939336B2 - 半導体集積回路用のテストプログラムを開発する方法および構造 - Google Patents

半導体集積回路用のテストプログラムを開発する方法および構造 Download PDF

Info

Publication number
JP3939336B2
JP3939336B2 JP2006502670A JP2006502670A JP3939336B2 JP 3939336 B2 JP3939336 B2 JP 3939336B2 JP 2006502670 A JP2006502670 A JP 2006502670A JP 2006502670 A JP2006502670 A JP 2006502670A JP 3939336 B2 JP3939336 B2 JP 3939336B2
Authority
JP
Japan
Prior art keywords
test
pattern
file
name
module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2006502670A
Other languages
English (en)
Japanese (ja)
Other versions
JP2006520947A (ja
JP2006520947A5 (enExample
Inventor
ラマチャンドラン クリシュナスワミー
ハルサンジート シング
アンカン プラマニック
マーク エルストン
リーオン チェン
敏明 足立
善文 田原
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advantest Corp
Original Assignee
Advantest Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/404,002 external-priority patent/US7460988B2/en
Priority claimed from US10/403,817 external-priority patent/US7290192B2/en
Application filed by Advantest Corp filed Critical Advantest Corp
Publication of JP2006520947A publication Critical patent/JP2006520947A/ja
Publication of JP2006520947A5 publication Critical patent/JP2006520947A5/ja
Application granted granted Critical
Publication of JP3939336B2 publication Critical patent/JP3939336B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/319—Tester hardware, i.e. output processing circuits
    • G01R31/31903—Tester hardware, i.e. output processing circuits tester configuration
    • G01R31/31907—Modular tester, e.g. controlling and coordinating instruments in a bus based architecture
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318307—Generation of test inputs, e.g. test vectors, patterns or sequences computer-aided, e.g. automatic test program generator [ATPG], program translations, test program debugging
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Non-Volatile Memory (AREA)
JP2006502670A 2003-02-14 2004-02-16 半導体集積回路用のテストプログラムを開発する方法および構造 Expired - Fee Related JP3939336B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US44783903P 2003-02-14 2003-02-14
US44962203P 2003-02-24 2003-02-24
US10/404,002 US7460988B2 (en) 2003-03-31 2003-03-31 Test emulator, test module emulator, and record medium storing program therein
US10/403,817 US7290192B2 (en) 2003-03-31 2003-03-31 Test apparatus and test method for testing plurality of devices in parallel
PCT/JP2004/001649 WO2004072670A1 (en) 2003-02-14 2004-02-16 Method and structure to develop a test program for semiconductor integrated circuits

Publications (3)

Publication Number Publication Date
JP2006520947A JP2006520947A (ja) 2006-09-14
JP2006520947A5 JP2006520947A5 (enExample) 2006-10-26
JP3939336B2 true JP3939336B2 (ja) 2007-07-04

Family

ID=32872965

Family Applications (3)

Application Number Title Priority Date Filing Date
JP2006502670A Expired - Fee Related JP3939336B2 (ja) 2003-02-14 2004-02-16 半導体集積回路用のテストプログラムを開発する方法および構造
JP2006502669A Expired - Fee Related JP3954639B2 (ja) 2003-02-14 2004-02-16 集積回路をテストする方法および装置
JP2006252498A Withdrawn JP2007052028A (ja) 2003-02-14 2006-09-19 集積回路をテストする方法および装置

Family Applications After (2)

Application Number Title Priority Date Filing Date
JP2006502669A Expired - Fee Related JP3954639B2 (ja) 2003-02-14 2004-02-16 集積回路をテストする方法および装置
JP2006252498A Withdrawn JP2007052028A (ja) 2003-02-14 2006-09-19 集積回路をテストする方法および装置

Country Status (8)

Country Link
EP (2) EP1592975B1 (enExample)
JP (3) JP3939336B2 (enExample)
KR (2) KR20050101216A (enExample)
CN (1) CN1784609B (enExample)
AT (1) ATE384269T1 (enExample)
DE (1) DE602004011320T2 (enExample)
TW (1) TWI344595B (enExample)
WO (2) WO2004072670A1 (enExample)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007528993A (ja) * 2004-05-22 2007-10-18 株式会社アドバンテスト 半導体集積回路のための試験プログラムを開発するための方法及び構造

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040225459A1 (en) 2003-02-14 2004-11-11 Advantest Corporation Method and structure to develop a test program for semiconductor integrated circuits
US7184917B2 (en) 2003-02-14 2007-02-27 Advantest America R&D Center, Inc. Method and system for controlling interchangeable components in a modular test system
US7197416B2 (en) 2004-05-22 2007-03-27 Advantest America R&D Center, Inc. Supporting calibration and diagnostics in an open architecture test system
US7430486B2 (en) 2004-05-22 2008-09-30 Advantest America R&D Center, Inc. Datalog support in a modular test system
US7210087B2 (en) 2004-05-22 2007-04-24 Advantest America R&D Center, Inc. Method and system for simulating a modular test system
US7543200B2 (en) * 2005-02-17 2009-06-02 Advantest Corporation Method and system for scheduling tests in a parallel test system
US8214800B2 (en) * 2005-03-02 2012-07-03 Advantest Corporation Compact representation of vendor hardware module revisions in an open architecture test system
JP2006275986A (ja) * 2005-03-30 2006-10-12 Advantest Corp 診断プログラム、切替プログラム、試験装置、および診断方法
US7253607B2 (en) * 2005-04-29 2007-08-07 Teradyne, Inc. Site-aware objects
EP1724599B1 (en) * 2005-05-20 2007-08-22 Agilent Technologies, Inc. Test device with test parameter adaptation
US7788562B2 (en) * 2006-11-29 2010-08-31 Advantest Corporation Pattern controlled, full speed ATE compare capability for deterministic and non-deterministic IC data
JP5022262B2 (ja) * 2008-02-12 2012-09-12 株式会社アドバンテスト デバッグ中にツールを使用可能な試験システム及び方法
US8949784B2 (en) 2008-10-03 2015-02-03 Microsoft Technology Licensing, Llc Type system for declarative data scripting language
US8692566B2 (en) 2008-12-08 2014-04-08 Advantest Corporation Test apparatus and test method
US7906981B1 (en) 2009-09-10 2011-03-15 Advantest Corporation Test apparatus and test method
US8405415B2 (en) 2009-09-10 2013-03-26 Advantest Corporation Test apparatus synchronous module and synchronous method
US8261119B2 (en) 2009-09-10 2012-09-04 Advantest Corporation Test apparatus for testing device has synchronization module which synchronizes analog test module to digital test module based on synchronization signal received from digital test module
CN102193553A (zh) * 2010-03-02 2011-09-21 珠海格力电器股份有限公司 空调控制器功能的测试方法、装置及系统
TWI470421B (zh) * 2010-03-16 2015-01-21 Via Tech Inc 微處理器及其除錯方法
US8868371B2 (en) * 2011-09-09 2014-10-21 Infineon Technologies Ag Method and device for determining test sets of operating parameter values for an electronic component
US9400307B2 (en) 2013-03-13 2016-07-26 Keysight Technologies, Inc. Test system for improving throughout or maintenance properties of semiconductor testing
CN104144084B (zh) * 2013-05-10 2017-12-01 腾讯科技（深圳）有限公司 终端状态的监控方法及装置
CN104298590B (zh) * 2013-07-16 2019-05-10 爱德万测试公司 用于按管脚apg的快速语义处理器
US10539609B2 (en) * 2014-12-08 2020-01-21 Nxp Usa, Inc. Method of converting high-level test specification language to low-level test implementation language
KR20180084385A (ko) 2017-01-17 2018-07-25 한국항공우주산업 주식회사 데이터베이스 기반의 자동시험장비의 운용 시스템 및 그 운용 방법
US10592370B2 (en) * 2017-04-28 2020-03-17 Advantest Corporation User control of automated test features with software application programming interface (API)
US10890621B2 (en) * 2017-05-30 2021-01-12 Raytheon Company Systems and methods for testing an embedded controller
KR102179508B1 (ko) 2019-07-05 2020-11-16 한국항공우주산업 주식회사 자동화 시험장비의 운용 시스템
TWI748300B (zh) * 2019-12-09 2021-12-01 新唐科技股份有限公司 測試系統和測試方法
CN111459840A (zh) * 2020-04-26 2020-07-28 恩亿科(北京)数据科技有限公司 一种进程的调试方法及装置
CN112311627B (zh) * 2020-10-29 2022-09-09 许昌许继软件技术有限公司 一种基于xml格式的规约描述文件的电力规约通用测试方法及系统
CN113051114A (zh) * 2021-03-19 2021-06-29 无锡市软测认证有限公司 一种用于提高芯片测试效率的方法
US11574696B2 (en) * 2021-04-12 2023-02-07 Nanya Technology Corporation Semiconductor test system and method
KR102314419B1 (ko) * 2021-07-27 2021-10-19 (주) 에이블리 반도체 테스트 패턴 발생 장치 및 방법
CN114818669B (zh) * 2022-04-26 2023-06-27 北京中科智加科技有限公司 一种人名纠错模型的构建方法和计算机设备
KR102790875B1 (ko) * 2022-06-27 2025-04-04 주식회사 와이씨 반도체 디바이스 할당 정보에 따른 전원 공급 제어를 위한 반도체 디바이스 테스트 장치 및 그 시스템
CN115630594B (zh) * 2022-12-19 2023-03-21 杭州加速科技有限公司 一种芯片设计仿真文件到Pattern文件的转换方法及其系统
CN116520754B (zh) * 2023-06-27 2023-09-22 厦门芯泰达集成电路有限公司 基于预加载模式的dps模块控制方法、系统
CN117291145A (zh) * 2023-11-24 2023-12-26 之江实验室 片上系统的验证方法、系统和电子装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02246841A (ja) * 1989-03-17 1990-10-02 Hitachi Ltd 自動車の制御装置及び制御方法
US5488573A (en) * 1993-09-02 1996-01-30 Matsushita Electric Industrial Co., Ltd. Method for generating test programs
US6182258B1 (en) * 1997-06-03 2001-01-30 Verisity Ltd. Method and apparatus for test generation during circuit design
US6028439A (en) * 1997-10-31 2000-02-22 Credence Systems Corporation Modular integrated circuit tester with distributed synchronization and control
US6195774B1 (en) * 1998-08-13 2001-02-27 Xilinx, Inc. Boundary-scan method using object-oriented programming language
US6779140B2 (en) * 2001-06-29 2004-08-17 Agilent Technologies, Inc. Algorithmically programmable memory tester with test sites operating in a slave mode

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007528993A (ja) * 2004-05-22 2007-10-18 株式会社アドバンテスト 半導体集積回路のための試験プログラムを開発するための方法及び構造

Also Published As

Publication number Publication date
CN1784609B (zh) 2011-02-23
EP1592975A1 (en) 2005-11-09
JP2006518460A (ja) 2006-08-10
KR20050099626A (ko) 2005-10-14
KR20050101216A (ko) 2005-10-20
TW200508855A (en) 2005-03-01
CN1784609A (zh) 2006-06-07
ATE384269T1 (de) 2008-02-15
WO2004072669A1 (en) 2004-08-26
EP1592975B1 (en) 2008-03-26
DE602004011320D1 (de) 2008-03-06
JP2006520947A (ja) 2006-09-14
EP1592976A1 (en) 2005-11-09
EP1592976B1 (en) 2008-01-16
JP3954639B2 (ja) 2007-08-08
WO2004072670A1 (en) 2004-08-26
JP2007052028A (ja) 2007-03-01
TWI344595B (en) 2011-07-01
DE602004011320T2 (de) 2009-02-05

Similar Documents

Publication Publication Date Title
JP3939336B2 (ja) 半導体集積回路用のテストプログラムを開発する方法および構造
US8255198B2 (en) Method and structure to develop a test program for semiconductor integrated circuits
US7197417B2 (en) Method and structure to develop a test program for semiconductor integrated circuits
US7184917B2 (en) Method and system for controlling interchangeable components in a modular test system
JP4332200B2 (ja) モジュール式試験システム内のパターンオブジェクトファイルを管理するための方法およびモジュール式試験システム
JP4332179B2 (ja) パターンコンパイラ
JP2007528993A5 (enExample)
KR20070023762A (ko) 반도체 집적 회로를 위한 테스트 프로그램을 개발하는 방법및 구조
KR20070035507A (ko) 모듈식 테스트 시스템에서 호환성있는 컴포넌트를 제어하는방법 및 시스템

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060829

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20060829

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20061004

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20061024

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20061222

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20070227

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20070327

R150 Certificate of patent or registration of utility model

Ref document number: 3939336

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110406

Year of fee payment: 4

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120406

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130406

Year of fee payment: 6

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130406

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130406

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140406

Year of fee payment: 7

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees