JP3920447B2 - 絶縁体一化合物半導体界面構造および製造方法 - Google Patents

絶縁体一化合物半導体界面構造および製造方法 Download PDF

Info

Publication number
JP3920447B2
JP3920447B2 JP06780298A JP6780298A JP3920447B2 JP 3920447 B2 JP3920447 B2 JP 3920447B2 JP 06780298 A JP06780298 A JP 06780298A JP 6780298 A JP6780298 A JP 6780298A JP 3920447 B2 JP3920447 B2 JP 3920447B2
Authority
JP
Japan
Prior art keywords
compound semiconductor
band gap
insulator
spacer layer
interface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP06780298A
Other languages
English (en)
Japanese (ja)
Other versions
JPH10275806A (ja
JPH10275806A5 (enExample
Inventor
マシュアス・パスラック
ジュン・ワン
ジョナサン・ケイ・アブロクワ
ジヒイ・ジミー・ユ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NXP USA Inc
Original Assignee
NXP USA Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NXP USA Inc filed Critical NXP USA Inc
Publication of JPH10275806A publication Critical patent/JPH10275806A/ja
Publication of JPH10275806A5 publication Critical patent/JPH10275806A5/ja
Application granted granted Critical
Publication of JP3920447B2 publication Critical patent/JP3920447B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00Electrodes of devices having potential barriers
    • H10D64/60Electrodes characterised by their materials
    • H10D64/66Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/68Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
    • H10D64/691Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator comprising metallic compounds, e.g. metal oxides or metal silicates 
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158Making the insulator
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28264Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being a III-V compound
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/015Manufacture or treatment of FETs having heterojunction interface channels or heterojunction gate electrodes, e.g. HEMT
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/80FETs having rectifying junction gate electrodes
    • H10D30/801FETs having heterojunction gate electrodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Formation Of Insulating Films (AREA)
  • Junction Field-Effect Transistors (AREA)
JP06780298A 1997-03-04 1998-03-02 絶縁体一化合物半導体界面構造および製造方法 Expired - Lifetime JP3920447B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/812,952 US6359294B1 (en) 1997-03-04 1997-03-04 Insulator-compound semiconductor interface structure
US812952 1997-03-04

Publications (3)

Publication Number Publication Date
JPH10275806A JPH10275806A (ja) 1998-10-13
JPH10275806A5 JPH10275806A5 (enExample) 2005-03-17
JP3920447B2 true JP3920447B2 (ja) 2007-05-30

Family

ID=25211069

Family Applications (1)

Application Number Title Priority Date Filing Date
JP06780298A Expired - Lifetime JP3920447B2 (ja) 1997-03-04 1998-03-02 絶縁体一化合物半導体界面構造および製造方法

Country Status (4)

Country Link
US (1) US6359294B1 (enExample)
EP (1) EP0863539B1 (enExample)
JP (1) JP3920447B2 (enExample)
DE (1) DE69827058T2 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20130092548A (ko) 2010-08-31 2013-08-20 스미또모 가가꾸 가부시키가이샤 반도체 기판, 절연 게이트형 전계 효과 트랜지스터 및 반도체 기판의 제조 방법
CN103098188B (zh) 2010-08-31 2016-03-30 住友化学株式会社 半导体基板及绝缘栅极型场效电子晶体管
CN106560928B (zh) * 2015-09-28 2019-11-08 河北大学 一种电荷俘获型存储元件及其制备工艺

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4859253A (en) * 1988-07-20 1989-08-22 International Business Machines Corporation Method for passivating a compound semiconductor surface and device having improved semiconductor-insulator interface
US5124762A (en) * 1990-12-31 1992-06-23 Honeywell Inc. Gaas heterostructure metal-insulator-semiconductor integrated circuit technology
US5334865A (en) * 1991-07-31 1994-08-02 Allied-Signal Inc. MODFET structure for threshold control
US5597768A (en) * 1996-03-21 1997-01-28 Motorola, Inc. Method of forming a Ga2 O3 dielectric layer
US5747838A (en) * 1996-11-27 1998-05-05 The Regents Of The University Of California Ultra-low phase noise GaAs MOSFETs

Also Published As

Publication number Publication date
DE69827058D1 (de) 2004-11-25
US6359294B1 (en) 2002-03-19
DE69827058T2 (de) 2005-03-03
JPH10275806A (ja) 1998-10-13
EP0863539A1 (en) 1998-09-09
EP0863539B1 (en) 2004-10-20

Similar Documents

Publication Publication Date Title
JP3251889B2 (ja) 中間ギャップ作業関数タングステン・ゲートの製造方法
US7105895B2 (en) Epitaxial SiOx barrier/insulation layer
TWI452693B (zh) Semiconductor transistor
US8872238B2 (en) Method for manufacturing a low defect interface between a dielectric and a III-V compound
US20120326212A1 (en) HIGH k GATE STACK ON III-V COMPOUND SEMICONDUCTORS
Stevens et al. Demonstration of a silicon field‐effect transistor using AlN as the gate dielectric
JP2000150503A (ja) GaAsやGaNに基づく半導体基体上に酸化物層を含む物品
KR102716586B1 (ko) 채널 이동도를 증가시키기 위한 양자 컴퓨팅 디바이스의 제조 동안의 처리
JPH10289906A (ja) Iii−v族エピタキシャル・ウェハ製造
US20140035001A1 (en) Compound semiconductor structure
JP3023090B2 (ja) 半導体デバイスを有する物品
JP2764049B2 (ja) 化合物半導体装置の製造方法、化合物半導体装置及び電界効果トランジスタ
US5086321A (en) Unpinned oxide-compound semiconductor structures and method of forming same
JP3920447B2 (ja) 絶縁体一化合物半導体界面構造および製造方法
KR20070044441A (ko) 고 k 유전체 재료와 사용되는 계면 층
Nguyen et al. Investigating FinFET sidewall passivation using epitaxial (100) Ge and (110) Ge metal–oxide–semiconductor devices on AlAs/GaAs
JP2004214530A (ja) Mis型化合物半導体装置の製造方法
Akazawa et al. Formation of ultrathin SiNx∕ Si interface control double layer on (001) and (111) GaAs surfaces for ex situ deposition of high-k dielectrics
US20080003752A1 (en) Gate dielectric materials for group III-V enhancement mode transistors
CN102804382A (zh) P型半导体器件
JPH05335346A (ja) 半導体装置及びその製造方法
US20080251814A1 (en) Hetero-bonded semiconductor-on-insulator substrate with an unpinning dielectric layer
JP7743873B2 (ja) 電界効果トランジスタの作製方法
Yamada et al. Fabrication and characterization of novel oxide-free InP metal-insulator-semiconductor FETs having an ultra narrow Si surface quantum well
Asada et al. Epitaxial growth of a metal (CoSi2)/insulator (CaF2) nanometer‐thick heterostructure and its application to quantum‐effect devices

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040412

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040412

A711 Notification of change in applicant

Free format text: JAPANESE INTERMEDIATE CODE: A711

Effective date: 20040927

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20060630

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060711

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20061011

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20061016

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070111

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20070206

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20070215

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110223

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120223

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130223

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130223

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20140223

Year of fee payment: 7

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

S533 Written request for registration of change of name

Free format text: JAPANESE INTERMEDIATE CODE: R313533

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

EXPY Cancellation because of completion of term