JP3895884B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP3895884B2 JP3895884B2 JP08178699A JP8178699A JP3895884B2 JP 3895884 B2 JP3895884 B2 JP 3895884B2 JP 08178699 A JP08178699 A JP 08178699A JP 8178699 A JP8178699 A JP 8178699A JP 3895884 B2 JP3895884 B2 JP 3895884B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- back surface
- external connection
- semiconductor device
- semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/01—Manufacture or treatment
- H10W72/0198—Manufacture or treatment batch processes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/851—Dispositions of multiple connectors or interconnections
- H10W72/874—On different surfaces
- H10W72/877—Bump connectors and die-attach connectors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
Landscapes
- Die Bonding (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP08178699A JP3895884B2 (ja) | 1999-03-25 | 1999-03-25 | 半導体装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP08178699A JP3895884B2 (ja) | 1999-03-25 | 1999-03-25 | 半導体装置 |
Related Child Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004285690A Division JP4017625B2 (ja) | 2004-09-30 | 2004-09-30 | 半導体装置の製造方法 |
| JP2006311131A Division JP2007073987A (ja) | 2006-11-17 | 2006-11-17 | 半導体モジュール |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2000277542A JP2000277542A (ja) | 2000-10-06 |
| JP2000277542A5 JP2000277542A5 (https=) | 2005-06-23 |
| JP3895884B2 true JP3895884B2 (ja) | 2007-03-22 |
Family
ID=13756181
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP08178699A Expired - Lifetime JP3895884B2 (ja) | 1999-03-25 | 1999-03-25 | 半導体装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3895884B2 (https=) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7595547B1 (en) | 2005-06-13 | 2009-09-29 | Vishay-Siliconix | Semiconductor die package including cup-shaped leadframe |
| US6744124B1 (en) * | 1999-12-10 | 2004-06-01 | Siliconix Incorporated | Semiconductor die package including cup-shaped leadframe |
| JP2002252318A (ja) | 2001-02-27 | 2002-09-06 | Nec Kansai Ltd | チップ型半導体装置 |
| JP3942500B2 (ja) | 2002-07-02 | 2007-07-11 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
| JP3853263B2 (ja) * | 2002-07-08 | 2006-12-06 | Necエレクトロニクス株式会社 | 半導体装置 |
| DE10249206B3 (de) * | 2002-10-22 | 2004-07-01 | Siemens Ag | Verfahren zum Zusammenbau eines Leistungsbauelements |
| DE10249205B3 (de) * | 2002-10-22 | 2004-08-05 | Siemens Ag | Leistungsbauelementanordnung zur mechatronischen Integration von Leistungsbauelementen |
| US6841865B2 (en) * | 2002-11-22 | 2005-01-11 | International Rectifier Corporation | Semiconductor device having clips for connecting to external elements |
| JP4222092B2 (ja) | 2003-05-07 | 2009-02-12 | 富士電機デバイステクノロジー株式会社 | 半導体ウェハ、半導体装置および半導体装置の製造方法 |
| US20070215997A1 (en) * | 2006-03-17 | 2007-09-20 | Martin Standing | Chip-scale package |
| EP4044226A1 (en) * | 2021-02-16 | 2022-08-17 | Nexperia B.V. | A semiconductor device and a method of manufacturing of a semiconductor device |
-
1999
- 1999-03-25 JP JP08178699A patent/JP3895884B2/ja not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JP2000277542A (ja) | 2000-10-06 |
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