JP3859128B2 - Game machine - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a game machine such as a so-called seven machine, a ball game machine such as a feather, a right object, or an arrangement ball, or a coin-type game machine such as a slot machine.
[0002]
[Prior art]
Conventionally, a variable display device that variably displays identification information such as a plurality of symbols on the game board surface is provided, and another game is started when a predetermined condition is satisfied, for example, when a game ball wins at the start port, and the separate game is started. Then, a plurality of pieces of identification information are variably displayed on the variable display device for a predetermined time, and thereafter the identification information is sequentially stopped, and when each piece of identification information is stopped, the stop mode achieves a specific condition, for example, There is known a gaming machine that gives a specific value to a player based on the fact that the same symbols are gathered).
[0003]
Whether or not the specific value is generated is determined at a timing when the game ball wins a prize at the starting port. In other words, a random number counter that is periodically updated by 1 count in a certain range (for example, a range of 0 to 255 every 2 ms), and when the game ball is won at the start opening, When the value of the read random number counter matches a specific value such as “7”, a specific value such as a jackpot is generated. When the jackpot occurs, a jackpot command is transmitted to the display board of the variable display device via a cable connected to the connector of the control board. In the variable display device, the variable display is controlled based on the received jackpot command, and a jackpot display that stops at a predetermined symbol combination is displayed.
[0004]
[Problems to be solved by the invention]
However, in recent years, fraudulent activity using an unauthorized substrate called a “hanging substrate” has been reported. This fraudulent act is that an illegal substrate is hung between the control substrate and the display substrate of the variable display device (an illegal “hanging substrate” is attached) to unjustly generate a big hit. Specifically, a counter (counter that is regularly updated within a certain range in increments of 1 count) is provided in the “hanging board”, which functions in the same manner as a random number counter for determining the jackpot provided in the gaming machine, By resetting the counter value in accordance with the power-on of the gaming machine (clearing to 0), the occurrence timing of the jackpot in the “hanging board” is grasped. Then, in accordance with the grasped jackpot occurrence timing, illegally generate a starting ball winning signal of the game ball in the “hanging board”, and output it to the control board of the gaming machine to generate an unreasonable jackpot It is.
[0005]
Japanese Patent Application Laid-Open No. 11-70252 discloses a ball game machine that changes the initial value of the random number counter update every n (n is a natural number) of the random number counter that counts the random number value that determines the jackpot. Has been. According to this ball and ball game machine, the initial value of the update of the random number counter that determines whether or not the jackpot is generated is changed every n times, making it impossible to grasp the timing of the jackpot occurrence by the “hanging board”. In the above-mentioned ball game machine, apart from the random number counter, an initial value counter for counting the initial value of the random number counter update within the update range of the random number counter is provided, and the remaining time of the reset interrupt processing that is periodically executed During this period, the value of the initial counter is repeatedly updated. Since the reset interrupt process is a process for controlling the game of the gaming machine, the processing time is shortened depending on the game situation. Since the “hanging board” cannot grasp the time until the reset interrupt processing is long or short, it grasps the value of the initial value counter that is repeatedly updated during the remaining time until the next reset interrupt processing occurs. I can't do it. Therefore, the initial value of the update of the random number counter cannot be grasped by the “hanging board”, and illegal acts by the “hanging board” are prevented.
[0006]
By the way, in the control board, when the RAM clear switch is pressed when the power is turned on, or when it is determined that the contents of the RAM are destroyed, the RAM clear process is executed. For this reason, in the above conventional ball game machine, it is possible to perform an illegal act of generating a jackpot by intentionally generating a RAM clear. That is, when the RAM clear process is executed, the value of the jackpot random number (failure random number) is always initialized to zero, and only in that case, the point where the value of the jackpot random number is a jackpot from the outside of the control board is easy. Can be estimated. In game halls and the like, a great deal of damage has been caused by fraudulent acts that generate a big hit by intentionally generating a RAM clear using a “hanging board”.
[0007]
The present invention has been made to solve such a problem, and an object of the present invention is to provide a gaming machine capable of preventing “an illegal act of generating a jackpot by intentionally generating a RAM clear”. To do.
[0008]
Another object of the present invention is to provide a gaming machine that can easily prevent fraud with a simple configuration.
[0009]
Still another object of the present invention is to provide a gaming machine that can easily prevent fraud with another simple configuration.
[0010]
Still another object of the present invention is to provide a gaming machine that can easily prevent fraud with another simple configuration.
[0011]
Still another object of the present invention is to provide another gaming machine capable of preventing “an illegal act of generating a jackpot by intentionally generating a RAM clear”.
[0012]
Still another object of the present invention is to provide still another gaming machine capable of preventing “an illegal act of generating a jackpot by intentionally generating a RAM clear”.
[0013]
Another object of the present invention is to provide a gaming machine that can easily prevent fraud with a simple configuration.
[0014]
Still another object of the present invention is to provide a gaming machine that can easily prevent fraud with another simple configuration.
[0015]
Still another object of the present invention is to provide a gaming machine that can easily prevent fraud with another simple configuration.
[0016]
[Means for Solving the Problems]
  The gaming machine according to claim 1 includes a main control unit that controls basic progress control of a game, and a variable display device that variably displays a plurality of identification information when a predetermined condition is satisfied, and the stop mode of the variable display device is specified. A gaming machine that gives a player a specific value based on achieving a condition,
  Regularly updated within a certain range, n(N is a natural number.)A random number counter whose initial value is changed every round update,
  A storage unit that stores a storage unit storing a determination program that reads out the value of the random number counter when the predetermined condition is satisfied, and determines whether or not the random number counter is read using the read value of the random number counter.
  Control means for performing the determination of the success / failure by the determination program of the success / failure;
  Storage means for storing data used during execution of the success / failure determination program;
  An initial value counter for counting an initial value for updating the random number counter.A gaming machine,
  A CPU functioning as the control means;
The CPU includes a RAM functioning as the storage unit, and the random number counter is provided in the RAM.
The initial value counter is an external initial value counter provided outside the CPU;
While providing a delay circuit between the CPU and the external initial value counter,
The initial value of the random number counter at the time of initialization of the random number counter is determined by the external initial value counter.
  The gaming machine according to claim 2 includes a main control unit that controls basic progress control of the game, and a variable display device that variably displays a plurality of identification information when a predetermined condition is satisfied, and the stop mode of the variable display device is specified. A gaming machine that gives a player a specific value based on achieving a condition,
A random number counter that is periodically updated within a certain range and whose initial value is changed every time n (n is a natural number) is updated;
A storage unit that stores a storage unit storing a determination program that reads out the value of the random number counter when the predetermined condition is satisfied, and determines whether or not the random number counter is read using the read value of the random number counter.
Control means for performing the determination of the success / failure by the determination program of the success / failure;
Storage means for storing data used during execution of the success / failure determination program;
An initial value counter that counts an initial value for updating the random number counter, and a gaming machine comprising:
  A CPU functioning as the control means;
The CPU includes a RAM functioning as the storage means, the random number counter is provided in the RAM,
As the initial value counter, an internal initial value counter provided in the RAM, and an external initial value counter provided outside the CPU,
While providing a delay circuit between the CPU and the external initial value counter,
In order to determine the initial value of the random number counter when the random number counter is initialized by the external initial value counter, and to update the random number counter when the random number counter is not initialized by the internal initial value counter The initial value is determined.
  In addition, the gaming machine of “the first invention that is disclosed by reference in the present application and whose rights are excluded from the claims” (hereinafter referred to as “reference invention 1”) governs basic progress control of the game. A main control unit and a variable display device that variably displays a plurality of identification information when a predetermined condition is satisfied, and a specific value is given to the player based on the fact that the stop mode of the variable display device achieves the specific condition A gaming machine that
A random number counter that is periodically updated within a certain range, and whose initial value is changed every n times, and
A storage unit that stores a storage unit storing a determination program that reads out the value of the random number counter when the predetermined condition is satisfied, and determines whether or not the random number counter is read using the read value of the random number counter.
Control means for performing the determination of the success / failure by the determination program of the success / failure;
Storage means for storing data used during execution of the success / failure determination program;
An initial value counter for counting an initial value for updating the random number counter;
Delay means for delaying the timing counted by the initial value counter,
The initial value of the random number counter is determined by the value of the initial value counter delayed by the delay means when the random number counter is initialized.
  here,Reference invention 1“N” is a natural number.
[0017]
  In Reference Invention 1,Since the delay means delays the count timing of the initial value counter, it becomes difficult for an unauthorized person to grasp the value (timing) of the initial value counter. Therefore, even if the RAM clear process is executed due to the fraudulent act of the fraudulent person, it becomes difficult to estimate the value of the random number counter (random number of success / failure) from the outside of the control board. You can prevent the act. Here, the delay means of the present invention can be provided, for example, between the initial value counter and the control means.
[0018]
  Also,Reference invention 1In (1)Reference invention 1The initial value counter for counting the initial value for updating the random number counter and the initialization of the random number counter by this initial value counter are provided. The initial value of the random number counter at the time may be determined, or (2)Reference invention 1Two initial value counters for counting the initial value for updating the random number counter, and determining the initial value of the random number counter at the time of initialization of the random number counter by one initial value counter, The initial value counter may be used to determine an initial value for updating the random number counter “when the random number counter is not initialized”. In the latter case (2), both initial value counters may be delayed by the delay means, or only one initial value counter may be delayed by the delay means.
[0019]
  The gaming machine according to claim 3 is the claim 1.Or2. The gaming machine according to 2, whereinDelay circuitDelayed by external elements due to environmenttimeIs determined.
[0020]
  Claim3In the present invention, the delay is caused by an external element acting independently of the control means (CPU, etc.).timeCan be changed so that fraudstersOutsideIt becomes more difficult to grasp the value (timing) of the initial value counter. Where the claim3As the “external element” of the invention, for example, external elements caused by the environment of the pachinko hall such as temperature, pressure, humidity, light, sound pressure, vibration, in addition to hardware external elements such as a clock and a calendar Can be illustrated. For example, delaycircuitWhen the main component is a component that is strongly affected by the temperature of capacitors, resistors, etc., it is delayed by the temperature difference of the pachinko hall (eg seasonal temperature difference, morning and evening temperature difference, etc.)timeTherefore, it becomes more difficult for a fraudster to grasp the value (timing) of the initial value counter. In particular, in a capacitor, a resistor, or the like, a characteristic value can be greatly changed by a slight temperature difference if it is an inexpensive product with low accuracy. In other words, if low-priced products are used, the delay is caused by a slight temperature difference.timeTherefore, a large effect can be obtained with an inexpensive configuration.
[0021]
  Claim4The gaming machine according to claim 1,Any oneIn the gaming machine according to claim 1,OutsideThe initial value counter is updated asynchronously with the update of the random number counter.
[0022]
  Claim4Of the inventionOutsideThe “initial value counter” is updated asynchronously with the update of the random number counter. Therefore, even if initialization processing is performed on the storage means (for example, RAM) and the random number counter is initialized, the initialization processing is independent of this initialization processing.OutsideAn initial value counter is counted. That is, even if the initialization process of the storage means is executed,OutsideIt is possible to determine the initial value of the random number counter based on the value of the initial value counter, and to perform the validity determination control. In other words, it is possible to avoid a situation in which the value of the random number counter (a random number for success or failure is always initialized to 0 when the RAM clear process is executed). Therefore, even if the RAM clear process is executed due to the fraudulent act of the fraudulent person, it becomes difficult to estimate the value of the random number counter (random number of success / failure) from the outside of the control board. You can prevent the act.
[0023]
  Where the claim4Of the inventionOutsideThe “initial value counter” is a clock that generates a clock signal at a predetermined frequency.OscillatorAnd the clockOscillatorAn initial value counter provided with a clock counter unit that counts the number of clock signals generated by. Claims4The “initial value counter” of the present invention may be used not only when the random number counter is initialized but also when the normal random number counter is updated. Since the clock type counter is generally high speed, it becomes more difficult for an unauthorized person to grasp the value of the initial value counter. Further, the “asynchronous initial value counter” of the present invention can be, for example, an “external initial value counter” provided outside the control means (CPU). In addition, a "synchronous initial value counter" that is updated in synchronization with the update of the random number counter is claimed.4The initial value counter (hereinafter referred to as “asynchronous initial value counter”) is provided separately from the initial value counter using the “asynchronous initial value counter” when initializing the random number counter, A “synchronous initial value counter” may be used.
[0024]
  Where the claim4Asynchronous in the invention of (a) Asynchronous typeOutsideThe update cycle of the initial value counter and the update cycle of the random number counter are the same, but there is a deviation in the count timing of both counters, or (b) an asynchronous typeOutsideFor example, the initial value counter update cycle and the random number counter update cycle are different. In particular, in the latter case (b), the asynchronous typeOutsideIf the initial value counter is updated at a high speed, it is difficult for an unauthorized person to grasp the value (timing) of the asynchronous initial value counter, and it is more difficult to perform an unauthorized act. Specifically, the frequency of the clock signal generated by the initial value counter can be set to a desired arbitrary value, for example, about 10 MHz.
  The gaming machine according to claim 5 is the gaming machine according to claim 3 or 4,
The external initial value counter includes a clock oscillation unit that generates a clock signal at a predetermined frequency and a clock counter unit that counts the number of clock signals generated by the clock oscillation unit.
[0025]
  Claim6The gaming machine described is claimed4 or 5In the gaming machine described above,OutsideThe initial value counter has a backup power source.
[0026]
  In the invention of claim 6,OutsideSince an auxiliary power supply is provided in the initial value counter, even when the gaming machine is powered off (hereinafter referred to as powering off),OutsideThe initial value counter can always count. Therefore, even when the machine is turned on, the asynchronous typeOutsideThe initial value counter can count various values (not necessarily 0).
[0027]
  A gaming machine of “the second invention disclosed in this application for reference and excluding the right from the scope of claims (hereinafter referred to as“ reference invention 2 ”)”A main control unit that controls basic progression control of the game, and a variable display device that variably displays a plurality of identification information when a predetermined condition is satisfied, and the game is based on the fact that the stop mode of the variable display device achieves a specific condition A gaming machine that gives a particular value to a person,
  A random number counter that is regularly updated within a certain range;
  A storage unit that stores a storage unit storing a determination program that reads out the value of the random number counter when the predetermined condition is satisfied, and determines whether or not the random number counter is read using the read value of the random number counter.
  Control means for performing the determination of the success / failure by the determination program of the success / failure;
  Storage means for storing data used during execution of the success / failure determination program;
  Delay means for delaying the timing counted by the random number counter,
  In the initialization of the storage means, the validity determination control is performed using the value of the random number counter delayed by the delay means.
[0028]
  Reference invention 2Since the timing counted by the random number counter is delayed by the delay means, it is difficult for an unauthorized person to grasp the value of the random number counter (big hit random number), and it is difficult to perform an unauthorized act. Where (1)Reference invention 2The number of “random number counters” is not particularly limited as long as it is 1 or more. That is, (1)Reference invention 2It is also possible to provide only one “random number counter that is periodically updated within a certain range”, and always use this one random number counter. (2)Reference invention 2Two random number counters that are periodically updated within a certain range are provided, and one random number counter is used to perform the go / no-go determination control at the time of initialization of the storage means. It may be possible to carry out the determination of whether or not it is “other than conversion”. In the latter case (2), both random number counters may be delayed by the delay means, or only one random number counter may be delayed by the delay means.
[0029]
  The gaming machine of the “third invention disclosed in this application for reference and whose rights are excluded from the claims” (hereinafter referred to as “reference invention 3”) is:A main control unit that controls basic progression control of the game, and a variable display device that variably displays a plurality of identification information when a predetermined condition is satisfied, and the game is based on the fact that the stop mode of the variable display device achieves a specific condition A gaming machine that gives a particular value to a person,
  A random number counter that is periodically updated within a certain range, and whose initial value is changed every n times, and
  A storage unit that stores a storage unit storing a determination program that reads out the value of the random number counter when the predetermined condition is satisfied, and determines whether or not the random number counter is read using the read value of the random number counter.
  Control means for performing the determination of the success / failure by the determination program of the success / failure;
  Storage means for storing data used during execution of the success / failure determination program;
  An initial value counter for counting an initial value for updating the random number counter;
  Delay means for delaying the timing counted by the random number counter,
  In the initialization of the storage means, the validity determination control is performed using the value of the random number counter delayed by the delay means. here,Reference invention 3“N” is a natural number.
[0030]
  Reference invention 3However, since the timing counted by the random number counter is delayed by the delay means, it becomes difficult for the fraudster to grasp the value of the random number counter (big hit random number), and it is difficult to cheat. Where (1)Reference invention 3The number of “random number counters” is not particularly limited as long as it is 1 or more. That is, (1)Reference invention 3It is possible to provide only one “random number counter that is periodically updated within a certain range and whose initial value is changed every n times of update”, and this one random number counter may always be used. (2)Reference invention 2Two random number counters that are periodically updated within a certain range and whose initial value is changed every n rounds of update are provided, and the determination of whether or not the storage unit is initialized is performed using one random number counter. Further, the determination of success / failure determination in “other than initialization of storage means” may be performed by another random number counter. still,Reference Invention 2 and Reference Invention 3This delay means can be provided, for example, between the random number counter and the control means. In the latter case (2), both random number counters may be delayed by the delay means, or only one random number counter may be delayed by the delay means.
[0031]
  A gaming machine according to a fourth invention disclosed in the present application by reference and whose rights are excluded from the claims (hereinafter referred to as “reference invention 4”) is referred to as reference invention 2.OrAny of Reference Invention 3In the gaming machine, the delay means has a delay speed determined by an external element depending on the environment.
[0032]
  Reference invention 4However, since the delay speed can be changed by an external element that acts independently of the control means (CPU or the like), it becomes more difficult for an unauthorized person to grasp the value (timing) of the random number counter. here,Reference invention 4Examples of the “external element” include external elements caused by the natural environment such as temperature, pressure, humidity, light, sound pressure, and vibration, in addition to hardware external elements such as a clock and a calendar. For example, when the delay means is mainly composed of components that are strongly affected by the temperature, such as capacitors and resistors, the delay speed depends on the temperature difference of the pachinko hall (eg seasonal temperature difference, morning and evening temperature difference, etc.) Therefore, it becomes more difficult for an unauthorized person to grasp the value (timing) of the random number counter. In particular, in a capacitor, a resistor, or the like, a characteristic value can be greatly changed by a slight temperature difference if it is an inexpensive product with low accuracy. That is, if a low-priced product is used, it is possible to cause a large “variation” in the delay speed due to a slight temperature difference, so that a great effect can be obtained with an inexpensive configuration.
[0033]
The gaming machine of the fifth invention (hereinafter referred to as “reference invention 5”) that is disclosed by reference in the present application and whose rights are excluded from the claims is referred to as reference invention 2 to reference invention 4. Any game ofThe random number counter is an external random number counter provided outside the control means.
[0034]
  Reference invention 5In this case, even if the initialization process is performed on the storage means (for example, RAM), the external random number counter is counted regardless of the initialization process. In other words, even if the initialization process of the storage unit is executed, the determination of validity / invalidity can be performed by the initial value of the external random number counter. In other words, it is possible to avoid a situation in which the value of the random number counter (a random number for success or failure is always initialized to 0 when the RAM clear process is executed). Therefore, even if the RAM clear process is executed due to the fraudulent act of the fraudulent person, it becomes difficult to estimate the value of the random number counter (random number of success / failure) from the outside of the control board. You can prevent the act.
[0035]
  here,Reference invention 5As an “external random number counter”, a clock that generates a clock signal at a predetermined frequencyOscillatorAnd the clockOscillatorThe random number counter provided with the clock counter part which counts the number of clock signals which generate | occur | produces can be illustrated. In addition, in the invention of claim 8, the gaming machine may include an “internal random number counter” provided inside the control means in addition to the “external random number counter”. The frequency of the clock signal generated by the “external random number counter” can be set to a desired arbitrary value, for example, about 10 MHz.
[0036]
The gaming machine of the sixth invention disclosed in the present application by reference and whose rights are excluded from the claims (hereinafter referred to as “reference invention 6”) is the game of reference invention 5.The random number counter has a backup power source.
[0037]
  Reference invention 6In the present invention, since the auxiliary power source is provided in the random number counter, the random number counter can always count even when the power of the gaming machine is shut off (hereinafter referred to as power off). Therefore, even when the gaming machine is turned on, the random number counter can count various values (not necessarily 0).
[0038]
  In addition, claims 1 to6Examples of the “predetermined condition” in each of the inventions include a condition that “the game ball wins a game ball at a specific start opening”. Claims 1 to6As the “specific condition” of each of the inventions, for example, “a plurality of pieces of identification information are variably displayed on the variable display device for a predetermined time, then the identification information is sequentially stopped, and each of the identification information is stopped. Achieving a specific condition, for example, a condition of “bottle eyes (the same pattern is aligned)” can be exemplified. Furthermore, claims 1 to6According to the invention of the present invention, “a determination program for determining whether or not the random number counter is read when the predetermined condition is satisfied, and a hit determination or a jackpot determination is performed when the read random number counter value matches a specific value. Can be exemplified. Claims 1 to6The “data used when executing the success / failure determination program” in each of the inventions includes “value of random number counter” and the like.
[0040]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, examples showing embodiments of the present invention will be described with reference to the drawings.
[0041]
A. Example 1
[0042]
(1) Mechanical structure of pachinko machine 1
  This exampleThe invention of claim 1, claim 3 to claim 6As a specific example of a gaming machine, a first-class pachinko machine (bullet ball gaming machine) of a type called a “seven machine” is illustrated. First, the mechanical structure of the pachinko machine 1 will be described with reference to FIGS.
[0043]
The front portion of the pachinko machine 1 is mainly composed of a main body frame 2, an inner frame 3, a front frame 4, an upper plate portion 5, a lower plate portion 6, and a locking device 7. The main body frame 2 is formed by assembling and fixing a wooden plate-like body into a substantially rectangular frame shape. The middle frame 3 is entirely made of plastic, has a frame body portion (not shown) and a lower plate portion (not shown), and is pivotally supported so as to be openable and closable with respect to the main body frame 2. A locking device 7 is provided at the center of the right end of the middle frame 3, and the locking device 7 has a substantially rectangular shape with a keyhole when viewed from the front, and is used for locking when the front frame 4 is closed.
[0044]
Here, the frame body portion is formed in a substantially rectangular frame shape from the upper end to the lower side to approximately 2/3 of the entire middle frame 3, and the substantially triangular frame decoration LED lens 4 c of the front frame 4 is formed at the upper end portion. 4e, a prize ball display LED (not shown) and a prize ball display LED substrate 4d (see FIG. 4) on the left side, and a stop display LED (not shown) and a stop display LED board 4f (see FIG. 4) on the right side. ) Is arranged.
[0045]
The lower plate portion occupies about 1/3 of the entire middle frame 3 from the lower end to the upper side, and the left end has an effect corresponding to the gaming state so as to correspond to the speaker surface 5a formed on the upper plate portion 5. A speaker 400a (see FIG. 4) for generating sounds and other sounds (sounds) is provided, and is stored in the upper plate part 5 at a substantially central position with respect to a launching device unit (not shown) for launching a game ball. A supply device or the like (not shown) for supplying game balls is provided.
[0046]
Further, below the lower plate portion, a lower tray portion 6 provided with an ashtray, a ball removal lever or the like is provided, and at the approximate center of the lower tray portion 6, a game ball is discharged from the inside of the pachinko machine 1. A discharge port 6a is opened, and a launching handle 9 for operating a launching unit (not shown) is provided at the right end. The launch handle 9 is provided with a touch switch 9a for detecting that the player is touching, and in the vicinity thereof, a launch stop switch 9b for instructing the stop of the launch is disposed.
[0047]
The front frame 4 is entirely made of plastic, and the upper side of the front frame 4 corresponds to the shape of the game area 11 (see FIG. 2) formed on the game board 10 so that the game board 10 (see FIG. 2) can be seen from the front. It has a substantially arc shape, and has an opening 4a that is formed in a substantially bullet shape as a whole. And on the back surface, a substantially rectangular glass frame (not shown) fitted with a glass plate according to the opening 4a is mounted. The front frame 4 occupies about 2/3 the size of the entire front surface of the pachinko machine 1 and is pivotally attached to the left end of the middle frame 3 so as to be opened and closed. Furthermore, a frame decoration lamp lens 4b is also provided at the upper end, and a frame decoration lamp substrate 4g (see FIG. 4) and a plurality of games are arranged inside the lens 4b along the arc portion of the upper end of the opening 4a. An effect lamp (not shown) is provided.
[0048]
The upper plate part 5 is attached to the left end of the middle frame 3 below the front frame 4 and is formed to be openable and closable. On the outer edge 5b of the dish, a ball removal button, a game ball rental / return button, and the like are arranged. In addition, a discharge port 5 c for discharging game balls from the inside of the pachinko machine 1 is opened in the upper plate part 5. A speaker surface 5a having a plurality of long holes is formed at the left end, and a volume switch substrate 12 (see FIG. 4) is provided on the back surface. A prepaid card unit 13 is mounted on the left end side of the pachinko machine 1.
[0049]
Next, the surface structure of the game board 10 of the present embodiment will be described with reference to FIG.
The game board 10 is a substantially rectangular wooden plate-like body, and is held by the middle frame 3 (see FIG. 1), and its back side is covered by a back mechanism board 102 (see FIG. 3) described later. In the game board 10, a substantially circular game area 11 is formed by an outer rail 14 and an inner rail 15 provided on the surface of the game board 10, and in the game area 11, a special symbol display device 16, A kind of starting port (ordinary electric accessory) 17, a variable winning device 18, a left winning port 19, a right winning port 20, a lower left winning port 21, a lower right winning port 22, a number of obstacle nails 23, and a pair Lamp windmills 24 and 25 are disposed.
[0050]
The special symbol display device 16 shows a specific example of a “variable display device”, and is arranged at a substantially central portion of the game area 11 and includes a center accessory 26 and a liquid crystal display board 27. The video screen of the liquid crystal display panel 27 has a substantially rectangular shape. One or a plurality of special symbols (identification information) are displayed on the display screen while changing them one after another in a predetermined direction, and then a special display for stopping display. A symbol display area (identification information display area) is formed. That is, the left special symbol display area for displaying the left special symbol, the middle special symbol display area for displaying the middle special symbol, and the right special symbol display area for displaying the right special symbol are arranged in a substantially horizontal direction. They are formed in this order (not shown). Each special symbol display area has a direction substantially orthogonal to the arrangement direction of these display areas, in this case, a symbol variation direction is set in the vertical direction, and a plurality of symbols (ID information) as identification information so as to vary in that direction ( Special symbols) are displayed sequentially.
[0051]
The liquid crystal display 27 changes the special symbols displayed in the display area (not shown) of the video screen when the game ball enters the first type starting port (ordinary electric accessory) 17. Stop display. Then, for example, when the symbols of the symbols “7, 7, 7” are arranged in the same three-digit pattern and stopped and displayed (determined display), the big prize opening 311 of the big prize winning device 31 described later disposed in the variable prize winning device 18 is displayed. Opened. That is, the game 1 includes a left special symbol display area, a middle special symbol display area, and a right special symbol display area as “plural identification information”. In addition, each special symbol is changed (that is, a plurality of pieces of identification information are variably displayed) by “satisfaction of a predetermined condition” that “a game ball enters the first type starting port (ordinary electric accessory) 17”. The pachinko machine 1 gives a “specific value” called “big hit” when the stop condition of the specific condition “the symbols are arranged in the same three-digit design” is achieved. The center accessory 26 is mounted on the front peripheral portion of the liquid crystal display panel 27 so as to project in a frame shape, and includes a normal symbol display device 32 and a special symbol hold display LED 16a.
[0052]
The normal symbol display device 32 is disposed in the upper center of the center accessory 26, and has a 7-segment indicator 32a and a normal symbol hold display LED 32b. The 7-segment display 32a displays the odd numbers of 1 to 9 in a variable manner. The 7-segment display 32a changes when the game ball passes through one of the left and right normal symbol operation gates 36 and 37, which will be described later. One kind of odd number is stopped and displayed. For example, when the stop display is made with “7”, the first-type start opening (ordinary electric accessory) 17 is opened for a predetermined time (for example, 0.5 seconds).
[0053]
Normal symbol operating gates 36 and 37 are respectively provided obliquely below the left and right of the center accessory 26, and left and right normal symbol operating gate detection switches 36s and 37s (see FIG. 4) is provided. Then, the 7-segment display 32a in the normal symbol display device 32 is variably displayed by passing one of the normal symbol operation gate passage detection switches 36s and 37s of the game ball.
[0054]
The normal symbol hold display LED 32b is composed of four round red LEDs, and is arranged close to both the left and right sides of the 7-segment display 32a. In this case, the number of game balls that have passed through the left and right normal symbol operation gates 36 and 37 is reserved up to four, and the lights are sequentially lit and displayed for each passage. Every time the next variable display on the 7-segment display 32a starts, the number of unstarted times is exhausted, and one normal symbol hold display LED 32b is turned off.
[0055]
The special symbol hold display LED 16a is an upper part of the center accessory 26, and is arranged in parallel on the left and right sides of the normal symbol display device 32 in two, and is composed of four red LEDs. In this case, the number of game balls that have entered the first-type starting port (ordinary electric accessory) 17 is reserved up to four, and the lights are sequentially turned on and shifted for each incoming ball. Each time the next special symbol change starts, the number of unstarted times is exhausted, and one special symbol hold display LED 16a is turned off.
[0056]
The first type starting port (ordinary electric accessory) 17 is integrated with a variable prize device 18 to be described later, and is arranged separately below the center position of the center accessory 26 in the special symbol display device 16. Yes. The first type starting port (ordinary electric accessory) 17 is a so-called tulip type formed so that a pair of wing pieces are opened and closed on the left and right sides, and has a decoration on the front surface and is attached to a substrate 34 to be described later. Inside, there are a first type start port (normal electric accessory) winning detection switch 17s (see FIG. 4) for detecting the passing of the game ball, and a first type start port (normal electric role) for operating the wing piece. A) Solenoid 17c (see FIG. 4). When the pair of wing pieces are opened to the left and right, the game ball is likely to enter the game in an open state, and the pair of wing pieces are erected so that the game ball is less likely to enter. .
[0057]
The variable winning device 18 is disposed below the first-type start opening (ordinary electric accessory) 17 and has a large winning device 31 and a lower left winning device on a substrate 34 whose front side is formed in a substantially inverted trapezoidal shape. A mouth 21 and a lower right winning opening 22 are provided. Here, the grand prize winning device 31 is formed at a substantially central position and is opened in a strip shape. The big prize winning opening 311, the opening / closing plate 312 for opening / closing the special winning prize opening 311, and the opening / closing plate 312 for opening / closing. A grand prize opening solenoid 313 (see FIG. 4), a specific area (V prize opening and general prize opening / not shown) through which a game ball passes after winning the big prize opening 311, an interlocking hook (not shown), and a prize A winning ball detection switch 318 (see FIG. 4) for detecting a ball, a back box (not shown), and a large winning opening relay board (not shown) are mainly configured.
[0058]
The lower left winning opening 21 is disposed on the left side substantially right next to the first-type start opening (ordinary electric accessory) 17, and a lower left winning opening passing detection switch 21s (see FIG. 4) is provided therein. . A plurality of lower left prize port LEDs 223 to 225 are attached to the lower left prize port LED substrate 21f (see FIG. 4) and covered with a decorative lens. Further, the lower right winning opening 22 is disposed on the right side of the first type starting port (ordinary electric accessory) 17 and is provided with a lower right winning opening passing detection switch 22s (see FIG. 4). ing.
[0059]
A left winning port 19 and a right winning port 20 are respectively arranged obliquely above and to the left and right of the variable winning device 18. In each of them, a left winning opening passing detection switch 19s (see FIG. 4) and a right winning opening passing detection switch 20s (see FIG. 4) are provided. In addition, a pair of lamp wind turbines 24 and 25 are disposed obliquely above and to the left and right of the special symbol display device 16, respectively. Further, a pair of side lamps 38 and 39 are arranged in a vertical circular arc shape and symmetrical with respect to both left and right ends of the game area 11. A number of obstacle nails 23 are arranged in the game area 11 so as to be suitable for a pachinko game in consideration of the positional balance with each gaming device described above.
[0060]
Next, an out port 48 is provided below the game board 10, and a back ball prevention member 58 is provided below the out port 48, so that the game ball that has returned without reaching the game area 11 is again. Prevents returning to the launch position. On the other hand, the foul ball prevention member 59 is attached to the front end portion of the inner rail 15, and the return rubber 60 is located on the right half side of the game board 10 on the substantially opposite side to the position of the foul ball prevention member 59. Attached along the outer rail 14 in a fitting manner.
[0061]
Next, the back surface structure of the pachinko machine 1 of the present embodiment will be described with reference to FIG. The front frame 4 (see FIG. 1) is in the middle frame 3 and is supported by a pair of hinges 101 provided at the upper and lower ends of the front frame 4 so as to be opened and closed. The back mechanism board 102 is supported by the pair of hinges 103 provided in the middle frame 3 at the upper and lower ends of the back mechanism board 102 so as to be opened and closed. The game board 10 (see FIG. 2) is detachably attached to the surface side of the middle frame 3. A prize ball tank 105 provided with a tank ball cut detection switch 104 at the bottom of the tank and a tank rail 106 connected to the prize ball tank 105 are attached to the left side as viewed from the position of the hinge 101 on the upper end side. ing. In addition, a ball removal lever 107 is provided on the right side of the tank rail 106, a supply ball runout detection switch (not shown) is provided on the downstream side, and an award as a backside gaming device is provided on the downstream side. A ball payout device 109 is provided.
[0062]
Subsequently, a game ball distribution unit (not shown) is provided on the downstream side of the prize ball payout device 109. Under the tank rail 106, a back case 111 with a lid for storing the liquid crystal display panel 27 (see FIG. 2) in the special symbol display device 16 is provided. As the control unit 140 (see FIG. 4), a main control board case 112 as a storage container storing a main control board 340 (see FIG. 5A) as a backside gaming device is disposed. On the lower back side of the main control board case 112, a launcher control board case 113 storing the launcher control board and a launch control assembly relay board (not shown) are provided as the launch control unit 201a (see FIG. 4). Yes. The above-mentioned launching device unit (not shown) is provided in the lower left portion of the back mechanism panel 102, and the first peripheral control board is also provided in the lower right portion as a frame control unit (dispensing control unit) 150 (see FIG. 4). (Discharge control substrate) 350 {Refer to FIG. 5B} A frame control substrate case (dispensing control substrate case) 118 is provided as a storage container storing the same. A relay board 200 as a backside gaming device is mounted on the upper right side of the main control board case 112.
[0063]
As shown in FIG. 4, the relay board 200 is a board for relaying the winning ball detection switches 318 and 19 s to 22 s and the main control unit 140. In this embodiment, the main control board case 112, the relay board 200, and the frame control board case (dispensing control board case) 118 are detachably attached to a metal plate (not shown), and this metal plate is a back mechanism board. It is suspended so as to be rotatable with respect to 102.
[0064]
On the other hand, at the upper right end portion of the back mechanism panel 102, a fuse box 119, a power switch 120, a power terminal board 121 and a jackpot, launcher control, ball break, door opening, prize ball, ball lending, etc. A terminal substrate 122 provided with external connection terminals is provided. A power cable 123 for receiving power from the outside is also provided on the upper side of the terminal board 122. A connection cable 124 extends upward from the frame control board case 118 storing the first peripheral control board 350 {see FIG. 5B}, and is connected to the prepaid card unit 13 including the power cable 125. Further, a ball passage member 126 for a lower plate portion is provided at the lower end of the center of the back mechanism panel 102.
[0065]
(2) Electronic control device 130 of the pachinko machine 1
Next, the electronic control device 130 of the pachinko machine 1 according to the present embodiment will be described with reference to FIGS. First, the electronic control unit 130 includes a main control unit 140 and a frame control unit connected to the main control unit 140 through a signal transmission path 500a {payout control unit (a prize ball payout control unit that mainly performs prize ball payout control). )} 150, a special symbol control unit 160, a lamp control unit 170, and a sound control unit 180. The main control unit 140 includes a main control board 340, and the four control units 150, 160, 170, and 180 other than the main control unit 140 are a frame control board 350 and a special control board as first to fourth peripheral control boards, respectively. A symbol control board 360, a lamp control board 370, and a voice control board 380 are provided.
[0066]
As shown in FIG. 5A, the main control board 340 includes a main circuit unit 400 including a CPU 401 (see FIGS. 13 and 14) and an input / output circuit unit 500. The main circuit unit 400 is connected to a RAM clear switch 144 for generating a “RAM clear signal” in the RAM 481, and a RAM clear signal is generated in the main control board 340. The main control board 340 is usually housed in a case that is difficult for an unauthorized person to open and close (that is, the main control board case 112), and the RAM clear switch 144 and its surrounding wiring are also housed in this case. Yes. Therefore, it is difficult for this fraudster to gain unauthorized access to the RAM clear switch 144 and its surroundings (attaching a hanging board).
[0067]
In addition, an external terminal unit 145 is connected to the input / output circuit unit 500, and a “hole computer” of a pachinko hall is connected to the external terminal unit 145. Then, the main control board 340 turns on the RAM clear signal after executing the RAM clear process and turns it off after a predetermined time has elapsed. The main control board 340 outputs the RAM clear signal to the outside of the pachinko machine 1 and sends it to the pachinko hall system or the like. Can be notified. For this reason, the manager of the pachinko hall can know the cheating while the cheating is not known.
[0068]
As shown in FIG. 14, the CPU 401 includes a CPU core 480 and controls operation of the entire pachinko machine 1 (that is, basic progress control of a game) using the RAM 481 as a work area by a control program stored in the ROM 482. In addition, the CPU 401 is the main player to perform the go / no-go judgment control by the go / no-go judgment program stored in the ROM 482 (win / fail judgment means). The CPU 401 (CPU core 480) functions as the “control unit” of the present invention, the ROM 482 functions as the “storage unit” of the present invention, and the RAM 481 functions as the “storage unit” of the present invention. . The RAM 481 is volatile. Further, the CPU 401 (CPU core 480) functions as a “changing unit” that changes the initial value of the random number counter 481v about every n times (in this example, once).
[0069]
As shown in FIG. 13, the main circuit unit 400 includes a CPU 401, an oscillation unit 410, a reset circuit unit 450, an I / O decode circuit unit 420, a data bus stabilization unit 411, and a first external input circuit unit 430. ing. As shown in FIG. 14, the CPU 401 includes a CPU core 480, a built-in RAM 481, a built-in ROM 482, a memory control circuit 483, a clock generator 484, an address decoder 485, a watchdog timer 486, a counter / timer 487, a parallel input / output port. 488, a reset / interrupt controller 489, an external bus interface 490, and an output control circuit 491.
[0070]
  Further, as shown in FIGS. 13 and 14, an external initial value counter 460 is connected to the CPU 401 via an output port 930. The external initial value counter 460 is defined in claims 1 to 4.6Shown in each inventionOutsideA specific example of “initial value counter” is shown. Further, a delay circuit 800 is provided between the external initial value counter 460 and the CPU 401, and the delay circuit 800 is defined in claims 1 to 4.6"Delay" shown in each inventioncircuitA specific example is shown. Details of the external initial value counter 460 and the delay circuit 800 will be described later.
[0071]
Returning to FIG. 4, the signal transmission path 500 a described above is connected to the input / output circuit section 500 shown in FIG. 5A, and each control section 150, 160, 170 is connected from the input / output circuit section 500 to the signal transmission path 500 a. , 180, command data as a command signal for instructing processing contents is transmitted. Note that data is transmitted from the main control unit 140 to the control units 150, 160, 170, and 180 in one-way format or bidirectional format. In addition, each control unit 140 to 180 is supplied with power from the power receiving board 410 via the power supply unit 420 and further through the power distribution board 430, and a system reset signal at the time of power-up described later is sent to all control boards. Sent to.
[0072]
Winning ball detection switches 318, 19s to 22s and the like are connected to the relay board 200, and the output terminal of the relay board 200 is connected to the input / output circuit unit 500 of the main control unit 140. Also, the first type start opening (ordinary electric accessory) winning detection switch 17s, normal symbol display device board 32f, various solenoids 17c and 313, right normal symbol operation gate passage detection switch 37s, left normal symbol operation gate passage detection switch 36s. Are connected to the input / output circuit unit 500 of the main control unit 140.
[0073]
A touch switch 9a, a firing stop switch 9b, a volume switch 202, a tank ball breakage detection switch 104, a supply ball breakage detection switch 108, and the like are connected to the frame terminal board 200a. An output terminal of the frame terminal board 200a is shown in FIG. It is connected to the input / output circuit unit 700 of the frame control unit 150 shown in FIG.
[0074]
As shown in FIG. 5B, the frame control unit (payout control unit) 150 includes a main circuit unit 600 and an input / output circuit unit 700 similar to the main control unit 140. It is connected to the signal transmission path 500a shown in FIG. The input / output circuit unit 700 is connected to a prize ball payout device 109, a launcher control board 201, and the like.
[0075]
As shown in FIG. 6A, the special symbol control unit 160 includes a CPU 161, a RAM 162, a ROM 163, an input / output port 164, and a VDP (video display processor) 166 as arithmetic circuit components. Arithmetic circuit components are connected to each other via a bus 165 and are connected to a signal transmission path 500a at an input / output port 164. A liquid crystal display board 27 is connected to the input / output port 164. The CPU 161 controls the operation of the special symbol display device 16 (liquid crystal display board 27) using the RAM 162 as a work area (that is, the display device) according to a control program stored in the ROM 163. Display control).
[0076]
As shown in FIG. 6B, the lamp control unit 170 includes arithmetic circuit components 171 to 175 similar to the special symbol control unit 160 and is connected to the signal transmission path 500 a at the input / output port 174. Yes. The frame decoration lamp board 4g, various lamp boards 261f and 262f, various LED boards 4d, 4f, 21f, and 22f shown in FIG. 4 are connected to the input / output port 174. One or more lamps or LEDs are connected to each of these substrates. These lamps, etc. are turned on / off or blinking according to the progress of the game. The lamp control unit 170 controls driving of a solenoid, a motor, etc. (not shown).
[0077]
As shown in FIG. 6C, the voice control unit 180 includes arithmetic circuit components 181 to 185 similar to the special symbol control unit 160 and the sound generator 203, and a signal transmission path at the input / output port 184. 500a. The sound generator 203 outputs various sounds corresponding to the progress of the game from the speaker 400a connected via the volume switch board 12 shown in FIG. 4 based on the stored sound data and sound output module. The volume switch board 12 connected to the input / output port 184 sets the output volume in accordance with the operation of the volume switch (not shown).
[0078]
Further, various lamps such as the frame decoration lamp board 4g and the sound generator 203 are provided with a special symbol change / stop display mode, presence / absence of reach generation, reach display mode (described later), special game mode under the control of the special symbol control unit 160. The mode is controlled according to the game mode (probability fluctuation, time reduction, etc.) and the like. The command signal of the control command is transmitted through the signal transmission path 500a as a command signal that targets the lamp control unit 170 or the voice control unit 180 as an operation command target.
[0079]
Note that the special symbol control unit 160, the lamp control unit 170, and the sound control unit 180 described above may be configured by the same circuit units as the main control unit 140 and the frame control unit 150. In other words, it is possible to use a CPU having a main circuit portion and an input / output circuit portion and having a ROM and a RAM built therein.
[0080]
Next, the winning ball operation is executed in the following order.
When the game ball passes the winning ball detection switch 318, the main control unit 140 receives 15 winning ball number data, and when the game ball passes the first type start port (ordinary electric accessory) winning detection switch 17s, the six winning ball numbers. In other cases, for example, when passing of the passage detection switches 21 s and 22 s of the left and right lower winning openings 21 and 22 is detected, ten prize ball number data are sent to the frame control unit 150. In order of detection, the frame control unit 150 is transmitted as a command signal for the operation command, via the signal transmission path 500a. (In other words, the number of unique prize balls is 6, 10, or 15 here.) The frame control unit 150 receives the prize ball number data from the main control unit 140 and receives a prize ball payout signal to transmit a prize. The ball dispensing device 109 is activated.
[0081]
Further, the main control unit 140 determines a gaming state based on the outputs of the various detection switches described above, makes a determination of success / failure based on the gaming state, and displays an image in a corresponding symbol display mode according to the determination content. Read data for display control. For example, the main control unit 140 uses the detection result of the first type start opening (ordinary electric accessory) winning detection switch 17s, the winning ball detection switch 318, etc., the acquired value of the special symbol success / failure determination random number, and the like. It is also determined whether there is a waiting state for a customer who has not been played, a state in which a game is being played but no start-up winnings (variable preparation state), a state in which there has been a starting win, and a special game state. In addition, when a start winning is detected, a determination of success or failure is made based on a random number value described later. Based on the determination result, fluctuations in special symbols (including reach display modes) or display mode control such as confirmation are performed. Data is read. This data is transmitted through the signal transmission path 500a as a command signal for which the special symbol control unit 160 is an operation command target.
[0082]
Next, a main job executed by the main control unit 140 will be described with reference to FIG. This is an example of a job executed by the CPU 401 based on a program stored in the ROM 482 of the main control unit 140 shown in FIG. First, after setting the stack pointer to a predetermined address in the RAM 481 (S10), it is determined whether or not the RAM clear switch 144 is operated (pressed) (S12). If it is operated, initialization processing of the RAM 481 is performed. If it is performed (S800) and it is not operated, it is determined whether a backup flag is set (S15). If the backup flag is set (S15: YES), the “recovery process for power interruption” of FIG. 9 is performed.
[0083]
In this embodiment, when a power failure occurs due to a power failure or the like, as shown in FIG. 8, the used register is saved in the RAM 481 (S630), and the value of the stack pointer is saved in the RAM 481 (S632). Then, the large winning opening solenoid and the first type starting opening solenoid are turned off (S634), the polling processing time of the winning ball sensor (for example, about 85 milliseconds) is set (S636), the sensor before counting the winning ball and the winning ball count. The passage of the game ball is monitored by the rear sensor (S638). Next, when the polling processing time elapses (S640), a checksum (excluding checksum, backup flag, and stack area) of the RAM 481 used is created (S642), stored, and the backup flag is set in the RAM 481 ( S646). Then, access to the RAM 481 is prohibited (S648), and an infinite loop process prepares for power down. It is also possible to execute HALT processing or STOP processing instead of the infinite loop processing.
[0084]
In the “return processing” of FIG. 9, checksum calculation (S664) is executed, the checksum values stored when the power is turned off are compared, and if they do not match, initialization processing of the RAM 481 is performed (S800). ). If they match, the stack pointer before power-off is restored (S668), the backup flag is cleared (S670), and a command for returning the sub-board to the state before power-off is transmitted (S672). Then, each register is returned to the state before the power is turned off (S674), the permission / non-permission of interruption is returned to the state before the power is turned off (S676, S678), and the address is returned to the address before the power is turned off (S680). In this embodiment, since a backup power supply for power failure countermeasures is added to the pachinko machine 1, “information advantageous to the player” that was generated before the power failure is saved even during a power failure in the pachinko hall. it can.
[0085]
Returning to FIG. 7, if the backup flag is not set (S15: NO), a determination of completion of initialization is made (S20). If the initialization is completed (S20: YES), the job from the LED job (S30) to the switch job (S70) is executed. If the initialization is not completed (S20: NO), the initialization job (S190) is executed, and the initialization completion is determined again (S20). If the pachinko machine 1 is initially turned on from the shipping state, the RAM clear switch 144 is operated (pressed), the backup flag is abnormal, or the checksums do not match, Initialization processing of the RAM 481 is performed.
[0086]
In the LED job (S30), the display pattern data of the normal symbol and the normal symbol unstarted count, the display pattern data of the special symbol unstarted count, and the like are output. In the constant speed random number job (S40), a special symbol success / failure random number memory, a general-purpose count memory, and the like of the RAM 481 described later are updated. In the non-constant speed random number job (S50), the off-normal symbol random number memory (not shown) is updated. Note that the general-purpose count memory (not shown) is used, for example, for creating a value of “0” to “255” for each interrupt, executing a command job, and a decoration job. Details regarding the special symbol success / failure determination random number and the update of the initial value random number will be described later.
[0087]
In the voice job (S60), data related to music and voice is read, and in the switch job (S70), various detection switches are read. That is, various signals such as a left and right winning opening passing detection signal are transmitted to the main control unit 140 via the relay substrate 200, and various signals such as a firing stop detection signal, a touch detection signal, and a volume detection signal are transmitted via the frame terminal substrate 200a. Each of them is taken into the frame control unit 150, and also the first type starting port (ordinary electric accessory) winning detection switch 17s, the first type starting port winning detection signal, the winning ball detection signal from the big winning device 31, and the normal symbol operation. A gate passage detection signal is taken into the main control unit 140.
[0088]
Further, it is determined whether or not there is an abnormality in the switch 318 (see FIG. 4) such as the count detection switch, the count detection and the specific area passage detection switch (S80), and if there is no abnormality (S80: YES), the special symbol main Jobs from job (S90) to voice job (S110) are executed. If there is an abnormality (ball clogging, disconnection, etc.) (S80: NO), an error job (S130) is executed.
[0089]
In the special symbol main job (S90), a job related to data necessary for the main controller 140 and the special symbol controller 160 to operate in cooperation is executed. Further, in the normal symbol main job (S100), the display pattern data of the normal symbol and the normal symbol unstarted count is read.
[0090]
Thereafter, each flag state is set in the backup memory (S140), and a prize ball signal job (S150), an information signal job (S160), a command job (S170), and a remaining time job (S180) are executed. In the prize ball signal job (S150), data relating to prize ball payout is read and output, and in the information signal job (S160), data necessary for outputting information to other control units is read. Further, in the command job (S170), a command for special symbol management or the like is output, and in the remaining time job (S180), a non-constant random number is called.
[0091]
Next, the success / failure determination job at the time of start winning (winning the first type start opening (ordinary electric accessory) 17) executed in the series of the main job will be described with reference to FIG. . Various memories used in these jobs are stored in the RAM 481 (see FIG. 14) of the main control unit 140 shown in FIG. 4, and typical ones (481a to 481n, 481v) are shown in FIG. In this embodiment, the external initial value counter 460 is arranged outside the control means (CPU 401) as described above. The external initial value counter 460 is updated asynchronously with the update of the random number counter 481v. Details of the external initial value counter 460 and the random number counter 481v will be described later.
[0092]
First, in S200, it is confirmed whether or not there has been a start prize. If YES, the number of reservations (unstarted number) stored in the special symbol reservation number memory 481b (see FIG. 11) is incremented by one in S210. If the number of reserves (the number of unstarted times) exceeds a certain value (“4” in the present embodiment), the start winning is invalid and skips to S250. If the number of holdings is within a certain value (the number of unstarted times), in S230, a special symbol success / failure determination random number (hereinafter also referred to as a success / failure random number or determination random number) is generated (even if a program is generated, The random number generation circuit may be used (random number generation means for success / failure)}, and the read determination random number value is converted into a special symbol validity determination random number memory 481a in S240 (see FIG. 11: hereinafter also referred to as determination random number memory). This memory stores the read determination random number value in the time series of the start winning prize in the shift memory format.
[0093]
Next, in S250, the oldest first determination random number value stored in the determination random number memory 481a (see FIG. 11) is read. Then, in S260, the big hit number memory 481h (see FIG. 11) is read out, and in S270, it is compared with the determination random number value. If they do not match, it will be judged as coming off. In the case of jackpot determination, the process proceeds to S280, where a jackpot symbol determination random number (identification information determination random number) is generated, read and stored in the jackpot symbol determination random number memory 481d (see FIG. 11) (see FIG. 11). S290). The big hit symbol determination random number is read at the same time as the winning random number at the time of starting winning, but it may be read simultaneously with the hit determination or after a predetermined time after the hit determination. In S300, the determination result of “big hit” (“1” in this embodiment) is stored in the determination result memory 481j (see FIG. 11). A reach mode determining random number is generated simultaneously with the jackpot symbol determining random number, and the determined random number value is read and stored in the reach mode determining random number memory 481k (see FIG. 11) (S295).
[0094]
The special symbol designated by the jackpot symbol determination random number is based on the special symbol image data stored in the ROM 163 of the special symbol control unit 160 {see FIG. 6A} (see FIG. 2). ), After passing through the variable display state, it is displayed in a predetermined arrangement mode (for example, “7, 7, 7”, the arrangement mode of the same three-digit symbols). The special symbol image data is stored in the RAM 481 (see FIG. 14) of the main control unit 140 as an identification information determination value in association with the jackpot symbol determination random number value, and the read jackpot symbol determination random number value and identification information are stored. It is good also as what determines the symbol stopped and displayed by comparing with the value for determination.
[0095]
Further, the reach display mode designated by the reach mode determination random number value is based on the reach display mode image data stored in the ROM 163 {see FIG. 6A} of the special symbol control unit 160. 2), after the variable display state, it is displayed in a predetermined reach mode. Also in this case, the reach display mode image data is associated with the reach mode determination random number value as a reach mode determination value, and is used as a reach mode determination value in the RAM 481 (see FIG. 14) of the main control unit 140 (see FIG. 14). 11), and the reach mode to be displayed may be determined by comparing the read reach mode determination random value and the reach mode determination value.
[0096]
On the other hand, if it is determined that the detachment has occurred, the process proceeds from S270 to S310, and whether or not to perform a detach reach job is determined by a random number. That is, in S310, a reach mode determining random number is generated and read, and in S320, the reach number stored in the reach number memory 481i (see FIG. 11) is read. In S330, if both match, it is a missed reach job, and if they do not match, it is a normally missed job.
[0097]
In the case of a missed reach job, the process proceeds to S340, and at least two special symbols to be aligned (for example, the left symbol and the right symbol among the three types of special symbols) are selected as the missed reach symbol determination random number (also the random number of the left symbol). The right symbol may be matched with the reference (S340), and stored in the outreach symbol number memory 481m (see FIG. 11) (S350). Further, in S360, the out-of-run symbol is similarly determined by a random number, and the random number value determined in S370 is stored in the out-of-run symbol number memory 481g (see FIG. 11). Further, in S380, the determination result of “outgoing reach” (“2” in this embodiment) is stored in the determination result memory 481j (see FIG. 11). On the other hand, in the case of a normal off-job, the process proceeds to S390, where each special symbol (for example, the left symbol, the right symbol, and the middle symbol) is determined by a random number, and each determined random number value is associated with a corresponding out symbol number memory 481e, 481f and 481g are stored (S390 to S440). In S450, the determination result “normally out” (“3” in this embodiment) is stored in the determination result memory 481j (see FIG. 11).
[0098]
Next, a schematic flow of the special symbol main job executed in the series of the main job will be described with reference to FIG. First, in S500, based on the winning of the game ball to the first type start opening (ordinary electric accessory) 17, the special symbols are displayed on the liquid crystal display board 27 (see FIG. 2) on the special symbol display device 16 in a variable manner. Let it begin. For example, the left and right and middle symbols are scrolled from top to bottom and from bottom to top.
[0099]
Next, in S510, the determination result for each winning obtained in the success / failure determination job shown in FIG. 10 is read from the determination result memory 481j (see FIG. 11). Specifically, in the case of jackpot determination (“1”) (S520: YES), the process proceeds to S580, and the reach mode determination stored in the reach mode determination value memory 481l corresponding to the reach mode determination random value described above. The business value is read, and the process further proceeds to S600, the jackpot number (identification information determination value) is read from the jackpot number memory (determination value storage means) 481h (see FIG. 11), and the process proceeds to S610, for example, the left symbol and the right symbol Are arranged in the same design and after a predetermined reach display mode, the middle design is stopped and displayed in the same design as the left design and the right design to be confirmed.
[0100]
On the other hand, in the case of the detachment reach determination (“2”) (S530: YES), the process proceeds to S570, where the detachment symbol number memory 481m (see FIG. 11) and the detaching symbol number memory 481g (see FIG. 11). The symbol number in the middle is read out (see FIG. 11). Then, in S571, the read out-reach symbol number and the out-of-out symbol number are compared, and the outreach mode is determined based on the difference between them (S572). Specifically, in S571, the difference between these numbers (that is, the difference between the left symbol and the middle symbol, for example) is calculated, and outlier reach manner data is read from the outlier reach manner memory 481n based on the difference. For example, when the difference is “−1” (that is, when the middle symbol is the symbol immediately before the left symbol, for example), one type is selected from a plurality of types (for example, three types) of outlier superreach ( For example, it can be selected by obtaining a predetermined random number). Then, for example, after the left symbol and the right symbol are aligned to the same symbol and after a predetermined reach display mode, the middle symbol is stopped and displayed in a symbol different from the other symbols and determined.
[0101]
Further, in the case of the normal detachment determination (“3”) (S540), the process proceeds to S550, and the detachment symbol numbers are read from the detachment number memories 481e, 481f, 481g (see FIG. 11), respectively, and the process proceeds to S560. The symbols (for example, the left symbol, the right symbol, and the middle symbol) are stopped and displayed at a timing shifted from each other. In the case of the normal deviation determination, the display mode can be changed to various modes by “slip display” or the like. In this case, the display mode image data is associated with the reach mode determination random number value and the normal mode is determined. The display mode determination value is stored in a normal out display mode determination value memory (not shown) in the RAM 481 (see FIG. 14) of the main control unit 140, and the read reach mode determination random number value and the normal out display mode determination are determined. It is good also as what determines the normal deviation mode displayed by comparing with a use value.
[0102]
Next, the special symbol is determined and displayed in a predetermined arrangement manner on the liquid crystal display panel 27 (see FIG. 2) by the big hit determination (for example, the arrangement manner of the same three-digit symbols “7, 7, 7”), and thereafter A special game is executed (special game state or jackpot game state). In the special game state, first, the open / close plate 312 of the big winning device 31 (see FIG. 2) is in the open state, and the winning of the game ball to the big winning port 311 is in a gaming ball receiving state that is superior to the player.
[0103]
In this special game state, the big winning device 31 is kept in the game ball receiving state until the end condition is satisfied. For example, the open state is a predetermined time t₁When (for example, 30 seconds) elapses, or a predetermined number n is entered in the winning ball detection switch 318 (see FIG. 4)₁When (for example, 10) winnings are detected, the end condition is established, the game ball receiving state is once ended, the opening / closing plate 312 is closed, and one round is ended. The opening / closing plate 312 is closed for a predetermined time t.₂After a lapse of (for example, 0.5 seconds), if a predetermined continuation condition (passage to a specific area not shown) is satisfied, the opening / closing plate 312 is opened again and the grand prize winning device 31 is set to the game ball receiving state. Become. Note that the game ball receiving state in which one round is the end condition is repeated up to a predetermined maximum number of continuous rounds (16 rounds in this embodiment). Further, if the continuation condition is not satisfied when the end condition is satisfied, the special gaming state ends (so-called puncture) in that round.
[0104]
In the pachinko machine 1, based on the type of the special symbol stopped and displayed on the liquid crystal display panel 27 (see FIG. 2) of the special symbol display device 16 by the hit determination, after the special gaming state ends, until the next big hit Probability changing means is provided for changing (improving) the probability of winning / failing determination (big hit probability). More specifically, the jackpot symbol determination random number value stored in advance is composed of a random number value for probability change and a random number value for non-probability change, and a probability change symbol or non-probability according to acquisition of each random value. The change symbol is stopped and displayed. In the case where the symbol that is stopped and displayed is a symbol for probability change, the probability of success / failure determination (big hit probability) is improved to about 4 to 5 times the normal value until the next big hit after the special gaming state.
[0105]
(3) Details of the main control unit 40
Hereinafter, details of the main control unit 140 will be described. As shown in FIG. 5A, the main control unit 140 includes a main control board 340. The main control board 340 includes a main circuit unit 400 including the CPU 401 and an input / output as shown in FIG. A circuit unit 500 is formed. Hereinafter, the main circuit unit 400 and the input / output circuit unit 500 will be described in order.
[0106]
First, as shown in FIG. 13, the main circuit unit 400 includes a CPU 401, an oscillation unit 410, a reset circuit unit 450, an I / O decode circuit unit 420, a data bus stabilization unit 411, and a first external input circuit unit 430. Have. As described above, the external initial value counter 460 is connected to the CPU 401 via the output port 930, and the delay circuit 800 is provided between the external initial value counter 460 and the CPU 401. Hereinafter, components of the main circuit unit 400 will be described.
[0107]
As shown in FIG. 14, the CPU 401 has a CPU core 480, built-in RAM 481, built-in ROM 482, memory control circuit 483, clock generator 484, address decoder 485, watchdog timer 486, counter / timer 487, parallel input / output port 488, reset. / Interrupt controller 489, external bus interface 490, and output control circuit 491. The oscillation unit 410 includes a crystal oscillation module 404 as shown in FIG.
[0108]
As shown in FIG. 15, the reset circuit unit 450 includes an initialization reset signal generation unit 412 (power-on initialization signal generation unit) and an interrupt signal generation unit 413 (steady control initialization signal generation unit). is doing. The initialization reset signal generation unit 412 includes a general-purpose initialization reset signal generation unit 418 (general-purpose initialization signal generation unit) and a CPU initialization reset signal generation unit 414 (CPU initialization signal generation unit). ing. The general-purpose initialization reset signal generation unit 418 of the initialization reset signal generation unit 412 includes a power input connector 445, a reset input protection resistor 451, a Schmitt trigger inverter IC 452, 454, a filter circuit 453, a NAND gate 455, a NORIC 458, and a counter IC 456. 457 is included. The CPU initialization reset signal generation unit 414 includes a flip-flop IC467, a Schmitt trigger inverter IC459, a counter IC460, and a NOR gate IC461. Further, the interrupt signal generation unit 413 includes a flip-flop circuit unit 462, a counter IC 463, a Schmitt trigger inverter ICs 464 and 466, and a counter IC 465.
[0109]
As shown in FIG. 16, the I / O decode circuit unit 420 includes a device selection signal generation unit 415 and a gate signal generation unit 416. The device selection signal generation unit 415 includes a NOR gate IC 422, decoder ICs 423 and 424, and resistance arrays 421 and 428. The gate signal generation unit 416 includes a NOR gate IC 425, a NAND gate IC 426, a flip-flop IC 427, a resistor array 429, and a Schmitt trigger inverter IC 405. The data bus stabilization unit 411 includes a resistance array 403 and a buffer IC 402.
[0110]
As shown in FIG. 17, the first external input circuit unit 430 includes an input connector unit 440, a switch driver 432, a signal matching unit 433, a standardized signal stabilization unit 434, and a resistance array 431. The input connector section 440 includes a frame connector 441 and a first special symbol start switch connector 442, a second special symbol start switch connector 443, and a normal symbol start switch connector 444 which are game board connectors. The standardized signal stabilization unit 434 includes a plurality of resistors, and the signal matching unit 433 includes a plurality of resistors and a capacitor.
[0111]
Next, functions of the CPU 401, the oscillation unit 410, the circuit units 411, 420, 430, and 450 of the main circuit unit 400 will be described.
Each terminal of the CPU 401 shown in FIGS. 15 to 17 is classified as follows.
(1) Address part
A0 to A15: 16-bit address bus output terminals.
(2) Data section
D0 to D7: 8-bit bidirectional data bus terminals.
(3) System control unit
XMI: An output terminal for a signal indicating machine cycle 1.
XMREQ: An output terminal for request signals to the memory space.
XIORQ: An output terminal for an input / output request signal to / from the I / O space.
XWR: A signal output terminal indicating that the data bus is in a write cycle.
XRD: An output terminal for a signal indicating that the data bus is in a read cycle.
XRFSH: Refresh signal output terminal.
(4) CPU controller
XHALT: Halt signal output terminal.
XINT: Maskable interrupt request signal input terminal.
XNMI: Non-maskable interrupt request signal input terminal.
XSRST: System reset signal input terminal.
XSRSTO: System reset signal output terminal.
XURST: Interrupt signal input terminal.
IEO / SCLKO: Unused output terminal for daisy chain signal and divided clock.
PRG: An input terminal for setting the CPU in the PROM mode.
MODE: An output terminal indicating the state of the operation mode of the CPU.
(5) I / O section
CLK / TRG2 / .CLK / TRG3: External clock / timer trigger signal input terminal.
ZC / TO0 / ZC / TO1: Built-in CTC signal output terminal.
PA0 to PA7: 8-bit parallel I / O terminals.
PBO / XCSIO0 to PB3 / XCSIO3: 4-bit parallel I / O port, external device chip select shared terminal.
(6) Clock part
EXTAL1, EXTAL2: Crystal resonator connection terminals.
CLKO: System clock signal output terminal. A square wave having a duty of 50% obtained by dividing the input signal frequency of the EXTAL1 / EXTAL2 terminal by 1/2 is output.
▲ 7 ▼ Power supply
VDD1 / 2: Power supply (+ 5V) terminal.
VSS1 and 2: Power supply (GND) terminals.
VBB: Backup terminal for the internal RAM 281.
▲ 8 ▼ Other
NC: Non-connection terminal.
[0112]
The CPU 401 uses the internal RAM 481 as a work area based on the program written in the internal ROM 482 shown in FIG. Further, the CPU 401 has a RAM backup function for holding the contents of the built-in RAM 481 by a voltage holding unit connected to the VBB terminal when the power is turned off, and a fraud prevention function such as a program authentication function and a program execution prohibition function outside the designated area. ing. The program authentication function is to check whether the authentication code calculated based on the program is correct when an initialization signal for initializing the CPU 401 is input when the power is turned on. This is a function that stops program execution. The out-of-designated-area program execution prohibition function is a function for prohibiting execution of a program outside a predetermined address range. Note that the “information advantageous to the player” at the time of power-off described above is stored by the RAM backup function.
[0113]
In the CPU 401, an interrupt reset is performed at a constant cycle to prevent runaway. The cause of the runaway is excessive noise intrusion. In the CPU 401 of this embodiment, I / O mapped I / O decoding is performed, the XIORQ terminal is used, and the XMREQ terminal is not used. However, it is also possible to employ the memory mapped I / O method for decoding and use the XMREQ terminal.
[0114]
The crystal oscillation module 404 of the oscillation unit 410 shown in FIG. 15 outputs an operation clock signal for the CPU 401. This operation clock signal is input to the EXTAL1 terminal of the CPU 401. A crystal oscillator is used in place of the crystal oscillation module 404, and this crystal oscillator is connected between the EXTAL 1 and 2 terminals, and an oscillation clock can be generated by the clock generator 484 of the CPU 401 (see FIG. 14). . However, in this embodiment, since the crystal oscillation module 404 is used and connected to the EXTAL1 terminal of the CPU 401, it is not necessary to match the crystal oscillator and the clock generation circuit.
[0115]
In the reset circuit unit 450 shown in FIG. 15, a general-purpose initialization reset signal generation unit 418 generates a general-purpose initialization reset signal, and an interrupt signal generation unit 413 generates an interrupt signal.
[0116]
The general-purpose initialization reset signal generation unit 418 generates a general-purpose initialization reset signal based on a system reset signal (hereinafter also referred to as a power-on reset signal) input from the outside via the power input connector 445. The data is output to the signal generation unit 414 and the input / output circuit unit 500 (see FIG. 13).
[0117]
The CPU initialization reset signal generation unit 414 outputs a CPU initialization reset signal to the XSRST terminal of the CPU 401 based on a system reset signal input from the outside via the external input connector 445. The CPU initialization reset signal is a pulse signal that maintains the H level for a certain period of time when the power supply of the CPU 401 is stabilized, and then once changes to the L level and then further changes to the H level. By generating this CPU initialization reset signal, the CPU 401 reliably performs initialization when the power is turned on without being affected by the power signal.
[0118]
The interrupt signal generation unit 413 outputs an interrupt signal to the XURST terminal of the CPU 401 based on the output signal from the XMI terminal of the CPU 401 and the system reset signal. That is, the interrupt signal generation unit 413 performs a counting operation based on the output signal from the XMI terminal of the CPU 401 becoming L level, and supplies the CPU 401 with an interrupt signal that is a pulse signal having a constant period.
[0119]
16 decodes an address signal from the CPU 401 and sends a device selection signal (CS0 to CS6) and a gate signal (G) to the input / output circuit unit 500 (see FIG. 11). Output. The device selection signal (CS0 to CS6) is a signal for selecting an external device, and the gate signal (G) is a signal for enabling the device selection signal (CS). The device selection signals (CS0 to CS6) include an output device selection signal (CS0 to CS5) and an input device selection signal (CS6).
[0120]
The output device selection signal (CS0 to CS5) is when the CPU 401 is in a state of writing data to the input / output circuit unit 500 (see FIG. 5) and the range address of the PB0 / XCSIO0 terminal is designated. When a predetermined address signal is output from the A4 terminal, the signal is output from the decoder IC 423 to the flip-flops IC511 to 561. That is, when the data of the D0 to D7 terminals of the CPU 401 is output to the input / output circuit unit 500 (see FIG. 5) via the data bus, the output device selection signals (CS0 to CS5) are output ports 390 shown in FIG. (Described later), and data is input to the 1D to 8D terminals of the flip-flop ICs 511, 521, 531, 541, 551, and 561. The address signal is decoded into an output device selection signal (CS0 to CS5) by the I / O decode circuit unit 420, which is transmitted to the output port 390 (see FIG. 22) and is sent to the clock terminal of the corresponding flip-flop IC. Entered.
[0121]
The input device selection signal (CS6) is output from the decoder IC 424 to the buffer IC 571 (see FIG. 21) when a predetermined address signal is output from the A0 to A4 terminals and output from the PB1 / XCSIO1 terminal. Is done. Further, the gate signal generation unit 416 generates a gate signal (G) based on the oscillation clock output from the crystal oscillation module 404 and the output signals of the XRD terminal and the XIORQ terminal of the CPU 401, which are also output to the buffer IC 571. Is done. That is, when both the input device selection signal (CS6) and the gate signal (G) are output to the buffer IC 571 (see FIG. 21), the data of the Y1 to Y8 terminals of the buffer IC 571 (see FIG. 21) is the data bus. Through the terminals D0 to D7 of the CPU 401. The address signal is decoded by the I / O decode circuit unit 420 into an input device selection signal (CS6), which is input to the G1 terminal of the buffer IC 571 (see FIG. 21).
[0122]
Further, in this embodiment, as shown in FIG. 16, the impedance on the input terminal side is reduced by the resistor arrays 421, 428, and 429, and the output selection signal, the input selection signal, and the gate generated by the device selection signal generation unit, respectively. The influence of external noise or the like on the gate signal generated by the signal signal generation unit 416 is suppressed. In this embodiment, the data bus (OD, D) is divided into two paths. This is due to the load capacity between the CPU 401 and the flip-flop ICs 511 to 561 shown in FIG. 22, and may have a circuit configuration that does not need to be divided into two paths.
[0123]
The data bus stabilization unit 411 shown in FIG. 16 stabilizes the signal on the data bus connecting the CPU 401 and the input / output circuit unit 500 {see FIG. 4A}. The resistor array 403 reduces the noise entering the bus by reducing the impedance, and the buffer 402, among the data buses divided into two paths, each of the command output circuit units 510, 520, and 530 for the award ball, lamp, display, and voice. , 540 (see FIG. 18), the output signal (OD0 to OD7) of the bus (OD) is amplified.
[0124]
Here, in the first external input circuit unit 430 shown in FIG. 17, signals of the ball detection switches requested from the CPU 401 are transmitted to the CPU 401. That is, various switch groups are connected to the first external input circuit unit 430 via the input connector unit 440, and when the CPU 401 reads the switch state, the state of each switch is changed from O1 to O5 of the switch driver 432. The data is sent to the CPU 401 from the terminal and the VO terminal. In this embodiment, six output terminals (O1 to O5 terminals, VO terminals) of the switch driver 432 are used in accordance with the number of associated ball dust switches. These six terminals individually correspond to the six ports (PA0 to PA5) assigned by the CPU 401. In the present embodiment, the impedance of the PA0 to PA5 terminals is reduced by the resistor array 431, and the influence of external noise and the like is suppressed.
[0125]
In FIG. 17, the signal from the input connector 440 is subjected to noise removal by a combination of the standardized signal stabilization unit 434 or the signal matching unit 433 and the internal circuit of the switch driver 432. Further, the signal matching unit 433 also performs voltage adjustment. This is based on the fact that some of the switches connected to the input connector 440 have branched transmission destinations, and the detection signal is sent to other than the main control board 340. That is, since the load of the circuit system related to the switch is larger than that of other switches, the characteristics of the signal are different from those of other signals. Therefore, a signal matching unit 433 is provided on the corresponding signal line to achieve matching with other signals. The output signal of the signal matching unit 433 is input to the V1 terminal of the switch driver 432.
[0126]
Next, the input / output circuit unit 500 will be described.
As shown in FIG. 13, the input / output circuit unit 500 includes a prize ball command output circuit unit 510, a lamp command output circuit unit 520, a display command output circuit unit 530, a voice command output circuit unit 540, a solenoid drive circuit unit 550, An LED drive / information output circuit unit 560 and a second external input circuit unit 570 are provided. Further, the aforementioned external terminal portion 145 is connected to the signal transmission path 500a to which these circuit portions 500 to 570 are connected.
[0127]
Among the circuit units 510 to 570 described above, the prize ball command output circuit unit 510, the lamp command output circuit unit 520, the display command output circuit unit 530, and the voice command output circuit unit 540 all have the same circuit configuration. is doing. Therefore, in this embodiment, in order to avoid redundant drawings, only the prize ball command output circuit unit 510 is shown (FIG. 18), and the other circuit units 520, 530, and 540 are denoted by parentheses in FIG. These illustrations are omitted only for writing. That is, the output circuit units 510, 520, 530, and 540 are connected to the flip-flop ICs 511, 521, 531, 541, the buffer ICs 512, 522, 532, and 542, and the strobe signal line buffer ICs 513, 523, 533, and 543, respectively. And connectors 514, 524, 534, and 544.
[0128]
19 includes a flip-flop IC551, three lamp / solenoid drivers 552 to 554, and a freewheel diode 555 connected in parallel to the drain terminals of the lamp / solenoid driver. And an output connector 556.
[0129]
20 includes a flip-flop IC561, a transistor array 562, a lamp / solenoid driver 563, a relay unit 565, a power adjustment unit 564, an output connector 556, and an information output connector 566. Further, the flip-flop IC551 is also responsible for part of that. The relay unit 565 includes two relays 567 and 568, and the power adjustment unit 564 includes ten resistors R4 to R13.
[0130]
The second external input circuit unit 570 shown in FIG. 21 has a buffer IC 571, a switch driver 572, a low resistance array 573, a power adjustment unit 574, and an output connector 556. The power adjustment unit 574 includes six resistors R21 to R26.
[0131]
Further, as shown in FIG. 18, the prize ball command output circuit unit 510, the lamp command output circuit unit 520, the display command output circuit unit 530, the voice command output circuit unit 540, the solenoid drive circuit unit 550, and the LED drive / information output. The flip-flop ICs 511, 521, 531, 541, 551, and 561 of the circuit unit 560 constitute six output ports of the output port circuit unit 390.
[0132]
Next, the function of each of the circuit units 510, 520, 530, 540, 550, 560, and 570 of the input / output circuit unit 500 will be described. In the output port circuit unit 390 shown in FIG. 22, data (OD, D), a device selection signal (CS0 to CS5), and a clear signal (CLR) from the main circuit unit 400 are input. An external device is assigned to each port of the output port circuit unit 390. Examples of the external device include a prize ball device, a lamp device, a display device, a sound device, a solenoid device, an LED device, and a hall computer.
[0133]
Data (OD) is input to the 1D to 8D terminals of the flip-flops IC511 to 541, and data (D) is input to the 1D to 8D terminals of the flip-flops IC551 and 661. The device selection signals (CS0 to CS5) are input to the Clock terminals of the corresponding flip-flops IC511 to 541. In the flip-flop ICs 511 to 541 selected by the device selection signal (CS0 to CS5), the data (OD, D) from the main circuit unit 400 is input to the 1D to 8D terminals, and the device selection signal (CS0 to CS5) Data is output from the 1Q to 8Q terminals at the timing of the rising edge. Further, in the output port circuit unit 390, when the power to the pachinko machine 1 is turned on, the flip-flop ICs 511, 521, 531, 541, 551 are received by the initialization reset signal from the general-purpose initialization reset signal generation unit 418 described above. 561 is initialized.
[0134]
The various command output circuit units 510 to 540 shown in FIG. 18 transmit command data to a prize ball device, a lamp device, a display device, and an audio device, which are external devices at the subsequent stage. That is, one of the command output circuits 510 to 540 is selected by the device selection signal (CS0 to CS3). Then, the command data output from the flip-flop ICs 511 to 541 is input to the A1 to A8 terminals of the buffer ICs 512 to 542 and output to the connection connectors 514 to 544. The output enable terminals G1 and G2 of each of the buffer ICs 512 to 542 are grounded, and a signal with enhanced drive capability is output from the buffer ICs 512 to 542. The control signals handled by the various command output circuit units 510 to 540 are 9 bits in total including 8 bits of data and 1 bit of strobe, but the number of data bits may be changed depending on the connected external device.
[0135]
A solenoid drive circuit unit 550 shown in FIG. 19 is a circuit unit that is selected by a device selection signal (CS4) and drives a solenoid device that is an external device in accordance with the gaming state. In the solenoid drive circuit section 550, lamp / solenoid drivers 552 to 554 are provided corresponding to the respective solenoids. The flip-flop IC 551 outputs a signal from the 5Q to 7Q terminals to the corresponding lamp / solenoid driver 552 to 554. Further, when the input signal from the flip-flop IC551 to the IN terminals of the lamp / solenoid drivers 552 to 554 is at the H level, the lamp / solenoid drivers 552 to 554 drive the solenoid device. Further, the flip-flop IC 551 also functions as a strobe signal generation unit that transmits a strobe signal to the command output circuit units 510 to 540 as shown in FIG. That is, the flip-flop IC551 transmits the output signals from the 1Q to 4Q terminals as strobe signals to the strobe signal line buffers IC513 to 543 of the corresponding command output circuit units 510 to 540.
[0136]
Returning to FIG. 19, the free wheel diode 555 of the solenoid drive circuit unit 550 maintains the load current during the high-speed switching operation, so that the output signals of the lamp / solenoid drivers 552 to 554 are switched from the H level to the L level. , Reflux the sustained current. In place of the lamp / solenoid drivers 552 to 554, the solenoid can be driven using, for example, a transistor or FET.
[0137]
An LED drive / information output circuit unit 560 shown in FIG. 20 is used for driving a normal design LED and outputting external information to a hall computer or the like. Data output from the flip-flop IC561 of the LED drive / information output circuit unit 560 is input to the terminals I1 to I8 of the transistor array 562. In the transistor array 562, 2 bits are normally assigned to the design LED, 6 bits are assigned to the external information output, and the outputs of the O1 to O7 terminals are output to the output connector 556. The output of the O8 terminal is sent to the information output connector 566 via the relay 568 of the relay unit 565. Note that the current of the output signal of the transistor array 562 is regulated by the resistances R4 to R13 of the protective resistance unit 564.
[0138]
The second external input circuit unit 570 shown in FIG. 21 is a circuit unit that inputs the state of various switches to the CPU 401, and the number of signal lines of the data bus (D) to be used corresponds to the number of connected switches. ing. A detection signal from the output connector 556 is input to the terminals I1 to I6 of the switch driver 572 via the power adjustment unit 574. In the power adjustment unit 574, noise removal and voltage adjustment are performed by a combination of the resistors R21 to R26 and the internal circuit of the switch driver 572. Output signals from the O1 to O6 terminals of the switch driver 572 are input to the buffer IC 571. The switch driver 572 has a short-circuit detection function, and when a switch connected to the I1 and I2 terminals is in a short-circuit state, the output signal changes from H level to L level. Furthermore, the resistor array 573 reduces the impedance of the A1 to A8 terminals of the buffer IC 571 to suppress the influence of external noise and the like.
[0139]
The gate signal (G) from the main circuit unit 400 is input to the G2 terminal of the buffer IC 571, and the buffer IC 571 amplifies the signal from the switch driver 572 and outputs it to the data bus (D).
[0140]
In the pachinko machine 1 of the present embodiment, as the pachinko machine 1 is powered on, the power supplied to the pachinko machine 1 from the outside rises, and a system reset signal (power-on reset signal) is supplied to the main control board 340, and the CPU 401 When the CPU initialization reset signal as described above is supplied, the CPU 401 is initialized by the CPU initialization reset signal at the L level after the externally supplied power rises. Thereafter, the CPU initialization reset signal once rises, then falls, and returns to the L level, so that the CPU 401 receives the initialization signal again. Then, the CPU initialization reset signal again indicates the H level, and the control of the pachinko machine 1 shifts to a steady state. In other words, according to the pachinko machine 1, since the CPU initialization reset signal is provided with a plurality of changes, the CPU 401 is more reliably and stably compared to the case where only a single change is given. Can be initialized, and the operation of the gaming machine can be stabilized. The reason why such a result was obtained is as follows. In other words, when the power of the pachinko machine 1 is shut off, the charge stored in the capacitor constituting the noise filter or the like remains in the internal circuit of the CPU 401. As a result, a signal exceeding the open value is generated partly early, and the rise of the power supply potential is influenced by the fact that the initialization signal to the CPU 401 shows the same level at the time of initialization of the CPU 401. Unbalance occurs, and the stability of the control is impaired. However, like the pachinko machine 1 of the present embodiment, by giving a plurality of changes to the CPU initialization reset signal, a change form of additional compensation is included. It is possible to eliminate the remaining defective elements that could not be achieved.
[0141]
Note that the CPU initialization reset signal generation unit 414 may be provided inside the CPU 401. In this way, the external circuit of the CPU 401 can be simplified and the main control board 340 can be downsized. And it becomes possible to simplify the back configuration of the pachinko machine 1 and to increase the degree of freedom in the design of the arrangement of the spear where the game balls flow down. Furthermore, in this embodiment, the first change form of the CPU initialization reset signal is a rising form, and the second change form is a falling form of the same signal. These may be considered as a constant waveform pattern including rising and falling, and may be combined. In this case, the number of rises and falls is not limited to one, and one or more selections can be made as appropriate. For example, the fall after the power is turned on and the subsequent rise of the CPU initialization signal in the present embodiment can be regarded as the second variation.
[0142]
Next, the external initial value counter 460 and the delay circuit 800 will be described in detail. First, as shown in FIG. 23, the external initial value counter 460 includes a clock oscillation unit 910 that oscillates a clock signal at a predetermined frequency, and a clock counter unit 920 that counts the number of clock signals generated by the clock oscillation unit 910. I have. That is, the electrical signal generated by the clock oscillation unit 910 is counted by the clock counter unit 920.
[0143]
The clock oscillation unit 910 generates a 10 MHz clock signal using a crystal oscillation circuit. The clock counter unit 920 is composed of an 8-bit IC and can store a numerical value of “0 to 255”. Unless the “reset signal” is input from the CCKEN terminal, the count is increased or updated by “+1” in accordance with the input of the clock signal from the CCK terminal. Therefore, in the external initial value counter 460, the numerical value can be updated by one count in the range of “0 to 255”. In this embodiment, since the frequency of the clock signal generated by the external initial value counter 460 and the frequency of the clock signal generated by the clock generator 484 of the CPU 401 do not match, the update of the external initial value counter 460 and the random number of the RAM 481 are performed. The counter 481v is updated asynchronously.
[0144]
In the present embodiment, other embodiments described later, and modifications, the count number when the external counter 460 counts once can be changed. For example, the clock counter 920 is composed of two 8-bit ICs, and one IC is a lower counter and the other IC is an upper counter. Then, the CCKEN terminal of the upper counter is connected to the RCO terminal of the lower counter, and both the lower and upper counters are connected in series. According to this, the external counter 460 substantially constitutes a 16-bit counter and can store numerical values from 0 to 65535.
[0145]
Next, the delay circuit 800 will be described with reference to FIGS. The delay circuit 800 is provided on the “output-side signal line 801” of the external initial value counter 460. That is, the inlet side end of the delay circuit 800 is connected to a portion of the signal line 801 on the external initial value counter 460 side via the inverter 810, and the outlet side end of the delay circuit 800 is also connected to the inverter (one of the waveform shapers). A specific example is shown.) The signal line 801 is connected to the CPU 401 (output port 930) side portion via the 820. In this embodiment, the inverter 810 at the inlet end of the delay circuit 800 can be omitted.
[0146]
As shown in FIG. 24, the delay circuit 800 includes a branch portion 830 that branches in parallel with the main line portion 825 and has a termination 826, and a capacitor 850 is provided in the middle of the branch portion 830. Has been placed. Further, in the main line portion 825, a resistor 860 is arranged in series with respect to the main line portion 825 between the branch portion 830 and an inverter (one specific example of a waveform shaper) 820.
[0147]
Next, the function of the delay circuit 800 will be described with reference to FIGS. 25A shows “the waveform of the output signal from the external initial value counter 460”, and FIG. 25B shows the “waveform of the signal after passing through the inverter 810”. FIG. 25C shows a “waveform of a signal when passing through the delay circuit 800”, and FIG. 25D shows a “waveform of a signal after passing through the inverter 820”.
[0148]
As shown in FIG. 25A, the output signal from the external initial value counter 460 is a rectangular wave (refer to the rectangular wave A). However, when the output signal becomes H level (high level), the capacitor 850 gradually increases. {Refer to the rising curve E in FIG. 25 (c). }. On the other hand, when the output signal from the external initial value counter 460 becomes L level (low level), the capacitor 850 gradually discharges against the resistor 860 {the downward curve F of FIG. reference. }. The waveform of the signal when passing through the delay circuit 800 becomes a sawtooth waveform N as shown in FIG. 32 (c) as the capacitor 850 is charged and discharged. That is, when the input signal to the delay circuit 800 becomes H level and the capacitor 850 is gradually charged, a rising slope curve E is drawn, the input signal to the delay circuit 800 becomes L level, and the capacitor 850 gradually When discharging, a downward sloped curve F is drawn.
[0149]
When such a sawtooth signal passes through the inverter 820, the signal is set to an H level and an L level based on a constant “threshold value {refer to the broken line D in FIG. 25 (c)}”. And again becomes a rectangular wave B {see FIG. 25 (c)}. However, the signal that is the source of the rectangular wave B is a sawtooth waveform N that is a combination of a rising sloped curve E (a curve having a smaller slope than the rising part of the rectangular wave) and a downward sloped curve F. For the sake of illustration, the “rising portion of the rectangular wave B from the L level to the H level” is referred to as a predetermined time (hereinafter referred to as “delay time”) compared to the “rising portion of the rectangular wave A from the L level to the H level”. ) T will be delayed {FIG. 25 (c)}.
[0150]
(4) Random number counter update processing
Next, a method for updating the random number counter 481v (see FIG. 11) will be described with reference to FIG. Here, the random number counter 481v is a “counter for determining occurrence of jackpot” as described above. That is, when the game ball wins the first type starting port (ordinary electric accessory) 17, the “determination random value” acquired from the random number counter 481v and the jackpot number memory 481h (see FIG. 11) are read. The "big hit number (winning judgment value)" is compared in the above-mentioned "S260", and if both match, a big hit determination is made, and if they do not match, a loss judgment is made.
[0151]
When the power of the pachinko machine 1 is turned on, the value of the random number counter 481v is set to an initial value “0” for each interruption of the “CPU 91 of the main control unit 140” (every 2 milliseconds in this embodiment). When “+1” is added / updated and reaches the maximum value (255 in this embodiment), the value returns to the initial value (0). That is, the value of the random number counter 481v is updated by 1 count for each interrupt in the range of “0 to 255”. Note that the update range of the random number counter 481v is not limited to the 256 numbers.
[0152]
In the present embodiment, the value of the random number counter 481v goes around once (in this embodiment, n = 1), and when it reaches the maximum value, it returns to the initial value “0” as described below. Then, the “initial value random number” is obtained from the external initial value counter 460 (see FIG. 23). Then, the value of the random number counter 481v is incremented and updated by “+1” for each interrupt, with this “initial value random number” as a “new initial value”, and when it reaches the maximum value (255 in this embodiment), A system is adopted that returns to the initial value (0) and repeats until the value of the random number counter 481v reaches the value “−1” of the “new initial value”.
[0153]
The external initial value counter 460 (see FIG. 23) is a counter for determining an initial value for updating the random number counter 481v. The value of the external initial value counter 460 is updated asynchronously with the update of the random number counter 481v. Then, the initial value “0” is incremented and updated by “+1” at a high speed. When the maximum value (255 in this embodiment) is reached, the initial value (0) is restored, and this is repeated thereafter.
[0154]
Next, the update process of the random number counter will be described more specifically. The “initial value memory 481c” in FIGS. 11 and 26 is a memory for storing the initial value of the random number counter 481v.
[0155]
First, after the power to the pachinko machine 1 is turned on, if it is the first reset interrupt process, an initialization process of the RAM 481 described later is performed. In the case of a reset interrupt process performed after the initialization process of the RAM 481 or after the power is turned on, the update process (S700) of FIG. 25 is performed. In this update process (S700), first, it is determined whether or not the value of the random number counter 481v is “256” or more (S705). If the value of the random number counter 481v is less than “256” (S705; NO) ), The value of the random number counter 481v is updated by adding “+1” (S710). On the other hand, if the value of the random number counter 481v is “256” or more (S705; YES), the value of the random number counter 481v is cleared to “0” (S715). By each processing of S705, S710, and S715, the value of the random number counter 481v is updated by one count within the range of “0 to 255”.
[0156]
After updating the value of the random number counter 481v, it is determined whether the value of the random number counter 481v matches the initial value memory 481c (720S). If the values of both 481v and 481c do not match (S720: NO), the value of the random number counter 481v has not yet been updated once. In this case, the initial value of the update of the random number counter 481v is used as the update value. Without changing, the updating process of the random number counter is terminated, and the process returns to the reset interrupt process.
[0157]
On the other hand, after the value of the random number counter 481v is updated, when the value of the random number counter 481v matches the initial value memory 481c (S720: YES), the update of the value of the random number counter 481v is completed once. Therefore, the initial value for updating the random number counter 481v is changed. That is, the value of the external initial value counter 460 at that time is read (S725), and the read value of the external initial value counter 460 is written in the random number counter 481v and the initial value memory 481c, and the random number counter 481v is updated. The initial value is changed and the initial value of this update is stored (S730, S740). Then, after changing the initial value of the update of the random number counter 481v and the initial value memory 481c, the update process of the random number counter is finished. Then, returning to the reset interrupt process, after the remaining time elapses, the next reset interrupt process occurs, and the next “random number counter update process” is performed.
[0158]
(5) Effects of Example 1
In the pachinko machine 1 of the present embodiment, when a reset signal is transmitted while the RAM clear switch 144 is operated (pressed) (hereinafter referred to as “RAM clear operation”), the initialization processing of the RAM shown in FIG. S800) is performed. That is, the clear value is written in the entire area of the RAM 481 (S805), the initial value is set in the entire area of the RAM 481 (S810), the value of the external initial value counter 460 is read (S815), and the read external initial value counter is read. The value of 460 is written into the random number counter 481v and the initial value memory 481c (S820, S825), and the value of the external initial value counter 460 is used as the initial value for updating the random number counter 481v.
[0159]
  In this embodiment, a delay circuit 800 is provided between the external initial value counter 460 and the CPU 401 (output port 930).I will.
[0160]
  In addition, in this embodiment, since the “capacitor 850 and resistor 860” constituting the delay circuit 800 generally depend on changes in the surrounding environment such as temperature change and humidity change, The charging speed and discharging speed of the capacitor 850 change, and the “sawtooth waveform B” also shows various forms. That is, as shown in FIGS. 24E to 24G, the delay time t does not increase or decrease in accordance with changes in the surrounding environment such as temperature change and humidity change.The
[0161]
Furthermore, according to this embodiment, even if the RAM 481 is initialized and the random number counter 481v is initialized, the external initial value counter 460 is counted regardless of the initialization process. That is, even when the initialization process of the RAM 481 is executed, the initial value of the random number counter 481v can be determined based on the value of the external initial value counter 460, and the validity determination control can be performed. In other words, it is possible to avoid a situation in which “the value of the random number counter 481v (random number) is always initialized to 0 when the RAM clear process is executed”.
[0162]
Therefore, according to the present embodiment, it is difficult to estimate the value (random number) of the random number counter 481 from the outside of the main control board 340 even if the RAM clear process is executed due to the cheating of the cheating person. Therefore, it is possible to prevent cheating by fraudsters. In this embodiment and other embodiments and modifications described later, the random number generated by the external initial value counter 460 is significant in that it is a so-called “hardware random number”. That is, the hardware random number is a random number that counts a signal that is generated regardless of software processing. With software random numbers generated by software processing, it takes a relatively long time for the random numbers to complete. In other words, if the value of the initial counter is updated every 2 milliseconds, it takes 640 milliseconds for the random number to make a round. On the other hand, with a hardware random number, it is easy to obtain a signal of about 10 MHz, and in this case, the counter value can be updated every 0.1 microseconds. Therefore, in hardware random numbers, the time required for a round of random numbers is so short that it cannot be compared with software random numbers, which makes it even more difficult for fraudsters to understand the timing of wins. . In addition, in this embodiment, since the hardware random number is used for the initial value counter and the software random number is used for the random number counter, the uniformity of the success / failure random numbers can be maintained, and the occurrence of bias in the occurrence of the jackpot is prevented. it can.
[0163]
  Next, a modification of the present embodiment will be described. In this modification, FIG. 28 is applied instead of FIG.26A configuration similar to that of the first embodiment is provided except that FIG. 29 is applied instead of FIG. That is, as shown in FIG. 28, as an initial value counter, an external initial value counter 460 and an internal initial value counter 481w provided in the RAM 481 are provided, and as shown in FIG. 29, an internal initial value counter 481w is provided. A configuration similar to that of the first embodiment is provided except that the update processing of the random number counter 481v is used. Therefore, FIGS. 1 to 10, FIG. 15, FIG. 24, and FIG. 26 used in the first embodiment and the detailed description thereof can be applied to the present modification as they are. Also, in FIG. 28 and FIG. 29, the detailed description regarding the common part with FIG. 14 and FIG. 25 can be applied as it is.
[0164]
The external initial value counter 460 according to the present modification also has the same configuration as the external initial value counter 460 according to the first embodiment, and is connected to the CPU 401 via the output port 930. When the power of the pachinko machine 1 is turned on, the value of the random number counter 481v in this embodiment is also set to the initial value “0” for each interrupt of the “CPU 91 of the main control unit 140” (in this embodiment, 2 msec. Every time, “+1” is added / updated, and when it reaches the maximum value (255 in this embodiment), it returns to the initial value (0). That is, the value of the random number counter 481v of this embodiment is also updated by one count for each interrupt within the range of “0 to 255”. Note that the update range of the random number counter 481v is not limited to the 256 numbers.
[0165]
Also in this modification, the value of the random number counter 481v goes around once (in this modification, n = 1), and when the maximum value is reached, the initial value “0” is returned to as described below. Then, the “initial value random number” is obtained from the internal initial value counter 481w (see FIG. 28). Then, the value of the random number counter 481v is incremented and updated by “+1” for each interrupt, with this “initial value random number” as a “new initial value”, and when it reaches the maximum value (255 in this embodiment), A system is adopted that returns to the initial value (0) and repeats until the value of the random number counter 481v reaches the value “−1” of the “new initial value”.
[0166]
The internal initial value counter 481w (see FIG. 28) is a counter for determining an initial value for updating the random number counter 481v. The value of the internal initial value counter 481w is also turned on to the pachinko machine 1. Then, as the initial value “0”, “+1” is added / updated for each “interrupt” and the remaining time (S180) in FIG. 7 to reach the maximum value (255 in this embodiment). Return to the initial value (0) and repeat this. However, also in the modified embodiment, the value of the external initial value counter 460 is updated asynchronously with the value of the internal initial value counter 481w and the value of the random number counter 481v. Further, the value of the internal initial value counter 481w may be updated only in the remaining time (S180) in FIG. 7, and the update range of the internal initial value counter 481w may be other than 256 ways. Furthermore, this remaining time is an indefinite time that varies depending on the game situation.
[0167]
Next, the update processing of the random number counter will be described more specifically with reference to FIG. First, after the power to the pachinko machine 1 is turned on, if it is the first reset interrupt process, an initialization process of the RAM 481 described later is performed. In the case of reset interrupt processing performed after the initialization processing of the RAM 481 or after the power is turned on, the update processing (S750) in FIG. 29 is performed. In this update process (S750), it is first determined whether or not the value of the random number counter 481v is “256” or more (S755). If the value of the random number counter 481v is less than “256” (S755; NO) ), The value of the random number counter 481v is updated by adding “+1” (S760). On the other hand, if the value of the random number counter 481v is “256” or more (S755; YES), the value of the random number counter 481v is cleared to “0” (S765). By each processing of S755, S760, and S765, the value of the random number counter 481v is updated by one count within the range of “0 to 255”.
[0168]
After updating the value of the random number counter 481v, it is determined whether or not the value of the random number counter 481v matches the initial value memory 481c (S770). If the values of the two 481v and 481c do not match (S770: NO), the value of the random number counter 481v has not been updated yet. In this case, the initial value of the update of the random number counter 481v is used. Without changing, the updating process of the random number counter is terminated, and the process returns to the reset interrupt process.
[0169]
On the other hand, after the value of the random number counter 481v is updated, when the value of the random number counter 481v matches the initial value memory 481c (S770: YES), the update of the value of the random number counter 481v is completed once. Therefore, the initial value for updating the random number counter 481v is changed. That is, the value of the internal initial value counter 481w at that time is read (S775), and the read value of the internal initial value counter 481w is written in the random number counter 481v and the initial value memory 481c, and the random number counter 481v is updated. The initial value is changed and the initial value of this update is stored (S780, S790). Then, after changing the initial value of the update of the random number counter 481v and the initial value memory 481c, the update process of the random number counter is finished. Then, returning to the reset interrupt process, after the remaining time elapses, the next reset interrupt process occurs, and the next “random number counter update process” is performed.
[0170]
Further, the process at the time of RAM clear is performed in the same manner as in the first embodiment according to FIG. 27 described above. In this modification, even if the initialization process is performed on the RAM 481 and the random number counter 481v is initialized, the external initial value counter 460 is counted regardless of the initialization process. That is, even when the initialization process of the RAM 481 is executed, the initial value of the random number counter 481v can be determined based on the value of the external initial value counter 460, and the validity determination control can be performed. In other words, it is possible to avoid a situation in which “the value of the random number counter 481v (random number) is always initialized to 0 when the RAM clear process is executed”. Accordingly, it is difficult to estimate the value of the random number counter 481 (random number) from the outside of the main control board 340 even if the RAM clear process is executed due to the cheating by the cheating agent. Can be prevented.
[0171]
  Further, also in this modification, a delay circuit 800 is provided between the external initial value counter 460 and the CPU 401 (output port 930).The
[0172]
  In addition, in this embodiment, since the “capacitor 850 and resistor 860” constituting the delay circuit 800 generally depend on changes in the surrounding environment such as temperature change and humidity change, The charging speed and discharging speed of the capacitor 850 change, and the “sawtooth waveform B” also shows various forms. That is, figure25As shown in (e) to (g), the delay time t does not increase or decrease according to changes in the surrounding environment such as temperature change and humidity change.The
[0182]
  Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and is not limited to the wording of each claim without departing from the scope described in each claim. Can be easily replaced by these, and improvements based on knowledge that a person skilled in the art normally has can be added as appropriate.That is, bookIn the embodiments of the present invention, the RAM clear switch 144 is provided in the main control board 340. However, in the present invention, the RAM clear switch may be provided outside the main control board, for example, a power terminal board.
[0183]
【The invention's effect】
As described above, according to the present invention, it is possible to obtain a gaming machine that can prevent “an illegal act of generating a jackpot by intentionally generating a RAM clear”.
[Brief description of the drawings]
[Figure 1]FruitExamples1 and strangeIt is a front view showing a gaming machine according to a form example.
[Figure 2]FruitExamples1 and strangeIt is a front view which shows the game board of the game machine which concerns on an example.
[Fig. 3]FruitExamples1 and strangeIt is a back view which shows the game machine which concerns on a example.
[Fig. 4]FruitExamples1 and strangeIt is a block diagram which shows the electronic control apparatus with which the gaming machine which concerns on an example is provided.
5A is an explanatory diagram of a main control unit configuring the electronic control device of FIG. 4, and FIG. 5B is an explanatory diagram of a frame control unit configuring the electronic control device of FIG. 4;
6A is an explanatory diagram of a special symbol control unit that constitutes the electronic control device of FIG. 4, and FIG. 6B is an explanatory diagram of a lamp control unit that constitutes the electronic control device of FIG. c) is an explanatory diagram of a voice control unit constituting the electronic control device of FIG.
[Fig. 7]FruitExamples1 and strangeIt is a flowchart for demonstrating the main job which the main control part which concerns on an example.
[Fig. 8]FruitExamples1 and strangeIn a form example, it is a flowchart which shows a process when power supply interruption (power failure etc.) generate | occur | produces.
FIG. 9FruitExamples1 and strangeIn a form example, it is a flowchart which shows a power recovery process when a power failure (power failure etc.) generate | occur | produces.
FIG. 10FruitExamples1 and strangeIt is a flowchart for demonstrating the success / failure determination job which concerns on an example.
FIG. 11 is an explanatory diagram illustrating representative examples of various memories and the like stored in a built-in RAM of the main control unit according to the first embodiment.
FIG.FruitExamples1 and deformationIt is a flowchart for demonstrating the outline of the special symbol main job which concerns on an example.
FIG. 13 is an explanatory diagram illustrating a main control unit according to the first embodiment.
FIG. 14 is an explanatory diagram illustrating a CPU that constitutes a main control unit according to the first embodiment;
FIG. 15FruitExamples1 and Modification 1It is a circuit diagram which shows the connection state of the reset circuit part in and CPU.
FIG. 16FruitExamples1 and strangeIt is a circuit diagram which shows the connection state of the I / O decoding circuit part in the main control part which concerns on an example, and CPU.
FIG. 17FruitExamples1 and deformationIt is a circuit diagram which shows the connection state of the 1st external input circuit part in the main control part which concerns on an example, and CPU.
FIG. 18FruitExamples1 and strangeIt is a circuit diagram which shows the structure of the command output circuit part which concerns on an example.
FIG. 19FruitExamples1 and strangeIt is a circuit diagram which shows the structure of the solenoid drive circuit part which concerns on an example.
FIG. 20FruitExamples1 and strangeIt is a circuit diagram which shows the structure of the LED drive and information output circuit part which concerns on an example.
FIG. 21FruitExamples1 and strangeIt is a circuit diagram which shows the structure of the 2nd external input circuit part which concerns on an example.
FIG. 22FruitExamples1 and strangeIt is a circuit diagram which shows the structure of the output port part which concerns on an example.
FIG. 23 shows an external initial value count according to the first embodiment (modified example).TFIG.
FIG. 24 shows the first embodiment (deformationExample)It is a circuit diagram for demonstrating the delay circuit which concerns.
FIG. 25 shows a first embodiment (modified example).)It is explanatory drawing which shows the waveform of the signal in the delay circuit etc. which concern.
FIG. 26 Example13 is a flowchart showing a random number counter update process.
FIG. 27 Example15 is a flowchart showing the “RAM initialization process” performed in FIG.
FIG. 28 is an explanatory diagram illustrating a CPU configuring a main control unit according to a modification of the first embodiment.
FIG. 29 is a flowchart showing “RAM initialization processing” performed in a modification of the first embodiment;The
[Explanation of symbols]
1 Pachinko machine (game machine)
10 Game board
16 Special symbol display device (variable display device)
140 Main control unit
150 Frame control unit
160 Special design controller
340 Main control board
401 CPU (control means)
481 RAM (storage means)
481v Internal random number counter
481w Internal initial value counter
482 ROM (storage means)
460 External initial value countT
800 delaycircuit.

Claims (6)

A main control unit that controls basic progression control of the game, and a variable display device that variably displays a plurality of identification information when a predetermined condition is satisfied, and the game is based on the fact that the stop mode of the variable display device achieves a specific condition A gaming machine that gives a particular value to a person,
A random number counter that is periodically updated within a certain range and whose initial value is changed every time n (n is a natural number) is updated;
A storage unit that stores a storage unit storing a determination program that reads out the value of the random number counter when the predetermined condition is satisfied, and determines whether or not the random number counter is read using the read value of the random number counter.
Control means for performing the determination of the success / failure by the determination program of the success / failure;
Storage means for storing data used during execution of the success / failure determination program;
An initial value counter that counts an initial value for updating the random number counter, and a gaming machine comprising:
A CPU functioning as the control means;
The CPU includes a RAM functioning as the storage unit, and the random number counter is provided in the RAM.
The initial value counter is an external initial value counter provided outside the CPU;
While providing a delay circuit between the CPU and the external initial value counter,
A gaming machine, wherein the external initial value counter determines an initial value of the random number counter when the random number counter is initialized. A main control unit that controls basic progression control of the game, and a variable display device that variably displays a plurality of identification information when a predetermined condition is satisfied, and the game is based on the fact that the stop mode of the variable display device achieves a specific condition A gaming machine that gives a particular value to a person,
  A random number counter that is periodically updated within a certain range and whose initial value is changed every time n (n is a natural number) is updated;
  A storage unit that stores a storage unit storing a determination program that reads out the value of the random number counter when the predetermined condition is satisfied, and determines whether or not the random number counter is read using the read value of the random number counter.
  Control means for performing the determination of the success / failure by the determination program of the success / failure;
  Storage means for storing data used during execution of the success / failure determination program;
  An initial value counter that counts an initial value for updating the random number counter, and a gaming machine comprising:
A CPU functioning as the control means;
  The CPU includes a RAM functioning as the storage means, the random number counter is provided in the RAM,
  As the initial value counter, an internal initial value counter provided in the RAM, and an external initial value counter provided outside the CPU,
  While providing a delay circuit between the CPU and the external initial value counter,
  In order to determine the initial value of the random number counter when the random number counter is initialized by the external initial value counter, and to update the random number counter when the random number counter is not initialized by the internal initial value counter A game machine characterized by determining an initial value of. 3. The gaming machine according to claim 1, wherein a delay time of the delay circuit is determined by an external element depending on an environment. The outer initial value counter, game machine mounting serial to any one of claims 1-3, characterized in that it is updated asynchronously and update the random number counter. 5. The external initial value counter includes a clock oscillation unit that generates a clock signal at a predetermined frequency and a clock counter unit that counts the number of clock signals generated by the clock oscillation unit. Gaming machine. The outer initial value counter, a game machine according to claim 4 or 5 Symbol mounting and having a backup power supply.
Listed gaming machines

Images