JP6490622B2 - Game machine - Google Patents

Description

  The present invention relates to a gaming machine such as a pachinko gaming machine capable of playing a game.

  As a gaming machine, a game ball, which is a game medium, is launched into a game area by a launching device, and when a game ball wins a prize area such as a prize opening provided in the game area, a predetermined number of prize balls are paid out to the player. There is something to be done. Further, a variable display device capable of variably displaying the identification information (also referred to as “fluctuation”) is provided, and when the display result of the variable display of the identification information in the variable display device becomes a specific display result, a predetermined game value Are configured to give the player.

  The game value is the right for the variable winning ball apparatus provided in the gaming area of the gaming machine to be in an advantageous state for a player who is easy to win a ball or in an advantageous state for a player. Or a condition where a condition for paying out a winning ball is easily established.

  In a pachinko machine, a specific display that is determined in advance as a display result of variable display of special symbols (identification information) that is started in the variable display device based on the winning of a game ball in the start winning opening (starting area) When the mode is derived and displayed, a “big hit” occurs. Note that the derivation display is to stop and display a symbol (excluding stop before so-called re-variation). When the big hit occurs, for example, the big winning opening is opened a predetermined number of times, and the game shifts to a big hit gaming state where the hit ball is easy to win. And in each open period, if there is a prize for a predetermined number (for example, 10) of the big prize opening, the big prize opening is closed. An opening time (for example, 29 seconds) is determined for each opening, and even if the number of winnings does not reach a predetermined number, the big winning opening is closed when the opening time elapses. Hereinafter, the opening period of each special winning opening may be referred to as a round.

  Such pachinko gaming machines or gaming machines such as slot machines are controlled by executing a program in a CPU or the like. Patent Document 1 discloses control using a CPU in a slot machine. The main control unit shown in FIG. 3 of Patent Document 1 is provided with interrupt input terminals (INT, MNI) for starting interrupt processing. By inputting a trigger signal to the trigger terminal, the basic process is interrupted and the interrupt process is started. When interrupt processing is not used, the interrupt input terminals (INT, MNI) are pulled up to the power supply (+ 5V), and even if noise occurs at the interrupt input terminals, an interrupt is generated. Is not misdetected.

JP 2011-189178 A

  In gaming machines such as pachinko machines and slot machines, many new models appear each year. Each gaming machine will be equipped with components such as a CPU that performs control. However, if a different configuration is used for each model, it may be possible to increase manufacturing costs and design efforts. Therefore, by sharing parts between different models, cost and labor are reduced. In addition, since the gaming machine is collected from the store in a relatively short period of time, it is possible to reduce the manufacturing cost by recycling the collected parts of the gaming machine.

  As described above, the versatility of parts is important for sharing parts among models and facilitating recycling. An object of the present invention is to improve versatility between different types of electronic devices having a plurality of input terminals such as a CPU in a gaming machine such as a pachinko gaming machine or a slot machine.

The gaming machine according to means A of the present invention is characterized by adopting the following configuration.
An electronic device including a first input terminal and a second input terminal;
The second input terminal is
It has an input function and an interrupt function and can be set to low active or high active.
When the interrupt function is used, it is set to low active.
When the input function is used, it is set to high active,
When it is an empty terminal, it is connected to the power line,
The first input terminal is connected to the ground when it is an empty terminal,
Setting means for setting the function of the second input terminal ;
Before Symbol electronic apparatus includes a plurality of said second input terminal,
The plurality of second input terminals are adjacent to each other.
The gaming machine according to the first means of the present invention (for example, the pachinko gaming machine 1 in FIG. 1) is characterized by adopting the following configuration.
Electronic device including a first input terminal (for example, terminals D0 to D7 and terminals PI0 to PI4 in FIG. 6) and a second input terminal (for example, terminal PI5 / XINT, terminal PI6 / XNMI, and terminal PI7 / RX0 in FIG. 6). (For example, the CPU 56 of FIG. 6)
The second input terminal can be set to low active (for example, set to XINT at the terminal PI5 / XINT in FIG. 6) or high active (for example, set to PI5 at the terminal PI5 / XINT in FIG. 6). , When using a certain function, it is set to low active,
When the second input terminal is an empty terminal, the second input terminal is connected to a power supply line (for example, the predetermined voltage Vcc in FIG. 6),
When the first input terminal is an empty terminal, the first input terminal is connected to a ground (for example, the ground G in FIG. 6).

  According to the gaming machine according to the first means of the present invention, an electronic device having a plurality of input terminals is characterized in that a second input terminal that can use different functions is provided. With such a configuration, when the electronic device is used in the model A, it is set to be active high, and when the electronic device is used in the model B, it is set to be low active to use a predetermined function. It is possible to improve versatility between models with a small number of input terminals. In addition, since the number of input terminals can be reduced, the electronic device can be downsized. In addition, when the second input terminal is not used, the terminal is connected to a relatively stable power line, so that even if a predetermined function is mistakenly set to the second input terminal that is not used, the second input terminal is inadvertently specified. Execution of the function is suppressed.

Furthermore, the gaming machine according to the second means of the present invention is the gaming machine according to the first means,
A plurality of the second input terminals (for example, terminal PI5 / XINT, terminal PI6 / XNMI, terminal PI7 / RX0 in FIG. 6) are provided, and the plurality of second input terminals are adjacent to each other.

  According to the gaming machine according to the second means of the present invention, in the case where a plurality of second input terminals are provided, the second input terminals that are vacant terminals are gathered together by bringing the second input terminals adjacent to each other in the electronic device. It becomes possible to connect to. Therefore, it is possible to simplify the wiring layout of the board on which the electronic device is installed. As a result, the reference potential can be stabilized by adopting a layout that allows a large solid area of the ground (ground electrode) of the board. It is possible to improve resistance to external noise.

Furthermore, the gaming machine according to the third means of the present invention is the gaming machine according to the first or second means,
The electronic device is a CPU (for example, a CPU 56 in FIG. 6).

  According to the gaming machine according to the third means of the present invention, it is advantageous in reducing the cost and suppressing the design effort by giving the general-purpose to a relatively expensive CPU among the components in the gaming machine. .

Furthermore, the gaming machine according to the fourth means of the present invention is the gaming machine according to any one of the first to third means,
The predetermined function is an interrupt process.

  According to the gaming machine of the fourth means of the present invention, by connecting the second input terminal, which is an empty terminal, to a relatively stable power line, interrupt processing that also causes malfunction of the gaming machine is eliminated. It is suppressed that it is executed in advance.

Furthermore, the gaming machine according to the fifth means of the present invention is the gaming machine according to any one of the first to third means,
A plurality of the second input terminals are provided, and a predetermined function of each of the second input terminals is a different interrupt process.

  According to the gaming machine of the fifth means of the present invention, by setting different interrupt processing for the plurality of second input terminals, each second input terminal has a different function, and the electronic device It is possible to improve the general versatility.

Front view of pachinko machine Front view showing the front of the game board with the glass door frame removed Rear view of the pachinko machine from the back Block diagram showing a circuit configuration example of a game control board (main board) Block diagram showing a circuit configuration example of the payout control board Block diagram showing an example of the configuration around the CPU Explanatory diagram showing input terminal assignment The flowchart which shows the main process which CPU in the main board performs Flow chart showing 2ms timer interrupt processing

  Hereinafter, an embodiment of the present invention will be described with reference to the drawings. First, the overall configuration of a pachinko gaming machine that is an example of a gaming machine will be described. FIG. 1 is a front view of a pachinko gaming machine as viewed from the front, and FIG. 2 is a front view showing the front of the game board. In the following embodiments, a pachinko gaming machine will be described as an example. However, the gaming machine according to the present invention is not limited to a pachinko gaming machine, and can be applied to, for example, an image-type gaming machine or a slot machine.

  The pachinko gaming machine 1 includes an outer frame (not shown) formed in a vertically long rectangular shape, and a game frame attached to the inside of the outer frame so as to be opened and closed. Further, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape that is provided in the game frame so as to be opened and closed. The game frame includes a front frame (not shown) installed to be openable and closable with respect to the outer frame, a mechanism plate to which mechanism parts and the like are attached, and various parts attached to them (excluding a game board described later). And a structure including:

  As shown in FIG. 1, the pachinko gaming machine 1 has a glass door frame 2 formed in a frame shape. On the lower surface of the glass door frame 2 is a hitting ball supply tray (upper plate) 3. Under the hitting ball supply tray 3, an extra ball receiving tray 4 for storing game balls that cannot be accommodated in the hit ball supply tray 3 and a hitting operation handle (operation knob) 5 for launching the game balls are provided. A game board 6 is detachably attached to the back surface of the glass door frame 2. The game board 6 is a structure including a plate-like body constituting the game board 6 and various components attached to the plate-like body. A game area 7 is formed on the front surface of the game board 6.

Near the center of the game area 7, there is provided a variable display device (special symbol display device) 9 including a plurality of variable display portions each variably displaying a symbol as identification information. The variable display device 9 has, for example, three variable display portions (symbol display areas) of “left”, “middle”, and “right”. In addition, the variable display device 9 is provided with four special symbol start memory display areas (start memory display areas) 18 for displaying the number of effective winning balls that have entered the start winning opening 14, that is, the start memory number. Every time there is a valid start prize, the start storage display area is changed by one (for example, the display color is changed from blue display to red display). Each time the variable display of the variable display device 9 is started, the start memory number display area where the display color is changed is reduced by 1 (that is, the display color is returned to the original). In this example, the symbol display area and the start memory display area are provided separately, so that the start memory number can be displayed even during variable display. The start memory display area may be provided in a part of the symbol display area. In this case, the start memory number display may be interrupted during variable display. In this example, the start memory display area is provided in the variable display device 9, but a display (special symbol start memory display) for displaying the start memory number is provided separately from the variable display device 9. It may be.

  Below the variable display device 9, a variable winning ball device 15 is provided as a start winning port 14. The winning ball that has entered the start winning opening 14 is guided to the back of the game board 6 and detected by the start opening switch 14a. A variable winning ball device 15 that opens and closes is provided below the start winning opening 14. The variable winning ball device 15 is opened by a solenoid 16.

  An open / close plate 20 that is opened by a solenoid 21 in a specific gaming state (big hit state) is provided below the variable winning ball device 15. The opening / closing plate 20 is a means for opening and closing the special winning opening. Of the winning balls guided from the opening / closing plate 20 to the back of the game board 6, the winning ball entering one (V winning area) is detected by the V winning switch 22, and the winning ball from the opening / closing plate 20 is detected by the count switch 23. Is done. On the back of the game board 6, a solenoid 21A for switching the route in the special winning opening is also provided.

  When a game ball wins the gate 32 and is detected by the gate switch 32a, the variable display of the normal symbol display 10 is started. In this embodiment, variable display is performed by alternately lighting the left and right lamps (a symbol can be visually recognized when the lamp is lit). For example, if the right lamp is lit when the variable display ends, it is a win. When the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined number of times. In the vicinity of the normal symbol display 10, a normal symbol start memory display 41 having a display unit with four LEDs for displaying the number of winning balls entered into the gate 32 is provided. Each time there is a prize at the gate 32, the normal symbol start memory display 41 increases the number of LEDs to be turned on by one. Each time variable display on the normal symbol display 10 is started, the number of LEDs to be lit is reduced by one.

  The gaming board 6 is provided with a plurality of winning holes 29, 30, 33, 39, and winning of the game balls to the winning holes 29, 30, 33 is detected by winning hole switches 29a, 30a, 33a, 39a, respectively. The Each winning opening 29, 30, 33, 39 constitutes a winning area provided in the game board 6 as an area for accepting game media and allowing winning. The start winning port 14 that accepts game media and allows winnings, and the big winning port also constitute a winning area. Around the left and right of the game area 7, there are provided decorative lamps 25 blinking and displayed during the game, and at the lower part there is an outlet 26 for absorbing a game ball that has not won a prize. Two speakers 27 that emit sound effects are provided on the left and right upper portions outside the game area 7. On the outer periphery of the game area 7, a top frame lamp 28a, a left frame lamp 28b, and a right frame lamp 28c are provided. Further, a decoration LED is installed around each structure (such as a big prize opening) in the game area 7. The top frame lamp 28a, the left frame lamp 28b, the right frame lamp 28c, and the decoration LED are examples of a decorative light emitter provided in the gaming machine.

  In this example, a prize ball lamp 51 that is turned on when there is a remaining number of prize balls is provided in the vicinity of the left frame lamp 28b, and a ball that is turned on in the vicinity of the top frame lamp 28a when the supply ball is cut. A cut lamp 52 is provided. As described above, the pachinko gaming machine 1 of this embodiment is provided with lamps and LEDs as light emitters in various places. Further, FIG. 1 also shows a card unit 50 that is installed adjacent to the pachinko gaming machine 1 and enables lending of a ball by inserting a prepaid card.

  The card unit 50 includes a use indicator lamp 151 that indicates whether or not the card unit 50 is in a usable state, a connection table direction indicator 153 that indicates which side of the pachinko gaming machine 1 corresponds to the card unit 50, a card A card insertion indicator lamp 154 indicating that a card is inserted into the unit 50, a card insertion slot 155 into which a card as a recording medium is inserted, and a card reader / writer mechanism provided on the back surface of the card insertion slot 155 A card unit lock 156 is provided for releasing the card unit 50 when checking the card.

  The game balls launched from the hit ball launching device enter the game area 7 through the hit ball rail, and then descend the game area 7. When the game ball enters the start winning opening 14 and is detected by the start opening switch 14a, the special symbol starts variable display (variation) in the variable display device 9 if the variable display of the symbol can be started. If the variable display of the symbol cannot be started, the start memory number is increased by one.

  The variable display of the special symbol on the variable display device 9 stops when a certain time has elapsed. If the combination of special symbols at the time of stoppage is a jackpot symbol (specific display result), the game shifts to a jackpot gaming state. That is, the opening / closing plate 20 is opened until a predetermined time elapses or a predetermined number (for example, 10) of game balls wins. When the game ball wins the V winning area while the opening / closing plate 20 is opened and is detected by the V winning switch 22, a continuation right is generated and the opening / closing plate 20 is opened again. The generation of the continuation right is allowed a predetermined number of times (for example, 15 rounds). The continuation right may be eliminated without providing the V prize ball switch 22, and only a predetermined number of times (for example, 15 rounds) may be allowed.

  When the combination of special symbols in the variable display device 9 at the time of stopping is a combination of jackpot symbols (probability variation symbols) with probability fluctuations, the probability of the next jackpot increases. That is, it becomes a more advantageous state for the player in the probability variation state.

  When the game ball wins the gate 32, the normal symbol display unit 10 is in a state where the normal symbol is variably displayed. Further, when the stop symbol on the normal symbol display 10 is a predetermined symbol (winning symbol), the variable winning ball device 15 is opened for a predetermined time. Further, in the probability variation state, the probability that the stop symbol in the normal symbol display 10 becomes a winning symbol is increased, and the opening time and the number of times of opening of the variable winning ball device 15 are increased. That is, the opening time and the number of times of opening of the variable winning ball device 15 can be increased when the stop symbol of the normal symbol is a winning symbol or the stop symbol of the special symbol is a probabilistic symbol. Change to an advantageous state. It should be noted that increasing the number of times of opening is a concept including changing from a closed state to an open state.

  Next, the structure of the back surface of the pachinko gaming machine 1 will be described with reference to FIG. FIG. 3 is a rear view of the gaming machine as seen from the back side.

  As shown in FIG. 3, on the back side of the gaming machine, a game in which a variable display control unit 49 including an effect control board 80 on which an effect control means for controlling the variable display device 9 is mounted, a game control microcomputer, and the like are mounted. A control board (main board) 31 is installed. In addition, a payout control board 37 on which a payout control microcomputer for performing ball payout control is mounted is installed. The effect control means includes various decoration LEDs provided on the game board 6, the normal symbol start memory display 41, the decoration lamp 25, the top frame lamp 28a provided on the frame side, the left frame lamp 28b, and the right frame. The lamp 28c, the prize ball lamp 51 and the ball-out lamp 52 are controlled to be turned on, and the sound generation from the speaker 27 is controlled.

  Further, a power supply board 910 and a launch control board 91 on which a power supply circuit for creating DC30V, DC21V, DC12V, and DC5V is mounted are provided. Although most of the power supply substrate 910 overlaps with the main substrate 31, there is an exposed portion that is exposed so as to be visible from the outside without overlapping the main substrate 31. In this exposed portion, power is supplied to each electrical component control board (main board 31, production control board 80, payout control board 37) of the pachinko gaming machine 1 and each electrical component provided in the pachinko gaming machine 1. Alternatively, a power switch 914 as a power supply permission means for cutting off, and a backup RAM included in the main board 31 (variable data that can retain stored contents for a predetermined period even when power supply to the gaming machine is stopped) A clear switch 921 is provided as an operation means for clearing the backup data stored in the storage means).

  On the back side of the gaming machine, a terminal board 160 provided with terminals for outputting various information to the outside of the gaming machine is installed above. The terminal board 160 has at least a ball break terminal for introducing and outputting an output of the ball break detection switch, an award ball terminal for outputting the award ball number signal to the outside, and a ball lending number signal externally output. A ball lending terminal is provided. In addition, an information terminal board (information output board) 34 provided with terminals for outputting various information from the main board 31 to the outside of the gaming machine is installed near the center.

  The game balls stored in the storage tank 38 pass through the guide rails, reach the ball payout device covered with the prize ball case 40A through the curve rod. A ball break switch 187 as a game medium break detection means is provided on the upper part of the ball payout device. When the ball break switch 187 detects a ball break, the dispensing operation of the ball dispensing device stops. The ball break switch 187 is a switch for detecting the presence or absence of a game ball in the game ball passage, but the ball break detection switch 167 for detecting the shortage of supply balls in the storage tank 38 is also an upstream portion of the guide rail (in the storage tank 38). (Proximate part). When the ball break detection switch 167 detects the shortage of game balls, the game machine is replenished to the game machine from the supply mechanism provided on the gaming machine installation island.

  When a lot of game balls as prizes based on winning prizes and game balls based on ball lending requests are paid out, the batting supply tray 3 is full, and when game balls are further paid out, the game balls pass through the surplus ball passage and surplus balls. Guided to the tray 4. Further, when the game ball is paid out, the sensing lever presses the full tank switch as the storage state detection means, and the full tank switch as the storage state detection means is turned on. In this state, the rotation of the payout motor in the ball payout device stops, the operation of the ball payout device stops, and the drive of the launching device also stops.

  FIG. 4 is a block diagram illustrating an example of a circuit configuration in the main board 31. FIG. 4 also shows a payout control board 37 equipped with payout control means and an effect control board 80 equipped with effect control means. The main board 31 includes a basic circuit 53 for controlling the pachinko gaming machine 1 according to a program, a gate switch 32a, a start port switch 14a, a V winning switch 22, a count switch 23, winning port switches 29a, 30a, 33a, 39a, and Basically, a switch circuit 58 that gives a signal from the clear switch 921 to the basic circuit 53, a solenoid 16 that opens and closes the variable winning ball apparatus 15, a solenoid 21 that opens and closes the opening and closing plate 20, and a solenoid 21A that switches the path in the special winning opening. A solenoid circuit 59 that is driven in accordance with a command from the circuit 53 is mounted.

  Although not shown in FIG. 4, the count switch short circuit signal is also transmitted to the basic circuit 53 via the switch circuit 58. Further, the gate switch 32a, the start port switch 14a, the V winning switch 22, the count switch 23, the winning port switches 29a, 30a, 33a, 39a, and other switches may be referred to as sensors. That is, the name of the game medium detection means is not limited as long as it is a game medium detection means (game ball detection means in this example) that can detect a game ball.

  Further, according to the data given from the basic circuit 53, the jackpot information indicating the occurrence of the jackpot, the effective starting information indicating the number of starting winning balls used for starting the variable display of the symbols in the variable display device 9, the probability variation has occurred. An information output circuit 64 for outputting an information output signal such as probability variation information indicating the above to an external device such as a hall computer is mounted.

  The basic circuit 53 includes a ROM 54 for storing a game control program and the like, a RAM 55 as storage means (means for storing variation data) used as a work memory, a CPU 56 for performing control operations according to the program, and an I / O port unit 57. including. In this embodiment, the ROM 54 and RAM 55 are built in the CPU 56. That is, the CPU 56 is a one-chip microcomputer. The one-chip microcomputer only needs to have at least the RAM 55 built in, and the ROM 54 and the I / O port unit 57 may be externally attached or built in. Since the CPU 56 executes control according to the program stored in the ROM 54, the CPU 56 executes (or performs processing) hereinafter, specifically, the CPU 56 executes control according to the program. is there. The same applies to CPUs mounted on substrates other than the main substrate 31.

  A RAM 55 (may be a CPU built-in RAM) 55 is a backup RAM that is partially or entirely backed up by a backup power source created in the power supply substrate 910. That is, even if the power supply to the gaming machine is stopped, a part or all of the contents of the RAM 55 is saved for a predetermined period.

  The main board 31 is supplied with the VSL voltage (DC + 30V) from the power supply board 910 and becomes low level (reset level) when the VSL voltage is lower than the predetermined potential, and high level when the VSL voltage is higher than the predetermined potential. A reset circuit 65 for generating a reset signal is mounted. The reset signal is input to the reset terminal of the CPU 56.

  A power supply monitoring circuit 920 is mounted on the main board 31. The power supply monitoring circuit 920 detects the occurrence of power supply stoppage to the gaming machine by introducing the VSL voltage (DC + 30V) from the power supply board 910 and monitoring the VSL voltage. Specifically, when the VSL voltage becomes equal to or lower than a predetermined value (+22 V in this example), a power cut-off signal (power supply stop signal, that is, a detection signal from the power supply monitoring means) is output as a power supply stop occurs (specifically In fact, set it to low level.) The power-off signal is input to the input port. When the power-off signal is input to the input port, the CPU 56 executes a power supply stop process. In the power supply stop process, necessary information (information necessary for continuing the game process from the power supply stop state when the power supply is restored) is stored in the backup RAM (for example, parity data). Execute the setting process. In addition, a flag indicating that the power supply stop process has been performed is set.

  The input of a power-off signal (detection signal from the power monitoring means) to the input port means that the level of the power-off signal has reached a level indicating power-off. The state at the level shown is the state where the detection signal is released.

A ball hitting device for hitting and launching a game ball is driven by a drive motor 94 controlled by a circuit on the launch control board 91. Then, the driving force of the drive motor 94 is adjusted according to the operation amount of the operation knob 5. That is, the circuit on the launch control board 91 is controlled so that the game ball is launched at a speed corresponding to the operation amount of the operation knob 5.

  In this embodiment, the effect control means mounted on the effect control board 80 controls the display of the normal symbol start memory display 41 and the decoration lamp 25 provided on the game board, and on the frame side. Display control of the provided top frame lamp 28a, left frame lamp 28b, and right frame lamp 28c is performed. The effect control means mounted on the effect control board 80 also performs display control of the variable display device 9 that variably displays special symbols and the normal symbol display 10 that variably displays normal symbols.

  FIG. 5 is a block diagram showing components related to payout, such as components of the payout control board 37 and the ball payout device 97. As shown in FIG. 5, the detection signal from the full switch 48 is input to the input port 372 b of the payout control board 37 via the relay board 72. A detection signal from the ball break switch 187 is also input to the input port 372 b of the payout control board 37 via the relay board 72. A detection signal from the payout count switch 301 is input to the input port 372 b of the payout control board 37 via the relay board 72. The payout count switch 301 detects a game ball actually paid out from the ball payout device 97.

  The payout control CPU 371 of the payout control board 37 pays off the ball when the detection signal from the ball break switch 187 indicates a ball shortage state or when the detection signal from the full tank switch 48 indicates a full tank state. Stop processing.

  When there is a win, the output circuit 67 of the main board 31 outputs, as a payout command signal, a REQ signal (prize ball request signal) for making a payout request for a prize ball and a payout number signal indicating the number of prize balls to be paid out. Is done. The payout number signal is composed of 4-bit data and is output by four signal lines. The payout number signal is input to the I / O port 372a via the input circuit 373A. When a REQ signal and a payout number signal are input via the I / O port 372a, the payout control CPU 371 controls to drive the ball payout device 97 to pay out the number of game balls indicated by the payout number signal. A power supply confirmation signal is also output from the output circuit 67 of the main board 31.

  Also, when the payout control board 37 is executing the payout process of the winning ball, a BUSY signal (indicating that the payout process is being output to the main board 31 via the output circuit 373B of the payout control board 37). The winning ball payout signal) is input. Further, the payout control CPU 371 outputs a payout prohibition signal to the main board 31 in the payout prohibition state. In this embodiment, the payout control CPU 371 is a one-chip microcomputer and incorporates at least a RAM.

  The payout control CPU 371 receives a prize ball information signal indicating the number of prize balls to be paid out and a ball lending number signal indicating the number of balls to be rented via the output port 372c as terminal boards (frame external terminal boards and board external terminal boards). Output) 160. A driver circuit is provided outside the output port 372c, but is not shown in FIG. A door opening information switch 161 is connected to the terminal board 160 (frame external terminal board).

  The payout control CPU 371 outputs an error signal to the error display LED 374 via the input / output port 372d. Further, a signal for instructing lighting / extinguishing of the lamp is output to the winning ball lamp 51 and the ball-out lamp 52 via the output port 372f. A detection signal from an error release switch 375 for releasing the error state is input to the input / output port 372d of the payout control board 37. The error cancel switch 375 is used to cancel the error state by software reset.

  Further, a detection signal from a payout motor position sensor for detecting the rotational position of the payout motor 289 is input to the input port 372 b of the payout control board 37 via the relay board 72. A drive signal from the payout control board 37 to the payout motor 289 is transmitted to the payout motor 289 in the payout mechanism portion of the ball payout device 97 via the output port 372c and the relay board 72. A driver circuit (motor drive circuit) is installed outside the output port 372c, but is not shown in FIG.

  The card unit 50 is equipped with a card unit control microcomputer. In addition, the card unit 50 is provided with a usable display lamp 151, a connecting table direction indicator 153, a card insertion display lamp 154, and a card insertion slot 155 (see FIG. 1). The interface board 66 is connected to a frequency display LED 60, a ball lending LED 61, a ball lending switch 62 and a return switch 63 provided in the vicinity of the hitting ball supply tray 3.

  A card lending switch signal indicating that the ball lending switch 62 has been operated and a return switch signal indicating that the return switch 63 has been operated are provided to the card unit 50 from the interface board 66 in accordance with the player's operation. . Further, a card balance display signal indicating a prepaid card balance and a ball lending display signal are given from the card unit 50 to the interface board 66. Between the card unit 50 and the payout control board 37, a connection signal (VL signal), a unit operation signal (BRDY signal), a ball lending request signal (BRQ signal), a ball lending completion signal (EXS signal) and a pachinko machine operation signal ( PRDY signal) is exchanged via the input port 372g and the output port 372e. An interface board 66 is interposed between the card unit 50 and the payout control board 37. Therefore, a signal such as a connection signal (VL signal) is exchanged between the card unit 50 and the payout control board 37 via the interface board 66 as shown in FIG.

  When the power of the pachinko gaming machine 1 is turned on, the payout control CPU 371 of the payout control board 37 outputs a PRDY signal to the card unit 50. The card unit control microcomputer outputs a VL signal. The payout control CPU 371 determines the connected / unconnected state based on the input state of the VL signal. When a card is received in the card unit 50, the ball lending switch is operated and a ball lending switch signal is input, the card unit control microcomputer outputs a BRDY signal to the payout control board 37. When a predetermined delay time elapses from this point, the card unit control microcomputer outputs a BRQ signal to the payout control board 37.

  Then, the payout control CPU 371 of the payout control board 37 raises the EXS signal to the card unit 50, and when detecting the fall of the BRQ signal from the card unit 50, drives the payout motor 289 to draw a predetermined number of rental balls. Pay to the player. When the payout is completed, the payout control CPU 371 causes the EXS signal to the card unit 50 to fall. Thereafter, if the BRDY signal from the card unit 50 is not on, prize ball payout control is executed. The power supply voltage AC24V used in the card unit 50 is supplied from the payout control board 37.

  The power supply from the power supply board 910 to the card unit 50 is performed via the payout control board 37 and the interface board 66. In this example, a fuse for protecting the card unit 50 is provided in the AC 24V power supply line for the card unit 50 arranged in the interface board 66 so that a voltage higher than a predetermined voltage is not supplied to the card unit 50. I have to.

  In this embodiment, the case where the card unit 50 is installed adjacent to the gaming machine as a separate body from the gaming machine is taken as an example, but the card unit 50 may be integrated with the gaming machine. . Further, the present invention can be applied even in the case where game balls corresponding to the amount of money are lent out in accordance with coin insertion.

  FIG. 6 is a block diagram illustrating a configuration example around the CPU 56 in the main board 31. The CPU 56 of this embodiment includes terminals D0 to D7, terminals PI0 to PI4, terminal PI5 / XINT, terminal PI6 / XNMI, and terminal PI7 / RX0 as input terminals. Also, PI0 to PI7 are provided as output terminals. In addition, a terminal VBB, a terminal VDD, and a terminal VSS are provided as terminals around the power source.

  The input terminal of the CPU 56 is divided into two types, a first input terminal and a second input terminal. The first input terminals (terminals D0 to D7 and PI0 to PI4) are terminals that can be used with only one function (input function). On the other hand, the second input terminal (terminal PI5 / XINT, terminal PI6 / XNMI, terminal PI7 / RX0) is a terminal having an input function, an interrupt input function, and two functions. This is a terminal that can be used for functions. In the present embodiment, among the three second input terminals (terminal PI5 / XINT, terminal PI6 / XNMI, terminal PI7 / RX0), PI5, PI6, and PI7 included in the terminal names indicate the first function (input function). , XINT, XNMI, and RXO indicate the second function (interrupt input function).

  As described above, by providing the second input terminal with a plurality of functions, the versatility of the CPU 56 is improved between different models of gaming machines. In this embodiment, all the second input terminals are not used, but, for example, when the same CPU 56 is used in another model A, the second input terminal is set to the input function and used. When using the same CPU 56 in the model B, it can be considered that the second input terminal is set to the interrupt input function. In addition, the CPU 56 of the present embodiment includes a plurality of second input terminals, and a different interrupt input function can be set for each second input terminal, so that the versatility is improved.

  Here, the input function is a function for transmitting signals from various external winning switches and the like to the CPU 56, and the interrupt input function is a predetermined interrupt process (with the CPU 56 triggered by an input to the input terminal ( This is a function for starting normal interrupt processing (maskable interrupt processing) or non-maskable interrupt processing). Normal interrupt processing can be prohibited (masked), but non-maskable interrupt processing cannot be prohibited. In the present embodiment, among the second input terminals, the terminal PI5 / XINT is for normal interrupt processing, and the terminals PI6 / XNMI and PI7 / RX0 are for non-maskable interrupt processing. When the interrupt processing is set to be valid in the CPU 56, the interrupt processing (normal interrupt processing or non-maskable interrupt processing) is performed when the signal input to the second input terminal falls to a low level. Start. That is, the program counter of the CPU 56 is changed to the start address of normal interrupt processing or non-maskable interrupt processing, and the CPU 56 enters a state of executing the instruction set at the start address. Note that the second function (interrupt input function) that can be set in the three second input terminals (terminal PI5 / XINT, terminal PI6 / XNMI, and terminal PI7 / RX0) can be different. That is, it is possible to set different start addresses for non-maskable interrupt processing or normal interrupt processing (maskable interrupt processing) to each second input terminal.

  In the pachinko gaming machine 1 of this embodiment, the terminals D0 to D7 and the terminals PI0 to PI2 of the CPU 56 are used, and the terminals PI3 to PI4, the terminals PI5 / XINT, the terminals PI6 / XNMI, and the terminals PI7 / RX0 are not used. Yes. Various signals from the outside are input to the terminals D0 to D7 and the terminals PI0 to PI2 to be used via the input port 572. On the other hand, the unused terminals PI5 / XINT, terminal PI6 / XNMI, and terminal PI7 / RX0 are connected to the ground G or a predetermined voltage Vcc (5 V) depending on the type.

  Here, input terminals (empty input terminals) that are not used in the pachinko gaming machine 1 are classified into two types. One is a first input terminal (terminals PI3 and PI4) having only one function (input function), and the other is a second input terminal having two functions (input function and interrupt input function). (Terminal PI5 / XINT, terminal PI6 / XNMI, terminal PI7 / RX0). In the present embodiment, among the unused input terminals, the first input terminal is grounded to the ground G, and the second input terminal is connected to the predetermined voltage Vcc (5 V). This is intended to suppress the influence of noise at the empty input terminal.

  The first input terminal is set to high active. When the input terminal is at a low voltage (low state), the external input is not detected, and when the input terminal is at a high voltage (high state), the external input Detect that there was input from. Although the first input terminal can be set to low active, when it is made high active, the first input terminal that is not used (is used as an empty terminal) is connected to the ground G, so that the solid area of the ground G on the substrate (The area occupied by the conductive portion of the ground G on the substrate) can be increased, and the potential of the ground G can be stabilized. On the other hand, as described above, the second input terminal can be set to two functions (input function, interrupt input function), and when set to the first function (input function), the first input terminal Like, it is used by setting it to high active. In addition, when setting to a 1st function (input function), it is good also as a form set to low active. On the other hand, when the second function (interrupt input function) is set, when the input terminal is at a high voltage (high state), the external interrupt input is not detected and the input terminal is at a low voltage (low state). In this case, it is used by setting it to low active to detect the presence of an external interrupt input.

  In the present embodiment, among the empty input terminals, the first input terminals (terminals PI3 and PI4) are high active, and therefore are connected to the ground G (0 V) which is in a low state and no input signal is generated. Yes. On the other hand, the second input terminal (terminal PI5 / XINT, terminal PI6 / XNMI, terminal PI7 / RX0), which is an empty terminal, is connected to the predetermined voltage Vcc (5V) that goes to the high state, thereby generating an interrupt input signal. Not in a state. When the second input terminal is not used and is not used in the same manner as the first input terminal, it is preferable to connect to the ground G in order to increase the solid area of the ground G. However, since the second input terminal of this embodiment can set the second function (interrupt input function), even if the CPU 56 is erroneously set to the second function, the interrupt processing The second input terminal is connected to a predetermined voltage Vcc that is in a high state so as not to start inadvertently. In particular, the CPU 56 of the present embodiment includes an interrupt input function for starting a non-maskable interrupt process that cannot be prohibited, so that the second input that is vacant in terms of preventing malfunctions. It is effective to set the pin to the high state.

  The input terminals of the CPU 56 are arranged in the order shown in the block diagram of FIG. 6 even in an actual chip. In particular, the first input terminals (terminals D0 to D7, terminals PI0 to PI4) and the second input terminals (terminal PI5 / XINT, terminal PI6 / XNMI, terminal PI7 / RX0) are arranged together for each type. Therefore, the first input terminals not used (PI3 and PI4 in this example) can be collectively grounded to the ground G, and the solid area of the ground G on the board on which the CPU 56 is mounted (conduction of the ground G on the board). It is possible to achieve a layout with a wide area). Thus, by securing a wide solid area of the ground G, it is possible to stabilize the reference potential and improve resistance to external noise. In addition, since the second input terminals not used (in this example, the terminal PI5 / XINT, the terminal PI6 / XNMI, and the terminal PI7 / RX0) can be collectively connected to Vcc, a wiring layout for supplying Vcc is used. Can be simplified. Simplifying the wiring layout for supplying Vcc also leads to an increase in the solid area of the ground G.

  The output terminals (PD0 to PD7) of the CPU 56 output the processing result to the outside via the output port 573. In the CPU 56, the terminal VBB and the terminal VDD are terminals around the power supply, the terminal VBB is connected to a backup power supply, the terminal VDD is connected to a predetermined voltage Vcc (5V), and VSS is connected to the ground G. It is connected.

  As described with reference to FIG. 4, the power-off signal from the power supply monitoring circuit (power supply monitoring means; first power supply monitoring means) 920 is input to the terminal PI0 of the CPU 56 via the inverting circuit 943 and the input port 572. Therefore, the CPU 56 can confirm the occurrence of the stop of the power supply to the gaming machine by monitoring the terminal PI0 of the input port 572.

  The power monitoring circuit 920 includes a power monitoring IC 902. The power monitoring IC 902 detects the occurrence of power supply stoppage to the gaming machine by introducing the VSL voltage and monitoring the VSL voltage. Specifically, when the VSL voltage becomes equal to or lower than a predetermined value (+22 V in this example), a power-off signal is output because the power supply is stopped. The power supply voltage to be monitored is preferably higher than the power supply voltage (+5 V in this example) of the circuit element mounted on each electric component control board. In this example, VSL, which is a voltage immediately after being converted from AC to DC, is used.

  The predetermined value for the power monitoring IC 902 to detect the stop of power supply is lower than the normal voltage, but is a voltage that allows the CPU 56 to operate for a while. In addition, since the power monitoring IC 902 is higher than the voltage for driving circuit elements such as the CPU 56 (+5 V in this example), the monitoring range can be expanded with respect to the voltage required by the CPU. Therefore, more precise monitoring can be performed. Furthermore, when VSL (+ 30V) is used as the monitoring voltage, the voltage supplied to the various switches of the gaming machine is + 12V, so that it can be expected to prevent erroneous switch-on detection at the time of instantaneous power interruption. That is, when the voltage of the + 30V power supply is monitored, it is possible to detect a decrease in the level before + 12V created after the creation of + 30V starts to drop.

  When the voltage of the + 12V power supply decreases, the switch output becomes on. However, if the power supply voltage is monitored by monitoring the + 30V power supply voltage, which decreases faster than + 12V, and the power supply is stopped, the switch output is turned on. It is possible to enter a supply recovery waiting state and not detect the switch output.

  The reset circuit 65 includes a reset IC 651. When the power is turned on, the reset IC 651 sets the output to a low level for a predetermined time determined by the capacity of the external capacitor, and sets the output to a high level when the predetermined time has elapsed. That is, the reset signal (system reset signal) is raised to a high level to make the CPU 56 operable. The reset signal is input to the reset terminal (RESET) of the CPU 56 through the inverting circuits 942 and 941.

  The reset IC 651 monitors the power supply voltage of the VSL, which is the power supply voltage that is the same as the power supply voltage monitored by the power supply monitoring circuit 920, and the voltage value is a predetermined value (than the power supply voltage value at which the power supply monitoring circuit outputs a power-off signal). When the value is less than (low value), the output is set to low level. Therefore, the CPU 56 performs a predetermined power supply stop process in response to the power-off signal from the power supply monitoring circuit 920, and then the system is reset. That is, the operation is completely stopped. Accordingly, the reset circuit 65 corresponds to second power supply monitoring means for outputting the detection signal at a timing later than the timing at which the power supply monitoring means outputs the detection signal. In this example, the state in which the second power supply monitoring unit outputs the detection signal is a state in which the reset signal is set to a low level.

  FIG. 7 is an explanatory diagram showing input terminal assignment of the CPU 56 in the pachinko gaming machine 1 of the present embodiment. The assignment of input terminals in the CPU 56 is performed in a main process (described in detail later) that starts after the pachinko gaming machine 1 is activated. Although the same CPU 56 is used depending on the model of the pachinko gaming machine 1, the terminal to be used and the function to be used may be different. Such a case can be dealt with by changing the input terminal assignment according to the model of the pachinko gaming machine 1. The pachinko gaming machine 1 of this embodiment includes terminals D0 to D7, terminals PI0 to PI4, terminals PI5 / XINT, terminals PI6 / XNMI, and terminals PI7 / RX0 as described with reference to FIG. Among these, the terminals D0 to D7 and the terminals PI0 to PI4 are first input terminals T1 that are used only for one function (input function). The terminals PI5 / XINT, the terminals PI6 / XNMI, and the terminals PI7 / RX0 are 2 This is a second input terminal T2 having two functions (input function and interrupt input function).

  In the first input terminal T1, the terminals D0 to D7 and the terminals PI0 to PI2 are set to be connected to various switches. These first input terminals T1 detect an “on” state or a “power-off” state when the logic is “1” (high voltage state), and are when the logic is “0” (low voltage state). The high active state is set in which these states are not detected. On the other hand, among the first input terminals, unused terminals (terminals PI3 and PI4) are fixed to 0 (connected to the ground G), and there is no input signal.

  In the pachinko gaming machine 1 of the present embodiment, the second input terminal T2 of the CPU 56 is not used. When the second input terminal T2 is not used, it is connected to the predetermined voltage Vcc. The second input terminal T2 can be set to two functions (input function and interrupt input function) or unused based on the setting in the CPU 56 (set in the main process executed when the pachinko gaming machine 1 is started). Is possible. However, it is conceivable that a function (input function or interrupt input function) is set in the second input terminal T2 that is to be an empty terminal. In particular, when the interrupt input function is set by mistake, it is conceivable that the interrupt process is activated by noise or the like input to the second input terminal T2 that should be an empty terminal. If the interrupt process is inadvertently activated, the pachinko gaming machine 1 will not operate normally. In the present embodiment, the second input terminal T2, which should not be used, is connected to a high voltage (Vcc) that is in the interrupt processing OFF state, so that the interrupt input function is erroneously applied to the second input terminal T2. Even when is set, malfunction is prevented.

  Next, the operation of the gaming machine will be described. FIG. 8 is a flowchart showing a main process executed by game control means (CPU 56 and peripheral circuits such as ROM and RAM) in the main board 31. When power is turned on to the gaming machine and the input level of the reset terminal becomes high level, the CPU 56 starts main processing after step S1. In the main process, the CPU 56 first performs necessary initial settings.

  In the initial setting process, the CPU 56 first sets the interrupt prohibition (step S1). Next, the interrupt mode is set to interrupt mode 2 (step S2). The CPU 56 used in this embodiment is provided with the following three types of maskable (prohibitable) interrupt modes. When a maskable interrupt occurs, the CPU 56 automatically sets the interrupt disabled state and saves the contents of the program counter in the stack.

  Interrupt mode 0: The built-in device that has issued the interrupt request sends an RST instruction (1 byte) or a CALL instruction (3 bytes) onto the internal data bus of the CPU. Therefore, the CPU 56 executes the instruction at the address corresponding to the RST instruction or the address specified by the CALL instruction. At reset, the CPU 56 automatically enters interrupt mode 0. Therefore, when setting to interrupt mode 1 or interrupt mode 2, it is necessary to perform a process for setting to interrupt mode 1 or interrupt mode 2 in the initial setting process.

  Interrupt mode 1: In this mode, when an interrupt is accepted, the mode always jumps to address 0038 (h).

  Interrupt mode 2: A mode in which the address synthesized from the value (1 byte) of the specific register (I register) of the CPU 56 and the interrupt vector (1 byte: least significant bit 0) output by the built-in device indicates the interrupt address It is. That is, the interrupt address is an address indicated by 2 bytes in which the upper address is the value of the specific register and the lower address is the interrupt vector. Therefore, an interrupt process can be set at an arbitrary address (although it is skipped). Each built-in device has a function of sending an interrupt vector when making an interrupt request.

  Therefore, when the interrupt mode 2 is set, it becomes possible to easily process an interrupt request from each built-in device, and it is possible to install an interrupt process at an arbitrary position in the program. . Furthermore, unlike interrupt mode 1, it is also easy to prepare each interrupt process for each interrupt generation factor. As described above, in this embodiment, the CPU 56 is set to the interrupt mode 2 in step S2 of the initial setting process.

  After setting the interrupt mode 2, the CPU 56 sets a stack pointer designation address in the stack pointer (step S3). Then, the built-in device register is initialized (step S4). Further, after initialization of the CTC (timer / counter circuit) built in the CPU 56 and setting of the input terminal and output terminal (PIO: parallel input / output port) (step S5), the RAM is set to an accessible state. (Step S6).

  As described with reference to FIG. 6, the CPU 56 used in this embodiment has a plurality of input terminals and output terminals (both terminals are referred to as PIO). In step S4, the function of each input terminal and output terminal is set. As described above, since the second input terminal T2 can be set to different functions (input function and interrupt input function), it can be set according to the difference in the model of the pachinko gaming machine 1. is there. The PIO setting is performed by reading the setting for each terminal defined during the main process. The setting for each terminal is read from a storage unit in the CPU 56 or an external storage unit such as the ROM 54 or the RAM 55. In the examples of FIGS. 6 and 7, the second input terminal T2 is set as an unused empty terminal. In the present embodiment, when an input function is set to the second input terminal T2, it is set to high active that is logic “1”. Note that when an input function is set to the second input terminal T2, it may be set to low active which is a logic “0”. Further, when the interrupt input function is set to the second input terminal T2, it is set to low active which is a logic “0”. As described above, in the present embodiment, by preparing the second input terminal T2 that can be set to a plurality of functions, the number of input terminals is suppressed, and versatility among the types of the pachinko gaming machine 1 is enhanced. ing. At this time, when the second input terminal T2 is unused (empty terminal), the interrupt input function is not erroneously operated by connecting the second input terminal T2 to the predetermined voltage Vcc. Yes.

  Next, the CPU 56 checks the state of the output signal of the clear switch 921 input to the terminal PI2 via the input port 1 only once (step S7). When the on-state is detected in the confirmation, the CPU 56 executes normal initialization processing (steps S11 to S15). When the clear switch 921 is on (when pressed), a high-level clear switch signal is output to the terminal PI2 of the input port 572. By starting the power supply to the pachinko gaming machine 1 (for example, turning on the power switch) while the clear switch 921 is turned on by an operation of a game clerk or the like, the initialization process can be easily executed. That is, RAM clear or the like can be performed.

  If the clear switch 921 is not in the on state, the data protection process of the backup RAM area (for example, the process at the time of power supply stop such as addition of parity data) is performed when the power supply to the pachinko gaming machine 1 was stopped last time. It is confirmed whether or not it has been received (step S8). In this embodiment, when power supply is stopped, a process for protecting data in the backup RAM area is performed. When such protection processing is performed, it is assumed that there is a backup. When it is confirmed that such protection processing is not performed, the CPU 56 executes initialization processing.

  In this embodiment, whether or not there is backup data in the backup RAM area is confirmed by the state of the backup flag set in the backup RAM area in the power supply stop process. For example, if “55H” is set in the backup flag area, it means that there is a backup (ON state), and if a value other than “55H” is set, it means that there is no backup (OFF state).

  After confirming that there is a backup, the CPU 56 performs a data check of the backup RAM area (parity check in this example) (step S9). In this embodiment, clear data (00) is set in the checksum data area, and the checksum calculation start address is set in the pointer. Also, the number of checksum calculations corresponding to the number of data to be checksum is set. Then, the exclusive OR of the contents of the checksum data area and the contents of the RAM area pointed to by the pointer is calculated. The calculation result is stored in the checksum data area, the pointer value is incremented by 1, and the checksum calculation count value is decremented by 1. The above processing is repeated until the value of the checksum calculation count becomes zero. When the value of the checksum calculation count reaches 0, the CPU 56 inverts the value of each bit of the contents of the checksum data area and uses the inverted data as the checksum.

  In the power supply stop process, a checksum is calculated by the same process as described above, and the checksum is stored in the backup RAM area. In step S9, the calculated checksum is compared with the stored checksum. When the power supply is stopped after an unexpected power failure or the like, the data in the backup RAM area should be saved, so the check result (comparison result) is normal (matched). That the check result is not normal means that the data in the backup RAM area is different from the data when the power supply is stopped. In such a case, since the internal state cannot be returned to the state when the power supply is stopped, an initialization process that is executed when the power is turned on is not performed when the power supply is stopped.

  If the check result is normal, the CPU 56 performs a game state recovery process for returning the internal state of the game control means to the state when the power supply is stopped (step S10). Then, the saved value of the PC (program counter) stored in the backup RAM area is set in the PC, and the address is restored.

  In the initialization process (steps S11 to S15), the CPU 56 first performs a RAM clear process for clearing the entire area of the RAM (step S11). Note that the entire area of the RAM may not be initialized, and predetermined data (for example, count value data of a counter for generating a big hit determination random number) may be left as it is. For example, if the count value data of the counter for generating the big hit determination random number is left as it is, the big hit determination random number is generated even if the initialization process is executed by unauthorized means. Therefore, it is difficult to aim at the timing at which the count value of the counter matches the jackpot determination value. In addition, a predetermined work area (for example, a normal symbol determination random number counter, a normal symbol determination buffer, a special symbol left middle right symbol buffer, a total winning ball number storage buffer, a special symbol process flag, a winning ball flag, a ball running flag Then, a work area setting process for setting an initial value to a flag for selectively performing processing according to the control state such as a payout stop flag is performed (step S12).

  Further, the CPU 56 executes a process of transmitting an initialization command for initializing the effect control board 80 to the effect control board 80 (step S14). Examples of the initialization command include a command indicating an initial symbol displayed on the variable display device 9.

  Then, the CTC3 register provided in the CPU 56 is set so that a timer interrupt is periodically generated every 2 ms (step S15). That is, a value corresponding to 2 ms is set in a predetermined register (time constant register) as an initial value.

  The interrupt based on the count-up of CTC channel 3 (CH3) is an interrupt that occurs when the internal clock (system clock) of the CPU is counted down and the register value becomes “0”. Specifically, a clock obtained by dividing the operation clock of the CPU 56 is given to the CTC, the register value is subtracted by the input of the clock, and when the register value becomes 0, a timer interrupt occurs. For example, the register value of CH3 is subtracted at 1/256 period of the system clock. Since the subtraction is performed based on the divided clock, the initial value of the register does not increase. In step S15, a value corresponding to 2 ms is set as an initial value in the register of CH3.

  When the initialization process (steps S11 to S15) is completed, the display random number update process (step S17) and the initial value random number update process (step S18) are repeatedly executed in the main process. When the display random number update process and the initial value random number update process are executed, the interrupt disabled state is set (step S16). When the display random number update process and the initial value random number update process are finished, the interrupt enabled state is set. (Step S19). The display random number is a random number for determining a symbol displayed on the variable display device 9, and the display random number update process is a process for updating the count value of the counter for generating the display random number. . The initial value random number update process is a process for updating the count value of the counter for generating the initial value random number. The initial value random number is a random number for determining an initial value of a count value such as a counter for generating a random number for determining whether or not to make a big hit (a big hit determination random number generation counter). In a game control process described later, when the count value of the jackpot determination random number generation counter makes one round, an initial value is set in the counter.

  Note that when the display random number update process is executed, the interrupt is prohibited. The display random number update process is also executed in the timer interrupt process described later, and thus conflicts with the process in the timer interrupt process. This is to avoid that. That is, if the timer interrupt is generated during the process of step S17 and the counter value for generating the display random number is updated during the timer interrupt process, the continuity of the count value is impaired. There is a case. However, such an inconvenience does not occur if the interrupt is prohibited during the process of step S17.

  When a timer interrupt occurs, the CPU 56 executes a timer interrupt process. FIG. 9 is a flowchart showing the timer interrupt process. This timer interrupt process is executed every 2 ms. In the timer interrupt process, first, after performing the register saving process (step S19) and the power-off confirmation process (step S20), the game control process P of S21 to S33 is executed. In the game control process P, the CPU 56 first inputs detection signals of switches such as the gate switch 32a, the start port switch 14a, the count switch 23, and the winning port switches 29a, 30a, 33a, and 39a via the switch circuit 58. Then, the state determination is performed (switch processing: step S21). The power-off confirmation process (step S20) is substantially executed first in the timer interruption process.

  Next, a process of updating the count value of each counter for generating each determination random number such as a big hit determination random number used for game control is performed (step S22). The CPU 56 further performs a process of updating the count value of the counter for generating the initial value random number and the display random number (steps S23 and S24).

  Further, the CPU 56 performs special symbol process processing (step S25). In the special symbol process control, corresponding processing is selected and executed according to a special symbol process flag for controlling the pachinko gaming machine 1 in a predetermined order according to the gaming state. The value of the special symbol process flag is updated during each process according to the gaming state. Further, normal symbol process processing is performed (step S26). In the normal symbol process, the corresponding process is selected and executed according to the normal symbol process flag for controlling the display state of the normal symbol display 10 in a predetermined order. The value of the normal symbol process flag is updated during each process according to the gaming state.

  Next, the CPU 56 performs a process of setting an effect control command related to the special symbol in a predetermined area of the RAM 55 and sending the effect control command (special symbol command control process: step S27). Further, a process for sending an effect control command by setting an effect control command for the normal symbol in a predetermined area of the RAM 55 is performed (normal symbol command control process: step S28).

  Further, the CPU 56 performs information output processing for outputting data such as jackpot information, start information, probability variation information supplied to the hall management computer, for example (step S29).

  Further, the CPU 56 executes a prize ball process for setting the number of prize balls based on the detection signals from the prize opening switches 29a, 30a, 33a, 39a and the like (step S30). Specifically, a payout control command indicating the number of winning balls is output to the payout control board 37 in response to winning detection based on any of the winning opening switches 29a, 30a, 33a, 39a being turned on. The payout control CPU mounted on the payout control board 37 drives the ball payout device 97 according to a payout control command indicating the number of prize balls.

  And CPU56 performs the memory | storage process which checks the increase / decrease in the number-of-start-winning memory | storage number (step S31). In addition, a test terminal process, which is a process for outputting a test signal for enabling the control state of the gaming machine to be confirmed outside the gaming machine, is executed (step S32). Further, when a predetermined condition is established, a drive command is issued to the solenoid circuit 59 (step S33). The solenoid circuit 59 drives the solenoids 16, 21, and 21A in response to a drive command in order to open or close the variable winning ball device 15 or the opening / closing plate 20, or to switch the game ball passage in the special winning opening. To do. Thereafter, the contents of the register are restored (step S34), and the interrupt permission state is set (step S35).

  The timer interruption process including the game control process P of this embodiment is started every 2 ms. In this embodiment, the game control process P is executed in the timer interrupt process. However, in the timer interrupt process, for example, only a flag indicating that an interrupt has occurred is set, and the game control process P May be executed in the main process.

  As described above, in the present embodiment, the CPU 56 disposed on the main board 31 of the pachinko gaming machine 1 has been described as an example of the electronic device of the gaming machine, but the electronic device includes a plurality of input terminals and performs processing. The configuration to be executed is not limited to the CPU 56, and other configurations can be targeted. For example, the present invention is applied to a VDP (Video Display Processor) that is mounted on the effect control board 80 of FIG. 4 and forms an image to be displayed on the variable display device 9, or a payout control CPU mounted on the payout control board 37. Is possible.

  In this embodiment, the second input terminal, which is an empty terminal, is connected to the predetermined voltage Vcc to prevent the interrupt process that is a predetermined function from being executed inadvertently. On the contrary to the form, a form in which the second input terminal which is an empty terminal is connected to the ground G is also conceivable. In such a form, when a predetermined function (interrupt processing) is erroneously set in the second input terminal that is an empty terminal, the pachinko gaming machine 1 is caused to malfunction by intentionally executing the interrupt processing. It is possible to quickly notice a mistake in the setting of the CPU 56 (program setting of the CPU 56). Such a configuration makes it possible to find a setting error in the product development stage, and to prevent the CPU 56 from being shipped as a product with a wrong setting.

  Note that the pachinko gaming machine 1 of each of the above embodiments has a predetermined game value given to the player when the special symbol stop symbol variably displayed on the variable display device 9 based on the start winning combination is a combination of the predetermined symbols. The first type pachinko gaming machine that can be granted, the second type pachinko that can be given a predetermined game value to the player if there is a winning in a predetermined area of the electric game that is released based on the start winning A third-class pachinko machine where a predetermined right is generated or continued when there is a prize for a predetermined electric combination that is released when a stop symbol of a symbol that is variably displayed based on a starting prize is a combination of a predetermined pattern The present invention can also be applied to a gaming machine or an enclosed pachinko gaming machine that counts prize balls inside without awarding balls outside.

  Further, the present invention is not limited to pachinko gaming machines in which the game medium is a game ball, and the present invention can also be applied to a gaming machine such as a slot machine such as a medal.

1: Pachinko machine 60: Frequency display LED
2: Glass door frame 61: LED for lending ball
3: Hit ball supply tray 62: Switch 4: Extra ball receiving tray 63: Return switch 5: Operation knob 64: Information output circuit 6: Game board 65: Reset circuit 7: Game area 66: Interface board 9: Variable display device 67: Output Circuit 10: Normal symbol display 72: Relay board 14: Start winning opening 80: Production control board 14a: Start opening switch 91: Launch control board 15: Variable winning ball device 94: Drive motor 16: Solenoid 97: Ball payout device 20 : Opening / closing plate 151: Usable indicator lamp 21: Solenoid 153: Connecting base direction indicator 21A: Solenoid 154: Card insertion indicator lamp 22: V winning switch 155: Card insertion slot 23: Count switch 156: Card unit lock 25: Decoration Lamp 160: Terminal board 26: Out port 161: Door opening information switch 27: Speaker 167: burns out detection switch 28 a to 28 c: top frame ramp 187: burns out switch 29: winning opening 289: payout motor 29a: winning opening switch 301: payout count switch 30: winning opening 371: dispensing control CPU
30a: winning port switch 372a: I / O port 31: main board 372b, g: input port 32: gate 372c, e, f: output port 32a: gate switch 372d: input / output port 33: winning port 373A: input circuit 33a : Award opening switch 373B: Output circuit 37: Payment control board 374: LED for error display
38: Storage tank 375: Error release switch 39: Winning port 572: Input port 39a: Winning port switch 573: Output port 40A: Prize ball case 651: Reset IC
41: Normal symbol start memory display 902: IC for power supply monitoring
48: Full switch 910: Power supply board 49: Variable display control unit 914: Power switch 50: Card unit 920: Power monitoring circuit 51: Prize ball lamp 921: Clear switch 52: Out of ball lamp 941 to 943: Inversion circuit 53: Basic circuit D0 to D7: input terminal (first input terminal T1)
54: ROM PI0-PI4: Input terminal (first input terminal T1)
55: RAM PI5 / XINT: Output terminal (second input terminal T2)
56: CPU PI6 / XNMI: Output terminal (second input terminal T2)
57: I / O port portion PI7 / RX0: Output terminal (second input terminal T2)
58: Switch circuit G: Ground 59: Solenoid circuit Vcc: Predetermined voltage

Claims (1)

An electronic device including a first input terminal and a second input terminal;
The second input terminal is
It has an input function and an interrupt function and can be set to low active or high active.
When the interrupt function is used, it is set to low active.
When the input function is used, it is set to high active,
When it is an empty terminal, it is connected to the power line,
The first input terminal is connected to the ground when it is an empty terminal,
Setting means for setting the function of the second input terminal ;
The electronic device includes a plurality of the second input terminals,
A plurality of the second input terminals are adjacent to each other.