JP2011172654A - Game machine - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a game machine that prevents a delay of starting the whole game machine while reducing costs by delaying the start of a game control device more than the start of a slave control device by software. <P>SOLUTION: The slave control device starts while a communication port is maintaining the initial status to become a command receivable status receivable of a command from the communication port. A timer timing unit times a maintenance timer without updating the information memorized by a memory that decides rightfulness by a rightfulness determinator. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to processing at power-on in a gaming machine including a game control device and a subordinate control device that receives and controls a command from the game control device.

  When returning after the power is turned off, the award medium payout operation can be stopped until the inconvenient payout state is resolved, and there is no trouble between the player and the hall regarding the award medium payout. If the payout control means is activated prior to the main control means and the payout control is started at the time of recovery from a power failure, the initialization switch is not operated. There is known a gaming machine in which the payout operation is stopped and the payout can be resumed until the payout restart command is received from the main control means. In this gaming machine, when the main control means activated later does not detect an error relating to payout based on the detection switch from the supply replenishment detection switch or the fullness detection switch, a payout restart command is transmitted from the main control means. The payout control means is configured to restart the payout operation with the payout restart command received (see, for example, Patent Document 1).

JP 2002-224394 A

  In the gaming machine described in Patent Document 1, a delay circuit 90 is provided in the main control means (main control board 39) to activate the main control means with a delay from the payout control means, and a reset signal generating means 77 is provided. Is set so as to reach the main control means after a delay of time t from reaching the payout control means (payout control board 46) (paragraphs [0051] to [0053] of Patent Document 1. ], FIG. 9 and FIG. 11).

  For this reason, in the gaming machine described in Patent Document 1, hardware such as the delay circuit 90 is necessary, which causes a problem that the cost increases. Further, since the delay circuit 90 is configured by hardware, there is a problem in that the delay time value cannot be changed by a program.

  In this case, if the function corresponding to the delay circuit 90 is realized by software using a CPU provided in the main control means (main control board 39), the problem in terms of cost is solved.

  However, in order to measure the delay time using the CPU, the backup memory 39b of the main control means (main control board 39) must be used. In this case, after the main control means is started, the backup memory 39b Since the delay time is counted after the legitimacy is confirmed and the backup memory 39b becomes usable, the activation of the entire gaming machine is delayed.

  The present invention provides a gaming machine that prevents the activation of the entire gaming machine from being delayed while reducing the cost by delaying the activation of the gaming control apparatus from the activation of the subordinate control apparatus by software. With the goal.

  The first invention is a game capable of generating a special game state in which an auxiliary game is executed in a game area based on the establishment of a predetermined start condition and a privilege is given to a player in accordance with the result of the auxiliary game. A game control device that comprehensively controls games in the game area, and a subordinate control device that performs necessary control related to the game machine in response to a command from the game control device, and The game control device includes a communication port for outputting a command to the subordinate control device, an initialization means for initializing the communication port in response to a predetermined activation signal, and a predetermined calculation by a game control program. Arithmetic processing means for performing processing, storage means for storing information updated by the arithmetic processing means, and storing the stored information even when power supply to the gaming machine is stopped; After the generation of the signal, the validity determination means for determining the validity of the information stored and held in the storage means, and the timer timing means for timing a maintenance timer for maintaining the communication port in the initial state for a predetermined time And the slave control device is activated while the communication port maintains the initial state, enters a command receivable state capable of receiving a command from the communication port, and the timer The time measuring means measures the maintenance timer without updating the information stored in the storage means for which the validity is determined by the validity determining means.

  According to a second aspect of the present invention, the game control device is provided with a non-judgment storage area in which updatable information is stored and which is not subject to legitimacy judgment by the legitimacy judging means. The maintenance timer is timed using the non-determined storage area.

  The third invention is characterized in that the non-determination storage area is a register provided in the arithmetic processing means.

  According to a fourth aspect of the present invention, the game control device initially sets the storage means according to the validity determined by the validity determination means and the update restriction means for restricting the update of the information stored in the storage means. Storage means initialization means, and the update restriction means restricts the update of the storage means by the arithmetic processing means when the activation signal is generated, and the storage means initialization means initializes the storage means. In the case where the storage means is changed, the restriction of the update of the storage means is released.

  The fifth invention is characterized in that the update restricting means restricts updating of the storage means while the timer timing means keeps counting the maintenance timer.

  According to a sixth aspect of the invention, the storage means includes a stack area for saving information, and the validity determination means determines the validity of information stored in an area other than the stack area of the storage means. The update restricting means cancels the restriction of the update of the storage means before the validity determining means determines the validity, and the arithmetic processing means updates the storage means by the update restricting means. When the restriction is released, the setting process is executed based on the stack area.

  The seventh invention includes an initialization instruction receiving means for receiving an initialization instruction for initializing all areas of the storage means, and the arithmetic processing means is configured to determine whether the initialization instruction receiving means has received the initialization instruction. In order to confirm whether or not, the read instruction for reading the initialization instruction from the initialization instruction receiving means is executed a plurality of times without using the storage means, and the timer timing means is the read operation executed a plurality of times. During the processing, the maintenance timer is clocked.

  According to the first to third aspects, immediately after the power is turned on, the communication port is in the initial state and held for a predetermined time, and during this time, the slave control device is in a command ready state. In addition, erroneous data can be prevented from being transmitted while the communication port is in an unstable state. In addition, by performing timer measurement for a predetermined time using software, the state in which the communication port is in the initial state is maintained for a predetermined time. Therefore, a configuration that is less expensive than a method using hardware is sufficient. In addition, since the timer timing is performed without using the validity determination storage area, the validity determination processing can also be performed accurately.

  According to the fourth aspect, since the write restriction state can be set as necessary until the validity determination is performed, it is possible to prevent inadvertent writing to the storage unit.

  According to the fifth aspect, it is possible to prevent inadvertent writing to the storage means during the timer timing.

  According to the sixth invention, the processing program is shared by performing the processing using the stack area, so that the program capacity can be reduced. In addition, since the validity of the data stored in the stack area is not determined, it is possible to prevent the data in the validity determination area from being updated.

  According to the seventh aspect, the timer timing period can be used as the time for removing chattering of the operation signal, so that the processing at the time of starting the game control device can be made efficient.

It is explanatory drawing of the game device of embodiment of this invention. It is a rear view of the gaming machine of the embodiment of the present invention. It is a front view of the game board of the embodiment of the present invention. It is a block diagram of the gaming device of the embodiment of the present invention. It is a block diagram of the arithmetic processing unit (amuse chip) of the embodiment of the present invention. It is a block diagram around the arithmetic processing unit (amuse chip) for games provided in the game control device of the embodiment of the present invention. It is explanatory drawing of the user work RAM of embodiment of this invention. It is explanatory drawing of the stack area | region of embodiment of this invention. It is a flowchart of the power-on process of each device (game control device, payout control device, and effect control device) of the embodiment of the present invention. It is a flowchart of the first half part of the game control apparatus main process of embodiment of this invention. It is a flowchart of the latter half part of the game control apparatus main process of embodiment of this invention. It is explanatory drawing of the delay process of embodiment of this invention. It is explanatory drawing of the delay process of the modification of embodiment of this invention. It is a flowchart which shows the timer interruption process of embodiment of this invention. It is a timing chart of the state of the communication port with which the game control apparatus at the time of power activation of the embodiment of this invention, the payout control apparatus, and the production | presentation control apparatus performs, and the game control apparatus. It is a flowchart for demonstrating the procedure in the case of transmitting instruction | command from the game control apparatus of embodiment of this invention to an effect control apparatus and a payout control apparatus. It is explanatory drawing of the command signal transmitted to the payout control apparatus and the production | presentation control apparatus from the game control apparatus of embodiment of this invention. It is explanatory drawing of the signal transmitted to the payout control apparatus of embodiment of this invention. It is explanatory drawing of the signal transmitted to the presentation control apparatus of embodiment of this invention.

  Hereinafter, embodiments of the present invention will be described with reference to FIGS.

  In the following description of the embodiments, the front, rear, left, and right refer to directions viewed from the player, that is, viewed from the game board (game machine).

  FIG. 1 is an explanatory diagram of the gaming apparatus 6 according to the embodiment of the present invention.

  The gaming device 6 includes a card unit 70 into which a storage medium for storing a valuable value is inserted, and a gaming machine 1 that can actually play a game and pay out the gaming medium.

  First, the gaming machine 1 will be described.

  A front frame 3 of the gaming machine 1 is assembled to a main body frame (outer frame) 2 with a hinge 4 so as to be opened and closed. The game board 5 (see FIG. 3) is housed in a storage portion (not shown) formed on the front side of the front frame 3. Further, a glass frame 18 having a cover glass (transparent member) covering the front surface of the game board 5 is attached to the front frame 3.

  A decorative member 9 that emits decorative light is provided around the cover glass of the glass frame 18. The decoration member 9 is provided with a decoration device made up of a lamp, LED, or the like. The decorative member 9 emits light in a predetermined light emitting mode by emitting light from the decorative device in a predetermined light emitting mode.

  Speakers 30 that emit sound (for example, sound effects) are provided on the left and right sides of the glass frame 18. An illumination unit 10 is provided above the glass frame 18. A decoration device is provided inside the lighting unit 10.

  On the right side of the lighting unit 10, an error notification LED 29 is provided for notifying the hall clerk of the occurrence of an error in the gaming machine 1 and the opening of the front frame 3.

  The open / close panel 20 below the front frame 3 is provided with an upper tray 21 for supplying game balls to a hitting ball launching device (not shown), and the fixed panel 22 is provided with an ashtray 15, a lower tray 23, an operation unit 24 of the hitting ball launching device and the like. ing. The lower tray 23 is provided with a lower tray ball removing mechanism 16 for discharging the game balls stored in the lower tray 23. A key 25 for locking the glass frame 18 is provided on the lower right side of the front frame 3.

  Further, when the player turns the operation unit 24, the hitting ball launching device launches a game ball supplied from the upper plate 21.

  The upper edge of the upper plate 21 is provided with a select switch 40 and an operation switch 41 for receiving an operation input from a player.

  When the player operates the select switch 40, it is possible to select the contents of the effect of the variable display game on the display device 8 (see FIG. 3). In addition, when the player operates the operation switch 41, it is possible to perform an effect in which the player's operation is intervened in the variable display game on the display device 8.

  A ball lending button 26 that is operated when a player rents a game medium and a discharge button 27 that is operated to discharge the prepaid card from the card unit 50 are provided on the upper right portion of the upper plate 21. Between these buttons 26 and 27, a balance display unit 28 for displaying the balance of the prepaid card is provided.

  Next, the card unit 70 will be described.

  A card insertion slot 71 into which a card such as a prepaid card or a membership card can be inserted is provided below the card unit 70.

  A card such as a prepaid card or a member card stores a unique identifier of the card, member information of the owner (player) of the card, a balance, and the like.

  In the member information, the address, name, age, occupation, etc. of the card owner are registered.

  When a card such as a prepaid card or a membership card is inserted into the card insertion slot 71, information stored in the card is read by a card reader / writer (not shown).

  And the balance memorize | stored in the card | curd read by the card reader / writer which is not shown in figure is displayed on the balance display part 72 provided in the balance display part 28 of the game machine 1 and the center vicinity of the card unit 70. FIG.

  Above the balance display 72, a bill insertion slot 73 into which bills can be inserted is provided. The valuable value of the banknote inserted into the banknote insertion slot 73 is stored as a balance on the card.

  An operation display unit 74 is provided above the bill insertion slot 73. The operation display unit 74 changes the color corresponding to the operation of the card unit 70.

  Next, the back side of the gaming machine 1 will be described with reference to FIG. FIG. 2 is a rear view of the gaming machine 1 according to the embodiment of the present invention.

  On the back side of the gaming machine 1, specifically, on the back side of the front frame 3, a frame-like back mechanism board 310 having a substantially square opening at the center is attached.

  Above the back mechanism board 310, a ball storage unit 320 is provided that stores game balls replenished from a replenishment device (not shown) provided in the island facility and causes the stored game balls to flow down.

  On the side of the back mechanism board 310 (on the right side in FIG. 2), a ball discharge unit 330 that pays out the game balls flowing down from the ball storage unit 320 to the upper plate 21 and the lower plate 23 disposed in front of the game machine. Is disposed.

  At the center of the back mechanism board 310, there are a game control device 100 that controls the game in an integrated manner, and an effect control device 150 that controls the effect of the variable display game based on the effect control command transmitted from the game control device 100. Is disposed.

  The game control device 100 is provided with an inspection device connection terminal 107 connected to an inspection device (not shown).

  A payout control device 210 that controls the operation of the ball discharge unit 330 based on data transmitted from the game control device 100 and a power supply device 160 are disposed below the back mechanism board 310.

  The payout control device 210 is provided with an inspection device connection terminal 217 connected to an inspection device (not shown) and an error number display 222 for displaying the type of error that has occurred in the payout control device 210 in numbers.

  In addition, a card unit connection terminal 340 for connecting the gaming machine 1 to the card unit 70 is disposed on the back mechanism board 310 on the right side of the power supply device 160.

  Next, the game board 5 will be described with reference to FIG. FIG. 3 is a front view of the game board 5 according to the embodiment of the present invention.

  On the surface of the game board 5, a substantially circular game area 51 surrounded by the guide rail 55 is formed. The game area 51 is composed of resin side cases 52 and guide rails 55 provided on each of the four sides of the game board 5. The side case 52 on the lower right side of the game area 51 is covered with a black transparent certificate paper plate 53 at the center of the front surface.

  In the game area 51, a center case 300 provided with the display device 8 is arranged substantially at the center. The display device 8 is attached to a recess provided in the center case 300 at a position deeper than the front surface of the center case 300. That is, the center case 300 surrounds the display area of the display device 8 and is provided so as to protrude from the display area of the display device 8.

  In the lower right area of the game area 51, there is provided a symbol display unit 45 in which a special figure display 120 and a common figure display 121, which will be described later with reference to FIG.

  The display device 8 has a display screen composed of, for example, an LCD (liquid crystal display), a CRT (CRT), or the like. A plurality of variable display areas are provided in an area (display area) in which an image of the display screen can be displayed, and identification information (special symbol) and a character that produces a special figure variable display game are displayed in each variable display area. Is done. In the variable display area of the display screen, three special symbols assigned as identification information are displayed in a variable display (variable display), and a special map variable display game is played. In addition, an image based on the progress of the game (for example, jackpot display, fanfare display, ending display, etc.) is displayed on the display screen.

  A normal symbol starting gate 31 is provided on the left side of the center case 300. Three general winning openings 32 are provided on the lower left side of the center case 300, and one general winning opening 32 is provided on the lower right side of the center case 300.

  Under the center case 300, a start winning opening 34 provided with a normally variable winning device 33 that can be opened and closed is arranged.

  Also, below the start winning opening 34 provided in the center case 300, a special variable winning apparatus (large winning opening) 36 that can be converted into a state in which a game ball is not received and a state in which it can be easily received depending on the operation result of the display device 8. Is disposed.

  In the gaming machine 1, a game is played by launching a game ball (pachinko ball) from a launcher (not shown) toward the game area 51. The launched game balls flow down the game area 51 while changing the rolling direction by a direction changing member such as a nail or a windmill arranged in various places in the game area 51, and the normal symbol start gate 31, the general winning opening 32, The winning prize opening 34 or the special variable prize winning device 36 is won or it is discharged from the out opening 39 provided at the lowermost part of the game area 51.

  Note that the start winning opening 34 includes a state in which a game ball is likely to win and a state in which a game ball is difficult to win by opening and closing the normal variation winning device 33.

  Normally, the normally variable winning device 33 is in a closed state, and the start winning port 34 is in a state where it is difficult for a game ball to win. When the game ball passes through the normal symbol start gate 31, a general variation display game is executed, and when a hit state occurs as a result of the general variation display game, the normal variation prize winning device 33 is converted to an open state and started. The winning opening 34 is in a state where a game ball can easily win.

  The winning of a game ball in the general winning opening 32 is detected by winning openings SW (switches) 32A to 32N (see FIG. 4) provided in the general winning opening 32.

  The winning of a game ball in the start winning opening 34 is detected by a special figure start SW (switch) 34A (see FIG. 4). The special symbol random number counter value extracted by the passing timing of the game ball is stored in the special symbol storage area in the game control device 100 as a special symbol winning memory for a predetermined number of times (for example, up to four times). The number stored in the special symbol winning memory is displayed on the special symbol winning memory number display section (composite memory display section) of the display device 8. The game control device 100 plays a special symbol variation display game on the display device 8 based on the display of the special symbol winning memory number display unit.

  When there is a winning game ball at the start winning opening 34, the display device 8 has a special symbol (identification information) composed of the above-mentioned numbers etc. on the left (first special symbol), right (second special symbol), middle Variation display is started in the order of (third special symbol), and an image relating to the special diagram variation display game is displayed. That is, in the display device 8, a special symbol variation display game corresponding to the number of special symbol winning memories is performed, and various displays are produced to improve the interest.

  When a winning at the start winning opening 34 is made at a predetermined timing (specifically, when the winning random number at the time of winning detection is a winning value), a specific figure is displayed as a result of the special figure changing display game. A result mode (special result mode) is derived and a jackpot state is obtained. Specifically, the special symbol winning memory display unit of the display device 8 stops at a single-digit special symbol that is a winning symbol, and the display device 8 stops in a state where three special symbols are aligned (big hit symbol). To do. At this time, the special variable prize winning device 36 is opened so that it can easily accept a game ball from a closed state in which it does not accept a game ball for a predetermined time (for example, 30 seconds) by energizing a large prize opening solenoid 38 (see FIG. 4). Converted to a state. That is, since the special variable winning device 36 opens greatly until a predetermined time or a predetermined number of game balls wins, a privilege that the player can acquire many game balls during this time is given.

  In the special symbol display 120 (see FIG. 4) of the symbol display unit 45, the symbol variation display is performed in synchronization with the special symbol variation display game. Then, when a special result mode is derived from the display symbol as a result of the special symbol variation display game, the special symbol display device 120 can select a specific symbol corresponding to the win (for example, any one of “1” to “9”). When the special figure change display game is out of play, the special figure display 120 also displays a symbol (for example, “0” etc.) corresponding to the outage.

  The winning of the game ball to the special variation winning device 36 is detected by a count SW (switch) 36A (see FIG. 4).

  The passing of the game ball to the normal symbol start gate 31 is detected by a normal start SW (switch) 31A (see FIG. 4). The normal symbol random number counter value extracted based on the passing timing of the game ball is stored in the normal symbol storage area in the game control device 100 as a normal symbol winning memory for a predetermined number of times (for example, a maximum of four times). Then, the stored number of the memorized winning prize memory is displayed on a not-illustrated memorized winning prize memory number display section of the symbol display unit 45.

  When there is a general-purpose winning memory, the game control device 100 starts a general-game variable display game on the general-purpose winning memory display section based on the general-purpose winning memory. That is, when the passage detection to the normal symbol start gate 31 is performed at a predetermined timing (specifically, when the common random number counter value at the time of passage detection is a winning value), the common symbol winning memory number display is performed. The normal symbol displayed on the part stops in the hit state and enters the hit state. At this time, the normal variation winning device 33 is energized to the ordinary solenoid 90 (see FIG. 4), so that the entrance to the starting winning port 34 is within a predetermined time (for example, within a range of 0.5 seconds to 2.9 seconds). And the game ball is allowed to enter the start winning opening 34. This makes it easier for the game ball to win the start winning opening 34 and the special figure variation display game to be started easily.

  In this way, when game balls win the general winning opening 32, the start winning opening 34, or the special variable winning apparatus 36, the number of winning balls corresponding to the type of the winning opening is controlled by the payout control apparatus 210. From the dispensing unit 360, the front frame 3 is discharged to the upper plate 21 or the lower plate 23.

  Note that the pachinko gaming machine according to the present embodiment corresponds to the result of the special figure fluctuation display game (strictly, it corresponds to the display mode of the special figure display 120 executed in synchronization with the special figure fluctuation display game). The probability of hitting a special figure variation display game thereafter may change, and the gaming state is always a low probability state in which the special figure fluctuation display game is won with a low probability or more than the low probability state. The special figure variation display game is set to one of the high probability states in which the game is won with high probability. Note that the low probability state may be referred to as a non-probability variation gaming state, or the high probability state may be referred to as a probability variation gaming state.

  Further, the gaming state of the pachinko gaming machine according to the present embodiment may change the release frequency of the normal variation winning device 33 in accordance with the result of the special figure variation display game, and the gaming state is always varied normally. The winning device 33 is set to either a winning suppression state in which the opening frequency of the winning device 33 is low or a winning promotion state in which the opening frequency of the normal variation winning device 33 is higher than the winning suppression state. The winning suppression state may be referred to as a non-short-time gaming state, or the winning promotion state may be referred to as a short-time gaming state.

  In the winning promotion state, the execution time of the normal fluctuation display game is controlled to be shorter than the execution time in the winning suppression state (for example, 10 seconds in the winning suppression state and 1 second in the winning promotion state). As a result, the number of times of opening the normally variable winning device 33 per unit time is controlled to be substantially increased.

  Further, in the winning promotion state, when the normal variation winning game 33 is released as a result of winning the normal fluctuation display game, the opening time may be controlled to be longer than the opening time of the normal gaming state. (For example, 2.9 seconds in the winning promotion state versus 0.5 seconds in the winning suppression state). Further, in the winning promotion state, the normal variation winning device 33 may be opened a plurality of times (for example, twice) instead of once with respect to a single winning result of the normal symbol variation display game. Further, in the winning promotion state, control may be performed so that the probability of the winning result of the usual fluctuation display game is higher than the winning suppression state. That is, in the winning promotion state, the opening frequency of the normal variation winning device 33 increases more than in the winning suppression state, and it becomes easier for a game ball to win the normal variation winning device 33 and the special figure variable display game can be easily started. Is granted.

  FIG. 4 is a block diagram of the gaming apparatus 6 according to the embodiment of the present invention.

  The game control device 100 includes a game microcomputer (game calculation processing device 600) 101, an input I / F (Interface) 105, an output I / F (Interface) 106, and an inspection device connection terminal 107.

  The gaming microcomputer 101 includes a CPU 102, a ROM (Read Only Memory) 103, and a RAM (Random Access Memory) 104.

  The CPU 102 is a main control device that controls the game in an integrated manner, and controls the game. The ROM 103 stores invariant information (programs, data, etc.) for game control. The RAM 104 is used as a work area during game control.

  The game control device 100 is provided with an inspection device connection terminal 107, and an identification number uniquely set in the gaming microcomputer 101 can be output from the inspection device connection terminal 107. Thus, when an inspection device (not shown) is connected to the inspection device connection terminal 107, the inspection device can identify the gaming machine 1.

  The CPU 102 receives various inspection devices (special drawing start SW 34A, universal drawing start SW 31A, count SW 36A, winning opening SWa32A to winning opening SWn32N, overflow SW (switch) 109, out of ball SW (switch) 110 via the input I / F 105. , And a detection signal from the frame opening SW (switch) 111), various processes such as a big hit lottery are performed.

  The overflow switch 109 detects that a predetermined number or more of game balls are stored in the lower plate 23. The ball break switch 110 is disposed in the ball storage unit 320 and detects that the number of game balls stored in the ball storage unit 320 is less than or equal to a predetermined number. The frame opening switch 111 detects that the front frame 3 is opened.

  In addition, the CPU 102, via the output I / F 106, displays a general-purpose indicator 121, a special-purpose indicator 120, a general electric power SOL (solenoid) 90, a special winning opening SOL (solenoid) 38, a payout control device 210, and an effect control device. A command signal is transmitted to 150 to control the game in an integrated manner.

  The universal symbol display 121 displays a variable display game that is performed when a game ball wins the normal symbol starting gate 31. The special display 120 displays a variable display game that is played when a game ball wins the start winning opening 34.

  The general electric power SOL 90 opens the normal variation winning device 33 provided in the start winning opening 34 and opens the entrance to the starting winning opening 34 for a predetermined time.

  The special winning opening SOL38 is in an open state (advantageous to the player) from a closed state (a disadvantageous state for the player) in which the special winning opening of the special variable winning device 36 does not accept the game ball for a predetermined time. State).

  In addition, the game control device 100 outputs information related to the gaming machine 1 to an information collection terminal or a game hall internal management device (not shown) installed in the game store via the external information terminal 108.

  The game control device 100 transmits a change start command, a customer waiting demo command, a fanfare command, a probability information command, an error designation command, and the like to the effect control device 150 as an effect control command signal.

  Next, the payout control device 210 and the effect control device 150 will be described.

  The effect control device (display control device) 150 includes an error notification LED 29, a speaker 30, a decorative member 9 (FIG. 1) that performs a game effect by light emission, and the display device 8 based on various signals input from the game control device 100. Control.

  The effect control device 150 includes a game microcomputer (game operation processing device 600) 151, a driver 155, a sound circuit 156, and a VDP 157.

  The gaming microcomputer 151 includes a CPU 152, a ROM 153, and a RAM 154.

  The CPU 152 is a control device that controls effect control. The ROM 154 stores invariant information (programs, data, etc.) for effect control. The RAM 154 is used as a work area during production control.

  The driver 155 controls the error notification LED 29 and the decoration member 9 according to a command from the CPU 152. The sound circuit 156 generates a sound effect according to a command from the CPU 152 and outputs it from the speaker 30. The VDP 157 generates image data in response to a command from the CPU 152 and outputs the image data to the display device 8.

  The payout control device 210 is a device that drives the payout motor 220 of the payout device based on the prize ball command signal from the game control device 100 and performs control for paying out the prize ball. Also, the payout control device 210 drives the payout motor 220 of the payout device based on the payout command signal transmitted from the game control device 100 based on the loan request signal from the card unit 70, and pays out the rental money. It is an apparatus which performs control for making it happen.

  The payout control device 210 includes a game microcomputer (game processing device 600) 211, an input I / F (Interface) 215, an output I / F (Interface) 216, and an inspection device connection terminal 217.

  The gaming microcomputer 211 includes a CPU 212, a ROM 213, and a RAM 214.

  The CPU 212 is a control device that comprehensively controls the payout and controls the payout control. The ROM 213 stores invariant information (program, data, etc.) for payout control. The RAM 214 is used as a work area during payout control.

  The CPU 212 receives inputs from the payout ball detection sensor 112, the overflow switch 109, the ball break switch 110, the error release switch 223, the tax rate setting switch 226, and the lending fee setting switch 227 via the input I / F 215.

  The error release switch 223 is operated by the store clerk of the amusement store to cancel the error state when the cause of the error generated by the store clerk of the amusement store is resolved when an error occurs in the payout control device 210. It is a switch.

  The tax rate setting switch 226 is a switch for setting a tax rate of indirect tax imposed on the rental of game balls. The rental fee setting switch 227 is a switch for setting the valuable value of the game balls to be lent.

  Further, the CPU 212 transmits a command signal to the payout motor 220, the launch control device 221, the error number display 222, the tax rate display 224, and the rental charge display 225 via the input / output I / F 216. In addition, the CPU 212 receives various signals from the game control apparatus 100 via the input / output I / F 216.

  The payout motor 220 is a motor that is actually driven to pay out the game ball by the payout device. Specifically, the payout motor 220 pays out the game ball by rotating a sprocket having a predetermined number of recesses capable of storing one game ball.

  The launch control device 221 controls a launch device for launching a game ball onto the game board 5. The error number display 222 is disposed on the back side of the payout control device 210 and displays the type of error that has occurred in the payout control device 210 so that it can be specified.

  The tax rate indicator 224 is disposed on the back side of the payout control device 210 and displays the tax rate of the indirect tax set by the tax rate setting switch 226. The rental charge indicator 225 is disposed on the back side of the payout control device 210 and displays the valuable value of the game balls to be lent set by the rental charge setting switch 227.

  The game control device 100, the effect control device 150, and the payout control device 210 are connected to the power supply device 160.

  The power supply device 160 includes a backup power supply 161 and a RAM clear switch 162.

  The backup power supply 161 supplies power to the game control device 100, the effect control device 150, and the payout control device 210 even in the event of a power failure (it may not be supplied to the effect control device 150).

  The RAM clear switch 162 is a switch that initializes information stored in the RAM 104 provided in the game control device 100 and the RAM 214 provided in the payout control device 210.

  Further, when the ball lending button 26 provided in the gaming machine 1 is operated, the card unit 70 subtracts the valuable value for the gaming ball to be lent from the valuable value stored in the card such as the prepaid card or the membership card. The value of the subtracted valuable value is displayed on the balance display unit 28 of the gaming machine 1. Further, when the discharge button 27 provided in the gaming machine 1 is operated, the card unit 70 discharges the card inserted into the card insertion slot 71.

  The game microcomputer 101 provided in the game control device 100 and the game microcomputer 211 provided in the payout control device 210 are connected by SIO connection and NACKIN connection.

  An unencrypted signal (plain text data) that is not encrypted is communicated in the SIO connection, and an encrypted encrypted signal (encrypted data) is communicated in the NCLILINK connection.

  Note that the gaming microcomputer 101 provided in the gaming control device 100 and the gaming microcomputer 211 provided in the payout control device 210 include ports for SIO connection and NCLILINK connection.

  Next, the game microcomputer 101 provided in the game control device 100 and the game microcomputer 211 provided in the payout control device 210 (hereinafter collectively referred to as a game arithmetic processing device 600) will be described in detail with reference to FIG.

  FIG. 5 is a block diagram of the game processing unit (amuse chip) 600 according to the embodiment of the present invention.

  The game processing unit 600 is manufactured as an IC for a so-called amuse chip, and is divided into a game area unit 600A for performing game control and an information area unit 600B for managing information.

  First, the game area 600A is a collective term for a CPU core 601 (corresponding to the CPU 102 or CPU 212 in FIG. 4), a user program ROM 602 (corresponding to the ROM 103 or ROM 213 in FIG. 4), and an HW parameter ROM 603 (user program ROM 602 and HW parameter ROM 603). ROM (non-volatile storage means), user work RAM 604 (corresponding to RAM 104 or RAM 214 in FIG. 4), mirrored RAM 605 (user work RAM 604 and mirrored RAM 605 are collectively referred to as RAM (volatile storage means)), external Bus interface (I / F) 606, bus switching circuit 607, random number generation circuit 608, clock generator 609, reset / interrupt control circuit 610, address decoder 611, output control circuit 6 2, the boot block 613, decoding · ROM write circuit 614, a serial transceiver circuit 615, the encryption reception circuit 616, and configured by a bus 617.

  The CPU core 601 functions as arithmetic processing means for performing arithmetic processing for game control. The user program ROM 602 stores a control program. The control program is a game control program for controlling a game when the game arithmetic processing device 600 is the game microcomputer 101 provided in the game control device 100, and the game arithmetic processing device 600 is a payout control device. 210 is a payout control program for paying out game balls in the case of the game microcomputer 211 provided in 210, and in the case where the game arithmetic processing device 600 is the game microcomputer 151 provided in the effect control device 150, This is an effect control program for effect control.

  The HW parameter ROM 603 stores validity confirmation information. The legitimacy confirmation information is information in the case of performing a simple check of the legitimacy of the gaming arithmetic processing device 600. For example, a unique ID indicating a unique identifier of the gaming machine 1, a manufacturer code (manufacturer of the gaming machine 1) A unique identifier assigned to each manufacturer), a rank code indicating the rank (1 type, 2 type, etc.) of the gaming machine 1, a model code set by the manufacturer for the type of the gaming machine 1, and an inspection number. An inspection code to be displayed, a RAM backup code indicating whether or not to back up the RAM when the power is turned on, a tax rate set by the tax rate setting switch 226, a lending fee set by the lending fee setting switch 227, and the like. Further, the HW parameter ROM 603 stores only one unique ID that is a unique identifier of the inspection apparatus that first transmitted the lending information request.

  When the third party organization or the manufacturer of the gaming machine 1 writes the program in the user program ROM 602, the validity confirmation information is written in the HW parameter ROM 603.

  When performing a simple check of the gaming arithmetic processing device 600, when the gaming arithmetic processing device 600 is powered on, the arithmetic value calculated by the gaming arithmetic processing device 600 itself and the validity confirmation information (that is, a third party organization, etc.) And a result value set in advance by the above-described (3), the game processing unit 600 can be easily checked.

  The user work RAM 604 is used as a work area (work area) when executing processing based on a program in the game area 600A. Since the user work RAM 604 is supplied with the backup power from the backup power supply 161 (FIG. 4), the stored data is retained even if the power supply to the gaming machine 1 is interrupted. The mirrored RAM 605 duplicates the information stored in the user work area at the fall of the clock and stores the duplicated information (if the CPU core is Z80, the process is executed at the rise of the clock. To prevent it from moving.)

  The external bus interface 606 is an interface such as a memory request signal MREQ, an input / output request signal IORQ, a memory write signal WR, a memory read signal RD, and a mode signal MODE, and the bus switching circuit 607 is a 16-bit address signal A0. ˜A15 and 8-bit data signals D0 to D7.

  For example, if the data signals D0 to D7 are added while sequentially increasing the address signals A0 to A15 while the MODE signal is at a high level, the writing mode to the user program ROM 602 is set, and the gaming machine 1 manufacturer or The program can be written by a third party. Note that the write mode allows a program to be written, and does not allow a boot program stored in the boot block 613 to be written. Further, when the writing of the program to the user program ROM 602 is completed, a writing end code is recorded in a predetermined area of the HW parameter ROM 603 (for example, recorded by physically cutting a predetermined code or a predetermined bit). Thus, when a write end code is recorded in the HW parameter ROM 603, a new program cannot be written in the user program ROM 602.

  The random number generation circuit 608 generates a random number related to whether or not to add a game value (for example, jackpot) in the game execution process (the random number is used for determining a jackpot or determining a symbol at a stop). A mathematical method (for example, a congruent method or an M-sequence method) for generating a uniform random number is used. Note that when the gaming arithmetic processing device 600 is the gaming microcomputer 211 provided in the payout control device 210, the random number generation circuit 608 may not be provided.

  The clock generator 609 generates a timer interrupt signal generated at a predetermined cycle (for example, 4 milliseconds) and a clock signal. The timer interrupt signal and clock signal generated by the clock generator 609 are input to the CPU core 102. When the timer interrupt signal is input, the CPU core 102 executes the timer interrupt process shown in FIG.

  When the reset / interrupt control circuit 610 detects an externally input reset signal (RST), the reset / interrupt control circuit 610 transmits the reset signal to each circuit provided in the gaming arithmetic processing device 600. When the occurrence of a predetermined interrupt condition is detected, the CPU core 601 is notified of the occurrence of the interrupt.

  The address decoder 611 decodes the location of the built-in device and the built-in control / status register group by the memory mapped I / O method and the I / O mapped I / O method.

  The output control circuit 612 controls the signal from the address decoder 611, outputs an 8-bit chip select signal (CS0 to CS7) from the external terminal to the outside, and selects a circuit provided inside the game processing unit 600 A function of generating a chip select signal. The boot block 613 stores a boot program and performs processing related to initialization of the gaming arithmetic processing device 600 when the power is turned on.

  The decryption / ROM writing circuit 614 is used in the writing mode to the user program ROM 602 and the HW parameter ROM 603, and passes through the bus switching circuit 607 while the mode signal MODE is at the [H] level. The address signals A0 to A15 and the data signals D0 to D7 are fetched and the information (encrypted program and encrypted unique ID after change) included in the data signals D0 to D7 is decrypted, and then the bus The data is output (written) to the user program ROM 602 and the HW parameter ROM 603 via 617.

  The serial transmission / reception circuit 615 is a circuit for transmitting / receiving plaintext data not encrypted by SIO connection.

  The encrypted transmission / reception circuit 616 is a circuit that transmits / receives encrypted data encrypted by the NCLILINK connection. A NCLILINK signal line is connected to the encrypted transmission / reception circuit 616. The encrypted transmission / reception circuit 616 transmits / receives data via the NCLILINK signal line.

  The bus 617 includes a data bus (data bus 660 in FIG. 6), an address bus (address bus 650 in FIG. 6), and a control bus, and extends to the information area 600B.

  Next, an information area unit 600B for managing information in the game processing unit 600 includes an HPG program ROM 618, an ID property memory 619, a bus monitor circuit 620, an HPG work RAM 621, a control circuit 622, an external communication control circuit 623, and a bus 624. , And a part of the bus 617 extending from the game area 600A.

  The HPG program ROM 618 stores an HPG program for performing various inspection operations.

  In the ID property memory 619, the information stored in the HW parameter ROM 603 can be immediately output to the inspection device (not shown) based on the request received from the inspection device (not shown) via the external communication control circuit 623. The information stored in the HW parameter is duplicated and stored when the computer processing unit 600 is powered on (system reset). The ID property memory 619 can be accessed from both the game area 600A side and the information area 600B side.

  The bus monitor circuit 620 monitors and controls the state of the bus 617 on the game area 600A side from the information area 600B side. The control here refers to timing control when the contents of the HW parameter ROM 603 are copied to the ID property memory 619, or when the program stored in the user program ROM 602 is output to the outside (the bus 617 on the game area 600A side is connected). Timing control at the time of opening and reading a program from the user program ROM 602 and outputting it to the outside from the information area 600B side. The program is output after being encrypted by the external communication control circuit 623.

  The HPG work RAM 621 is used as a work area (work area) when executing processing based on a program in the information area unit 600B.

  The control circuit 622 controls the information area 600B side and has a buffer memory. For example, the control circuit 622 monitors the operation of the CPU core 102 via the bus monitor circuit 620 and copies the contents stored in the user work RAM 604 of the game area unit 600A to the mirrored RAM 605 during non-operation. Further, the contents of the ID property memory 619 of the information area unit 600B are transferred to the outside in response to a request from an inspection apparatus (not shown), or the program in the user program ROM 602 is received via the bus monitor circuit 620 in response to a program request. To the outside. The memory of the control circuit 622 is used for timing adjustment at the time of transfer.

  The external communication control circuit 623 communicates with an inspection device (not shown). For example, information (for example, a unique ID, a program, an actual payout) stored in the game processing device 600 based on a command from the outside. The number is encrypted, and then transferred to the outside. In the game processing unit 600, the game area unit 600A and the information area unit 600B operate independently via the bus monitor circuit 620. That is, the information area 600B side can operate regardless of the operation of the CPU core 102 in the game area 600A (regardless of the program execution).

  Although not shown in FIG. 5, the gaming arithmetic processing device 600 includes a security circuit 630 and a RAM access restriction circuit 640 described later in FIG. 6.

  FIG. 6 is a block diagram of a game arithmetic processing device (amuse chip) 600 provided in the game control device 100 according to the embodiment of the present invention and its surroundings.

  The arithmetic processing unit 600 for gaming includes a security circuit 630, a CPU core 102 (601 in FIG. 5), a RAM access restriction circuit 640, a user work RAM 104 (604 in FIG. 5), a bus switching circuit 607, an address decoder 611, and an output control circuit. 612 and a user program ROM 103 (602 in FIG. 5).

  Note that these circuits and the like included in the gaming arithmetic processing device 600 are connected via an address bus 650 and a data bus 660.

  Further, the game control device 100 includes an effect control communication port 670 connected to the effect control device 150 and a payout control communication port 680 connected to the payout control device 210 outside the game arithmetic processing device 600. . Hereinafter, the effect control communication port 670 and the payout control communication port 680 are collectively referred to as communication ports 670 and 680. The communication ports 670 and 680 function as communication ports (command output means) in the present embodiment, and are included in the output I / F 106 shown in FIG.

  The communication ports 670 and 680 are connected to the gaming arithmetic processing device 600 via a data bus 690 external to the gaming arithmetic processing device 600.

  The data buses 660 and 690 are configured by 8-bit signal lines D0 to D7.

  When power is supplied to the gaming arithmetic processing device 600, a reset signal (start signal) is input from the power supply device 160 via the RST terminal (FIG. 5), and the reset interrupt control circuit 610 (FIG. 5) is activated. Operate.

  When this reset signal is input, the security circuit 630 executes security check processing using the validity confirmation information stored in the HW parameter ROM 602. This security check process is a process for determining the validity of the program stored in the user program ROM 103.

  While this security check process is being executed, the security circuit 630 continuously outputs a reset signal to the reset terminal (RES (negative logic)) of the CPU core 102, thereby waiting for the CPU core 102 to start up. .

  The CPU core 102 includes the aforementioned reset terminal (RES (negative logic)), a write command output terminal (WR (negative logic)), and a read command output terminal (RD (negative logic)). The reset terminal is connected to the security circuit 630, and when a reset signal is input to the gaming arithmetic processing device 600, as described above, the reset to the CPU core 102 is performed during the security check process. A signal is input to the reset terminal.

  When a reset signal is input to the reset terminal of the CPU core 102, the CPU core 102 initializes a register (REG) provided in the CPU core 102.

  When the CPU core 102 outputs a write command for instructing the user work RAM 104 to write data, a low level signal having a voltage lower than a predetermined value is output from the write command output terminal of the CPU core 102. Is done. Similarly, when the CPU core 102 outputs a read command for instructing data read from the user work RAM 104, a low level signal having a voltage lower than a predetermined value is output from the read command output terminal of the CPU core 102. The

  That is, the normal voltage is maintained at a high level at the write command output terminal and the read command output terminal, and the voltage is at a low level only when reading / writing to the user work RAM 104 is performed.

  First, reading of data from the user work RAM 104 will be described.

  When a read command is input from the CPU core 102 to a read command input terminal (RD (negative logic)) of the user work RAM 104, read data is output to the CPU core 102 via the address bus 650 and the data bus 660.

  At this time, the address of the user work RAM 104 is output from the CPU core 102 to the address bus 650, and a selection signal is input from the address decoder 611 to a chip selection terminal (corresponding to a so-called CS terminal, not shown) of the user work RAM 104. As a result, the user work RAM 104 is selected. Next, the selected user work RAM 104 outputs the data in the storage area designated by the address bus 650 to the data bus 660. Next, the CPU core 102 takes in the data output to the data bus 660. By such a procedure, the CPU core 102 reads data from the user work RAM 104.

  Next, data writing to the user work RAM 104 will be described.

  The write command output terminal provided in the CPU core 102 is connected to one input terminal of the two input terminals provided in the OR gate circuit 642 of the RAM access restriction circuit 640. The other input terminal of the OR gate circuit 642 is connected to the output terminal (Q (negative logic)) of the flip-flop circuit 641 of the RAM access restriction circuit 640, and the output terminal of the OR gate circuit 642 is the write of the user work RAM 104. It is connected to the command input terminal (WR (negative logic)).

  When a low level signal having a voltage equal to or lower than a predetermined value is input to the write command input terminal of the user work RAM 104, writing to the user work RAM 104 is permitted.

  Therefore, writing to the user work RAM 104 is not permitted unless low level signals are input to the two input terminals of the OR gate circuit 642, respectively. In other words, when a high level signal is input to at least one input terminal of the OR gate circuit 642, writing to the user work RAM 104 is restricted (prohibited).

  Here, the flip-flop circuit 641 of the RAM access restriction circuit 640 will be described.

  The flip-flop circuit 641 uses, for example, a logic IC whose model number is 74HC74. The flip-flop circuit 641 is a D-type flip-flop circuit. As input terminals, a data terminal (D), a clear terminal (CLR (negative logic)), a clock terminal (CK (positive logic)), and a preset terminal ( PR (negative logic)) and output terminals (Q (positive logic), Q (negative logic)).

  One predetermined signal line (for example, D0) among the signal lines D0 to D7 constituting the data bus 660 is connected to the data terminal.

  A reset signal line is connected to the clear terminal from the power supply device 160, and when the reset signal is input, the clear terminal becomes low level. At this time, the flip-flop circuit 641 outputs a low level signal from the output terminal Q (positive logic) and outputs a high level signal from the output terminal Q (negative logic). The output from the output terminal Q (positive logic) and the output from the output terminal Q (negative logic) are at levels that are mutually inverted.

  The clock terminal is connected to the output control circuit 612 and is normally maintained at a low level.

  The signal level from the output terminal Q (negative logic) provided in the flip-flop circuit 641 can be freely set by the CPU core 102. This setting is realized by the CPU core 102 writing predetermined data in the storage area of the address assigned to the flip-flop circuit 641.

  Specifically, when the CPU core 102 performs processing to write data to the storage area of the address assigned to the flip-flop circuit 641, the address of the flip-flop circuit 641 is output from the CPU core 102 to the address bus 650. The Next, a clock signal is input from the address decoder 611 to the clock terminal of the flip-flop circuit 641 via the output control circuit 612, and the voltage level of the clock terminal rises to a high level.

  At this time, the flip-flop circuit 641 captures the signal input to the data terminal, outputs the captured signal from the output terminal Q (positive logic), and outputs the inverted value of the captured signal from the output terminal Q (negative logic). Output.

  Further, in the flip-flop circuit 641, when the output control circuit 612 finishes inputting the clock signal, the voltage level of the clock terminal falls and becomes a low level, and the output terminal Q (positive logic) and the output terminal Q (negative logic). ) Voltage level.

  The preset terminal is connected to a pull-up resistor (not shown), and the voltage level of the preset terminal is always high.

  The output terminal Q (negative logic) outputs a signal to the input terminal of the OR gate circuit 652. Nothing is connected to the output terminal Q (positive logic).

  Next, various operations according to the input state of the flip-flop circuit 641 will be described.

  As described above, the flip-flop circuit 641 reads the voltage level of the data terminal at the rise of the voltage level of the clock terminal, that is, when the input of the clock signal starts, and outputs the inverted value of the read voltage level to the output terminal Q (negative logic). Output from.

  On the other hand, the flip-flop circuit 641 holds the output from the output terminal Q (negative logic) at the fall of the voltage level of the clock terminal, that is, at the end of the input of the clock signal, at the rise of the power level of the clock terminal.

  When a high level signal is output from the output terminal Q (negative logic) to the input terminal of the OR gate circuit 642, either the low level signal or the high level signal is input to the other input terminal of the OR gate circuit 642. Also, a high level signal is output from the output terminal of the OR gate circuit 642.

  Therefore, if a high-level signal is output from the output terminal Q (negative logic) of the flip-flop circuit 641, even if a write command signal is input to the other input terminal of the OR gate circuit 642 (the other Even if a low level signal is input to the input terminal), the low level is not input to the write command input terminal of the user work RAM 104, and a RAM write inhibit state occurs.

  The voltage level input to the data terminal of the flip-flop circuit 641 when the clock signal is input to the flip-flop circuit 641 depends on whether the RAM access restriction circuit 640 is in the RAM write prohibition state or the RAM write permission state. Or based on the presence or absence of a reset signal input.

  As described above, the CPU core 102 can control the output control circuit 612 to control the output of the clock signal, and can also control the output of the signal line of the data bus 660, so that the output terminal Q (negative logic) of the flip-flop circuit 641. The signal output from can be controlled by the CPU core 102. In other words, the CPU core 102 can control the write state of the RAM access restriction circuit 640 by controlling the signal level of the data bus 660.

  Further, as described above, when the reset signal is input to the clear terminal of the flip-flop circuit 641, the flip-flop circuit 641 sets the voltage level of the output terminal Q to low, and therefore the output terminal Q (negative logic) The voltage level goes high. Therefore, when a reset signal is input to the flip-flop circuit 641, the RAM access restriction circuit 640 causes a RAM write prohibition state.

  Next, the communication ports 670 and 680 will be described.

  Communication ports 670 and 680 are configured by D-type flip-flop circuits. For example, a logic IC having a model number of 74HC273 is used for the flip-flop circuit, for example.

  This flip-flop circuit includes D0 to D7 terminals (D0_D7 in the figure), a clock terminal (CK), a clear terminal (CLR (negative logic)), and output terminals Q0 to Q7 (Q0_Q7 in the figure).

  DO to D7 terminals are terminals connected to the data bus 690 to acquire data to be transmitted to the effect control device 150 or the payout control device 210 from the data bus 690.

  A reset signal line is connected to the clear terminal from the power supply device 160. When a reset signal is input, the voltage level of the reset terminal becomes a low level. At this time, the communication ports 670 and 680 output low level signals from all of the output terminals Q0 to Q7.

  The signal levels from the output terminals Q0 to Q7 provided in the communication ports 670 and 680 can be freely set by the CPU core 102. This setting is realized by the CPU core 102 writing predetermined data in the storage area of the address assigned to the communication port 670 or the communication port 680.

  Specifically, when the CPU core 102 performs a process of writing data to the storage area of the address assigned to the communication port 670 (or communication port 680), the CPU core 102 transfers the communication port 670 ( Alternatively, the address of the communication port 680) is output. Next, a clock signal is input from the address decoder 611 to the clock terminal of the communication port 670 (or communication port 680) via the output control circuit 612, and the voltage level of the clock terminal rises to a high level.

  The communication ports 670 and 680 read data from the data bus 690 via the D0 to D7 terminals and output the read data from the Q0 to Q7 terminals when the voltage level of the clock terminal rises, that is, when the input of the clock signal starts.

  The communication ports 670 and 680 hold the voltage levels of the Q0 to Q7 terminals when the voltage level of the clock terminal falls, that is, when the input of the clock signal is completed.

  As described above, when the output control circuit 612 inputs a clock signal to the communication port 680 connected to the payout control device 210, the communication port 680 reads data from the data bus 690 at the timing when the clock signal is input, The read data is output to the dispensing control device 210.

  As described above, when a reset signal is input to the communication ports 670 and 680, the communication ports 670 and 680 are initialized. Specifically, when a reset signal is input, regardless of the voltage level of the DO to D7 terminals, the voltage level of the Q0 to Q7 terminals is low, and the communication ports 670 and 680 are in the initial state.

  Note that the activation (reset) of the security circuit 630, the RAM access restriction circuit 640, and the communication ports 670 and 680 described above receives a reset signal from the power supply device 160 via the reset interrupt control circuit 610 (FIG. 5). Will be executed if accepted. However, the reset signal from the power supply device 160 does not necessarily have to be input to each circuit via the reset interrupt control circuit 610, but to each circuit via a separate signal line that does not pass through the reset interrupt control circuit 610. It may be configured to be input.

  The payout control apparatus 210 does not include the communication ports 670 and 680, but includes a reception port (command input means) (not shown) that receives an output signal from the communication port 680 as shown in FIG. This is different from the game control device 100. The other configuration is the same as that of the game control apparatus 100 shown in FIG.

  In addition, the effect control device 150 does not include the communication ports 670 and 680, but includes a reception port (command input means) (not shown) that receives an output signal from the communication port 670 as shown in FIG. This is different from the game control device 100. Further, the gaming arithmetic processing device 600 does not include the RAM access restriction circuit 640. The other configuration is the same as that of the game control apparatus 100 shown in FIG.

  Note that the reception port provided in the payout control device 210 and the effect control device 150 uses a logic IC whose model number is 74HC244. 74HC244 is a three-state buffer, and signals from the communication ports 670 and 680 of the game control device 100 are connected to the data input side of the three-state buffer, and the data output side of the three-state buffer is connected to the payout control device 210 (or effect). The data bus 690 formed in the control device 150) is connected.

  FIG. 7 is an explanatory diagram of the user work RAM 104 according to the embodiment of this invention.

  The user work RAM 104 includes a first power failure recovery area 701, a work area 702, a checksum area 703, a second power failure recovery area 704, a use prohibition area 705, and a stack area 706.

  Addresses “2800H” to “29FFH” are assigned to the user work RAM 104, addresses “2800H” are assigned to the first power failure recovery area 701, and addresses “2801H” to “2917H” are assigned to the work area 702. The address “2918H” is allocated to the checksum area 703, the address “2919H” is allocated to the second power failure recovery area 704, and the addresses “291AH” to “297FH” are allocated to the prohibited area 705. The stack area 706 is assigned addresses “2980H” to “29FFH”.

  Each area of the user work RAM 104 will be described.

  The first power failure recovery area 701 and the second power failure recovery area 704 store information that is referred to when power supply to the gaming machine 1 is started. Information (power cutoff confirmation flag) indicating whether or not the power cutoff processing has been executed correctly when the power switch 1 is turned off) is stored.

  The work area 702 stores variables and the like necessary for game control, and these variables are updated by the game control device main process shown in FIGS. 10 and 11 and the timer interrupt process shown in FIG. The checksum area 703 stores the checksums of the first power failure recovery area 701, the work area 702, the checksum area 703, and the second power failure recovery area 704 of the user work RAM 104 that are calculated when a power failure occurs.

  The use-prohibited area 705 is a storage area that is not used, and the CPU core 102 is reset when the area is accessed.

  The stack area 706 stores saved data when part of the data calculated by the CPU core 102 is temporarily saved. In addition, a return address when an interrupt occurs and a return address when a subroutine or function is called are also stored.

  FIG. 8 is an explanatory diagram of the stack area 706 according to the embodiment of this invention.

  In FIG. 8, the case where the return address is stored in the stack area 706 will be described.

  First, in a state where no data is stored in the stack area 706, the stack pointer (SP) indicates the area (2A00H) adjacent to the last area (29FFH) of the stack area as the stack pointer initial value. Note that the area indicated by the stack pointer initial value is an area that is not included in the stack area (in this embodiment, an area that is not included in the storage area of the user work RAM 104).

  Next, when saved data is stored in the stack area 706, or when a return address is stored in the stack area 706 due to an interrupt or a subroutine call, the area where the data (or address) is stored last is stored by the stack pointer. Will show.

  When the saved data is restored from the stack area 706 or when the return address is extracted (when the interrupt process or the subroutine process ends and the process returns to the caller), the data (indicated by the stack pointer at that time) (Or address) is fetched, and the storage area from which data is to be fetched next is indicated by the stack pointer.

  In this way, the return address stored in the stack area 706 is read first from the return address stored later.

  FIG. 8 shows a state in which, when the stack pointer points to the third return address, a new interrupt or subroutine call occurs and the return address is stored as the fourth return address. Thereafter, the storage area (29F8H) of the fourth return address is indicated by the stack pointer.

  FIG. 9 is a flowchart of the power-on process of each device (game control device 100, payout control device 210, and effect control device 150) according to the embodiment of the present invention.

  Specifically, FIG. 9A is a flowchart of the power-on process of the game control apparatus 100, and FIG. 9B is a flowchart of the power-on process of the payout control apparatus 210. C) is a flowchart of the power-on process of the effect control device 150.

  This will be described from the power-on process (FIG. 9A) of the game control apparatus 100. This power-on process is not a process executed by the CPU 102 from the beginning, but is a process executed first by various hardware provided in the game control device 100 and later executed by the CPU 102.

  First, a reset signal is transmitted from the power supply device 160 to the game control device 100 (901).

  This reset signal is input from the power supply device 160 to the security circuit 630 (see FIG. 6), the clear terminal (see FIG. 6) of the flip-flop circuit 641 of the RAM access restriction circuit 640, and the clear terminals of the communication ports 670 and 680. The Specifically, when the power is turned on, a voltage equal to or lower than a predetermined voltage (for example, 5V) is applied to these clear terminals for a predetermined time, and a reset signal is input. As a result, the reset signal is not input.

  When the reset signal is input from the power supply device 160, the security circuit 630 continues to output the reset signal to the reset terminal of the CPU core 102 until the security check process described later is completed, and waits for the CPU core 102 to start up. Let

  Since the reset signal is input to the clear terminals of the communication ports 670 and 680, the voltage levels of the D0 to D7 terminals and the Q0 to Q7 terminals of the communication ports 670 and 680 are controlled to be low, and various devices (general power SOL90, The communication ports 670 and 680 and the output I / F 106 are initialized by hardware by setting all the ports of the output I / F 106 connected to the big prize opening SOL38 etc. to 0 (902).

  Next, the RAM access restriction circuit 640 generates a RAM write prohibited state in which writing to the user work RAM 104 is restricted (903).

  Specifically, as described with reference to FIG. 6, since the reset signal is input to the clear terminal of the flip-flop circuit 641, a high-level signal is output from the output terminal Q (negative logic) of the flip-flop circuit 641. It becomes a state. As a result, whether a high level signal is input to the other input terminal of the OR gate circuit 642 or a low level signal is input, a high level signal is input to the write command input terminal of the user work RAM 104. As a result, a RAM write prohibition state occurs.

  Next, the security circuit 630 shown in FIG. 6 to which the reset signal is input executes self-diagnosis processing (904). The self-diagnosis process is a process for determining whether or not the security circuit 630 has been initialized.

  If it is determined by the self-diagnosis process that the security circuit 630 has been initialized, the security circuit 630 executes a security check process (905). As described with reference to FIG. 6, the security check process uses the validity confirmation information stored in the HW parameter ROM 603 (see FIG. 5) to check the validity of the program stored in the user program ROM 602 (see FIG. 5). This is a process for making a determination.

  When the security check process is executed in the process of step 905, the process proceeds to the main process of the game control apparatus 100. At this time, the security circuit 630 stops the reset signal output to the reset terminal of the CPU core 102, whereby the CPU core 102 is activated. For this reason, the main process of the game control device 100 is executed by the CPU core 102. The main process of the game control apparatus 100 will be described with reference to FIG.

  Next, the power-on process (FIG. 9B) of the payout control device 210 will be described. As described above, the payout control device 210 is different from the communication ports 670 and 680 in that it includes a receiving port (not shown) (included in the input / output I / F 216 input in FIG. 4). It is the same structure as the game control apparatus 100 shown. The same components as those of the game control apparatus 100 shown in FIG.

  First, a reset signal is transmitted from the power supply device 160 to the payout control device 210 (911). Note that the specific description of the process in step 911 is the same as the process in step 901.

  Since the reset signal is input to the payout control device 210, the voltage level of the output port (included in the input / output I / F 216 in FIG. 4) of the payout control device 210 is set to 0, and various devices (the payout motor 220). And the ports of the input / output I / F 216 connected to the launch control device 221 and the like are all set to 0, and the input / output I / F 216 is initialized by hardware (912).

  Next, a RAM write inhibition state in which writing to the RAM 214 is restricted by the RAM access restriction circuit 640 of the payout control device 210 occurs (913). Note that the specific description of the process of step 913 is the same as the process of step 903.

  Next, the security circuit 630 of the payout control device 210 to which the reset signal is input executes self-diagnosis processing (914). Note that the specific description of the process of step 914 is the same as the process of step 904.

  If it is determined by the self-diagnosis process that the security circuit 630 has been initialized, the security circuit 630 executes a security check process (915). Note that the specific description of the process in step 915 is the same as the process in step 905.

  Then, the payout control device 210 executes initialization processing at power-on (916). The initialization process at power-on is a process for initializing the RAM 214 and the like, and is executed by the CPU 212. Further, before the RAM 214 is initialized, the RAM write prohibition state generated in the process of step 913 is canceled, and the RAM 214 becomes a RAM writable state.

  Next, the payout control device 210 allows the game control device to accept data from a reception port (not shown) (connected to the discharge control communication port 670 of the game control device 100 in FIG. 6). A state in which the command from 100 can be received is generated (917).

  Then, the payout control device 210 takes in the data transmitted from the game control device 100 from the reception port (918).

  Regarding the processing of step 918, the configuration of the payout control device 210 is almost the same as that of the game control device 100, and will be described with reference to FIG. 6. This output port (game) is output by the output selection circuit 612 of the payout control device 210. When connected to the discharge control communication port 670 of the control device 100 is selected, the data of D0 to D7 output from the discharge control communication port 670 of the game control device 100 is fetched, and the fetched data is paid out. The data is output to the data bus 690 of the device 210.

  Then, the CPU 212 of the payout control device 210 determines whether or not the data fetched by the reception port is an initialization command (919).

  If it is determined in step 919 that the data captured by the communication port is not an initialization command, the process returns to step 918, and the processing in step 918 is executed until the initialization command is captured.

  On the other hand, if it is determined in step 918 that the data fetched by the receiving port is an initialization command, the payout control device 210 executes initialization processing at the start of communication (920), and payout control. The apparatus main process is started.

  Next, the power-on process (FIG. 9C) of the effect control device 150 will be described. As described above, the payout control device 210 is provided with a receiving port (not shown) instead of the communication ports 670 and 680, and the gaming arithmetic processing device 600 is not provided with the RAM access restriction circuit 640. Is the same configuration as the game control device 100 shown in FIG. The same components as those of the game control apparatus 100 shown in FIG.

  First, a reset signal is transmitted from the power supply device 160 to the effect control device 150 (921). Note that the specific description of the process of step 921 is the same as the process of step 901.

  Since the reset signal is input to the effect control device 150, the reception port of the effect control device 150 is initialized by hardware (922).

  Then, the effect control device 150 executes an initialization process when the power is turned on (923). The initialization process at power-on is a process for initializing the RAM 154 and the like, and is executed by the CPU 152.

  Next, the effect control device 150 generates a state in which a command from the game control device 100 can be received by permitting the reception port to take in data (924).

  Then, the effect control device 150 takes in the data transmitted from the game control device 100 from the reception port (925).

  Regarding the processing of step 925, the configuration of the effect control device 150 is almost the same as the configuration of the game control device 100, and will be described with reference to FIG. 6. This output port (game) is output by the output selection circuit 612 of the effect control device 150. When connected to the production control communication port 680 of the control device 100 is selected, the data D0 to D7 output from the production control communication port 680 of the game control device 100 is fetched, and the fetched data is paid out. The data is output to the data bus 690 of the device 210.

  Then, the CPU 152 of the effect control device 150 determines whether or not the data captured by the reception port is an initialization command (926).

  If it is determined in step 926 that the data fetched by the receiving port is not an initialization command, the process returns to step 925, and the processing in step 925 is executed until the initialization command is fetched.

  On the other hand, if it is determined in the process of step 926 that the data captured by the reception port is an initialization command, the effect control device 150 executes an initialization process at the start of communication (927), and the effect control. The apparatus main process is started.

  Next, game control device main processing executed by the CPU 102 of the game control device 100 will be described with reference to FIGS. 10 and 11.

  FIG. 10 is a flowchart of the first half of the game control apparatus main process according to the embodiment of the present invention, and FIG. 11 is a flowchart of the second half of the game control apparatus main process according to the embodiment of the present invention.

  First, the game control device 100 prohibits interruption to the CPU 102 (1001).

  Then, the game control device 100 sets a stack pointer at a predetermined address (stack pointer initial value described above with reference to FIG. 8) in the stack area 706 shown in FIG. 8 (1002), and sets an interrupt mode. (1003). The interrupt mode allows the CPU 102 to process an interrupt request from a built-in device and to set a position for executing the interrupt request process in a program.

  Next, the game control apparatus 100 takes in the state of the RAM clear SW signal from the input I / F 105 and stores the state of the fetched RAM clear SW signal in the register of the CPU 102 (1004).

  And the game control apparatus 100 performs the delay process which does not use RAM104 (1005). This delay process is a process that waits for a predetermined time, and specifically, is a process that continues to decrement until a predetermined number becomes zero in a storage area where a checksum is not calculated. Details of the delay processing will be described with reference to FIGS.

  Next, the game control device 100 takes in the state of the RAM clear SW signal again from the input I / F 105 and stores the state of the fetched RAM clear SW signal in the register of the CPU 102 (1006). Note that the CPU 102 stores the RAM clear SW signal state in step 1004 and the register clear area that stores the RAM clear SW signal state in step 1004 so that the CPU 102 can compare the states of the two RAM clear signals. The register areas to be used are different areas.

  Next, the game control device 100 sets the RAM write prohibition state generated in the process of step 903 to a RAM writable state (1007).

  Specifically, a clock signal is input from the output control circuit 612 to the clock terminal of the flip-flop circuit 641 in accordance with a command from the CPU 102, and the signal level of the signal line connected to the data terminal of the flip-flop circuit 641 is set to a high level. To. As a result, a high level signal is output from the output terminal Q (positive logic) of the flip-flop circuit 641, and a low level signal is output from the output terminal Q (negative logic). When a low level signal is input, the RAM becomes writable.

  Next, the game control device 100 executes various setting processes using the stack area 706 (1008). This setting process is, for example, a process of setting initial data in various storage areas necessary for game control by calling a subroutine or a function. These subroutines and functions are called from a plurality of locations described in the game control program, and contribute to reducing the capacity of the game control program. On the other hand, when a subroutine or function is called, processing for saving the return address in the stack area 706 is required as described above.

  Then, the game control apparatus 100 compares the state of the RAM clear SW signal stored in the register in the process of Step 1004 with the state of the RAM clear SW signal stored in the register in the process of Step 1008, and determines which RAM It is determined whether the state of the clear SW signal also indicates that the RAM clear SW 162 has been operated (1009).

  In the processing of step 1009, since it is determined whether or not the RAM clear SW 162 has been operated based on the state of the RAM clear signal acquired at different timings, erroneous determination due to noise or the like can be prevented.

  If it is determined in step 1009 that the RAM clear SW 162 has been operated, the game control device 100 initializes all storage areas of the user work RAM 104 (1010).

  Then, the game control device 100 transmits an initialization command signal to the payout control device 210 and the effect control device 150 (1011), and proceeds to the processing of step 1017 shown in FIG.

  On the other hand, when it is determined in step 1009 that the RAM clear SW 162 has not been operated, the game control device 100 confirms that the power is shut down in the first power failure recovery area 701 and the second power failure recovery area 704 of the user work RAM 104. It is confirmed whether the flag is stored (more precisely, whether the power shutoff confirmation flag is on) (1012).

  Then, the game control device 100 determines whether or not the power-off process has been executed correctly when the power supply was stopped immediately before (1013). Specifically, in the game control device 100, when the power shutdown confirmation flag is stored in both the first power failure recovery area 701 and the second power failure recovery area 704, the power shutdown process is correctly executed. On the other hand, when the power shutdown confirmation flag is not stored in at least one of the first power failure recovery area 701 and the second power failure restoration area 704 (when at least one power interruption confirmation flag is OFF). Determines that the power-off process is not correctly executed.

  If it is determined in step 1013 that the power-off process has been executed correctly, the game control apparatus 100 determines that the first workout recovery area 701, work area 702, checksum area 703, and 2 Checksum is calculated using the power failure recovery area 704, and it is verified whether or not the calculated checksum matches the checksum stored in the checksum area 703 (1014).

  The checksum stored in the checksum area 703 is checked using the first power failure recovery area 701, work area 702, checksum area 703, and second power failure recovery area 704 of the user work RAM 104 when a power failure is detected. The sum is calculated and stored.

  That is, the process of step 1014 is a process of collating whether the information stored in the user work RAM 104 at the time of power failure detection matches the information stored in the user work RAM 104 at the time of power-on.

  Then, it is determined whether or not the collation result of the processing in step 1014 matches the calculated checksum and the checksum stored in the checksum area 703 (1015).

  If it is determined in step 1015 that the checksum calculated in step 1014 does not match the checksum stored in checksum area 703, that is, the information stored in user work RAM 104 when a power failure is detected If the information stored in the user work RAM 104 at the time of power-on does not match, the game control device 100 proceeds to the process of step 1010, initializes all areas of the user work RAM 104, and in the process of step 1011 An initialization command is transmitted to the payout control device 210 and the effect control device 150.

On the other hand, if it is determined in step 1015 that the checksum calculated in step 1014 matches the checksum stored in the checksum area 703 in step 1014, that is, the user work at the time of power failure detection. When the information stored in the RAM 104 matches the information stored in the user work RAM 104 at the time of power-on, the game control device 100 determines the area necessary for starting the game control device 100 (part of the user work RAM 104). Is initialized (1016). At this time, the power shutdown confirmation flag is erased in each of the first power failure restoration area 701 and the second power interruption restoration area 704 of the user work RAM 104 (more precisely, the power interruption confirmation flag is turned off in each area).
Then, the game control device 100 transmits an initialization command to the payout control device 210 and the effect control device 150 (1011).

  When these processes are completed, the initialization process related to the game control device 100 is completed. Next, the process proceeds to step 1017 shown in FIG.

  Next, after the initialization command is transmitted to the payout control device 210 and the effect control device 150 in the process of step 1011, the game control device 100 measures CTC (Counter Timer Circuit) for measuring various times and performing timer interrupts. Is started (1017), and a random number circuit for generating random numbers related to game control is initialized (1018). Then, the game control device 100 permits an interrupt to the CPU 102 that is prohibited in the process of Step 1001 (1019).

  Next, the game control device 100 executes an initial value random number update process for updating the initial value random number (1020). The initial value random number returns to the initial value when a random number counter related to game control (for example, a random number counter acquired at the timing of winning the start prize opening 34) reaches an upper limit value, but the initial value is determined. It is a random number to do.

  Then, the game control device 100 confirms whether or not a power failure detection signal has been input (1021), and determines whether or not the confirmation result in the processing of step 1021 indicates that a power failure detection signal has been input. (1022).

  If it is determined in step 1022 that the power failure detection signal has not been input, no power failure has occurred, and the process returns to step 1020.

  On the other hand, if it is determined in step 1022 that a power failure detection signal has been input, the game control device 100 prohibits interruption to the CPU 102 (1023), and lowers the voltage level of the output port of the output I / F 106. The level is set (1024).

  Next, the game control device 100 stores the power shutdown confirmation flag in the first power failure recovery area 701 and the second power failure restoration area 704 of the user work RAM 104 (more precisely, the power interruption confirmation flag is turned on in each area). (1025), the checksum is calculated using the first power failure recovery area 701, the work area 702, the checksum area 703, and the second power failure recovery area 704 of the user work RAM 104, and the calculated checksum is used as the checksum area. It is stored in 703 (1026).

  Next, the game control device 100 puts the user work RAM 104 into the RAM write prohibited state by the RAM access restriction circuit 640 (1027).

  Specifically, a clock signal is input from the output control circuit 612 to the clock terminal of the flip-flop circuit 641 in accordance with a command from the CPU 102, and the signal level of the signal line connected to the data terminal of the flip-flop circuit 641 is set to a low level. To. As a result, a low level signal is output from the output terminal Q (positive logic) of the flip-flop circuit 641, and a high level signal is output from the output terminal Q (negative logic). When a high level signal is input, the RAM write inhibit state is entered.

  Then, the game control device 100 stands by until the gaming machine 1 is turned off (1028). In addition, since the backup power supply is connected to the game control apparatus 100, even if a power failure occurs, the power supply is not immediately turned off.

  In the present embodiment, in the process of step 1014, the RAM is writable in the process of step 1007 before determining the validity of the user work RAM 104 at the time of power-off and the user work RAM 104 at the time of power-on. The timing for making the RAM writable state may be immediately before the initialization process of the user work RAM 104 in the process of step 1010 or 1016 performed according to the legitimacy of the process of step 1014 at the latest.

  As described above, when the power supply is cut off in the gaming machine 1, the user work RAM 104 is set to the RAM writing prohibited state after the necessary power-off process is executed, and the game machine 1 supplies power again. Even if the process returns, the user work RAM 104 is not immediately brought into the RAM writable state, the hardware initialization process is executed for a certain period of time, and the process of step 1010 or 1016 is performed according to the validity of the process of step 1014. Immediately before executing the initialization process of the user work RAM 104 in the process, by finally making the RAM writable state, it is possible to prevent inadvertent writing of the user work RAM 104 until the user work RAM 104 is initialized.

  Therefore, immediately before the validity determination in the process of step 1014 is performed, the RAM writing is in a prohibited state. Therefore, erroneous writing is performed in the user work RAM 104 after power-on, and an erroneous determination is made in the process of step 1014. Can be prevented.

  In the present embodiment, in order to execute various setting processes using the stack area 706 in the process of step 1008, the RAM write enabled state is set in the process of step 1007 before the validity determination process in the process of step 1014. ing.

  As a result, various setting processes using the stack area 706 that is not the target of the validity determination can be performed before the validity determination is performed, so that various settings of the game control device 100 can be performed at an early stage. Therefore, the game control apparatus 100 can be started up at a high speed, and the stack area 706 can be used to share a processing program, thereby reducing the program capacity.

  In FIG. 10, after the user work RAM 104 is initialized by the process of step 1010 or 1016, an initialization command signal is transmitted by the process of step 1015, but step 1008 before executing the validity determination in step 1014. An initialization command signal may be transmitted after execution of the process.

  In this case, since the validity determination in the process of step 1014 is not performed, the initialization command signal is transmitted using the stack area 706 that does not contribute to the validity determination or the register provided in the CPU 102.

  In the process of step 1010 or 1016, the process of step 1016, which is a process for initializing a partial area of the RAM 104, takes longer than the process of step 1010, which is a process for initializing the entire area of the RAM 104. The time for which the initialization command signal is transmitted differs depending on whether the processing of 1010 or the processing of step 1016 is performed.

  By transmitting the initialization command signal before executing the validity determination in the process of step 1014, the initialization command signal can be transmitted earlier than transmitting the initialization command signal in the process of step 1011. In addition, the initialization command signal can be transmitted in a certain time after the power is turned on.

  FIG. 12 is an explanatory diagram of the delay processing according to the embodiment of this invention.

  This delay processing is executed in step 1005 of FIG. 10, but at the time when the delay processing is executed, the RAM writing is prohibited so that the value of the user work RAM 104 cannot be updated. This is because the checksum stored at the time of the power failure immediately before is checked against the current checksum immediately after the power is turned on.

  For this reason, in the delay processing of the processing of step 1005 shown in FIG. 10, the user work RAM 104 including the storage area in which the validity is determined is not used, and other storage areas (determination targets that are not subject to the validity determination are included. The delay processing must be executed using the (external storage area). Therefore, the delay processing of this embodiment is executed using a register (general-purpose register) provided in the CPU core 102.

Hereinafter, delay processing using a register will be described. Since a Z80 CPU is used as the CPU core 102, description will be made using the registers and assembly language used in the Z80 CPU. First, line 1201 is used for the first processing of the delay processing. Correspondingly, “0400H” is loaded into the HL register in which the H register and the L register of the register of the CPU core 102 (see FIG. 6) are configured as one pair. Specifically, “04H” is loaded into the H register, and “00H” is loaded into the L register.

  Next, proceeding to line 1203, where the value of the HL register is decremented. When the row 1203 is executed for the first time, the value of the HL register is “03FFH”.

  The process then proceeds to line 1204, where the value stored in the H register is loaded into the A register.

  Then, proceeding to a row 1205, a logical sum of the A register and the L register is calculated. In line 1206, if the logical sum calculated in line 1205 is not zero, the process returns to line 1202. Accordingly, the processing in rows 1203 to 1206 is repeated until both the H register and the L register become “00H”.

  That is, in FIG. 12, “0400H” stored in the H register and L register used as the maintenance timer is decremented until “0000H”, and the decrement is performed 1024 times in total. During this time, the game control device main process shown in FIG. 10 waits in the process of step 1005, so that the activation of the game control device 100 is delayed.

  Further, during this delay process, the user work RAM 104 is not accessed at all. That is, the delay process can be executed without rewriting the value of the user work RAM 104 including the storage area where the validity is determined.

  FIG. 13 is an explanatory diagram of delay processing according to a modification of the embodiment of this invention.

  The delay process in FIG. 12 is performed without using the storage area of the user work RAM 104 at all. In this modification, the delay process is a target of validity determination in the storage area of the user work RAM 104. The first power outage recovery area 701, work area 702, checksum area 703, and second power outage recovery area 704 are not accessed, but processing is performed using the stack area 706 that is not subject to validity determination. Like to do.

  Therefore, in the case where the delay process is executed in the procedure of FIG. 13 in step 1005 of FIG. 10, it is necessary to set the user work RAM 104 in a RAM writable state before the execution of step 1005. For example, the process of changing to the RAM writable state in step 1007 in FIG. 10 is executed immediately before the process in step 1005.

  A delay process using the stack area 706 will be described below.

  First, a row 1301 corresponds to the first processing of the delay processing, and information stored in the A register and F register (flag register) of the CPU core 102 is saved in the stack area 706 as an AF register pair. Let

  In row 1302, the information stored in the H and L registers of the CPU core 102 is regarded as an HL register configured as one pair, and is saved in the stack area 706.

  In line 1303, “0400H” is loaded into this HL register. Specifically, “04H” is loaded into the H register, and “00H” is loaded into the L register.

  Next, proceed to line 1305, where the value of the HL register is decremented. When row 1305 is executed for the first time, the value of the HL register is “03FFH”.

  The process then proceeds to line 1306, where the value stored in the H register is loaded into the A register.

  Proceeding to row 1307, the logical sum of the A register and the L register is calculated. In line 1308, if the logical sum calculated in line 1307 is not zero, the process returns to line 1304. Therefore, the processing in rows 1305 to 1308 is repeated until both the H register and the L register become “00H”.

  In line 1308, if the logical sum calculated in line 1307 is zero, the process proceeds to line 1309, and the information stored in the H register saved in the stack area 706 is returned to the H register of the CPU core 102. Then, the information stored in the L register saved in the stack area 706 is returned to the L register of the CPU core 102.

  Then, the process proceeds to line 1310, the information stored in the A register saved in the stack area 706 is returned to the A register of the CPU core 102, and the information stored in the F register saved in the stack area 706 is returned to the CPU core 102. Return to F register.

  As described above, in the delay process of FIG. 13, the information stored in the A register, F register, H register, and L register of the CPU core 102 used in the delay process is stored in the stack area before the delay process is performed. The information stored in the A register, F register, H register, and L register can be prevented from being lost by the delay process.

  As described with reference to FIGS. 12 and 13, in this embodiment, the delay processing is realized by software using a region that does not contribute to the validity determination, that is, does not calculate the checksum, without using hardware. Therefore, it is possible to accurately determine the correctness in step 1014 shown in FIG. 10 and to realize it at a lower cost than the delay processing by hardware.

  12 and 13 is compared, the method of FIG. 13 is more effective when the number of registers that can be used by the CPU core 102 is small. However, it is desirable to prevent as much as possible that the storage areas of the first power failure recovery area 701, work area 702, checksum area 703, and second power failure recovery area 704, which are subject to the validity determination, are rewritten due to noise or the like. If this is the case, it can be said that the method of FIG. 12 in which the user work RAM 104 is in the RAM write-inhibited state throughout the delay process is superior.

  FIG. 14 is a flowchart showing timer interrupt processing according to the embodiment of the present invention. This timer interrupt process is executed by the CPU core 102 of the game control apparatus 100.

  When the power of the gaming machine is turned on, a game control device main process (see FIGS. 10 and 11) is executed. When a timer interrupt is generated at a predetermined time period (for example, a period of 4 milliseconds) by the CTC activated in the process of step 1017, the timer interrupt process is repeatedly executed by the CPU 102 of the game control device 100. However, all of these processes (processes 1412 to 1422) are not necessarily performed every time an interrupt occurs. For example, in the input / output process (S1412), the input signal is monitored every time, but the output process may be executed every other occurrence of an interrupt. That is, instead of completing all the processes in one interrupt process, the interrupt process may be repeatedly executed a plurality of times to complete a series of game control processes.

  In the timer interrupt process of this embodiment, first, the register data is saved (1411).

  Next, input / output processing is executed (1412). The input / output process includes an input process and an output process. In the input process, signals input from various sensors (special drawing start SW 34A, universal drawing start SW 31A, count SW 36A, winning opening SW 32A to 32N, overflow SW 109, out of ball SW 110, frame opening SW 111, etc.) via the input I / F 105. This is a process of performing processing such as chattering removal and determining input information.

  The output process is performed through the output I / F 106 based on the parameters set in the special figure game process (1419) and the general figure game process (1420), and the special figure display unit 120, the universal figure display unit 121, Signals for controlling the electric SOL 90 and the special winning opening SOL38 are output.

  As described above, the input process and the output process do not have to be executed simultaneously by a single timer interrupt.

  Next, command transmission processing for outputting (command) set in the transmission buffer in various processes to the effect control device 150 and the payout control device 210 is performed (1413). Specifically, an effect command signal (effect command) related to the special symbol variation display game is output to the effect control device 150, or a payout command signal (payout command) is output to the payout control device 124.

  The payout command will be described in detail with reference to FIG. 17, and the effect command will be described in detail with reference to FIG.

  Thereafter, a random number update process 1 is performed in which the value of the hit random number counter for determining the hit of the special symbol variation display game is incremented by 1 (1414). In addition, in this random number update process 1, 1 is also added to the value of the hit symbol random number counter for determining the stop symbol of the special symbol variation display game, and the random number per symbol for determining the hit of the normal symbol variation display game. .

  Next, the initial value of the random number is updated, and an initial value random number update process for breaking the temporal regularity of the random number is executed (1415). The initial value random number update process 1415 is the same as the initial value random number update process (1020) shown in FIG.

  Then, a random number update process 2 is performed in which the value of the variation display pattern random number counter for updating the random number for determining the variation display pattern in the decorative special symbol variation display game related to the special symbol variation display game is incremented by one (1416). .

  Next, in order to monitor whether or not a game ball has won a prize at each prize opening, a prize opening monitoring process is performed (1417). Specifically, it is determined whether or not a signal is input from the special chart start SW 34A, the general chart start SW 31A, the count SW 36A, and the winning openings SW 32A to 32N (whether or not a signal indicating detection of a game ball is input). Monitor. At this time, if the game ball is detected by the special figure start SW 34A, the special figure random number counter value (random number related to the result mode of the special symbol variation display game) is stored in the special figure start prize storage area, and the game by the normal figure start SW 31A is played. If a ball is detected, the usual figure random number counter value (random number related to the result pattern of the normal symbol variation display game) is stored in the usual figure start winning storage area.

  Thereafter, an error monitoring process is performed to monitor the clogging of the discharged balls and abnormalities of various switches and sensors (1418).

  Thereafter, a special figure game process (1419) for performing a process related to the special symbol variation display game and a general figure game process (1420) for performing a process related to the normal symbol variation display game are performed.

  The special symbol game processing (1419) is extracted based on the winning of the game ball to the start winning opening 34 detected by the special symbol start SW 34A, and is stored in the special symbol start winning memory (1417). It is determined whether or not the random number regarding the result of the special symbol variation display game extracted and stored in the process is hit, and the special symbol display device 120 executes the special symbol variation display game. The special figure starting winning memory stores the extracted random number as the starting winning memory when the game ball wins the starting winning opening 34 in a state where the variable display game cannot be immediately executed.

  In addition, a process for displaying the variation of the identification information corresponding to the display on the special figure display 120 is performed. If the extracted random number is a predetermined value, the hit state related to the special symbol is entered, and the variation display of the identification information stops at the hit symbol. Also, when the winning state is reached, the open state is such that the special variation winning device 36 can easily accept the game ball.

  The normal game process (1420) is extracted based on the passing of the game ball to the normal symbol start gate 31 detected by the normal symbol start SW 31A, and is stored in the normal symbol start winning memory (1417). It is determined whether or not the random symbol related to the result of the normal symbol variation display game extracted and stored in the above process is hit, and the normal symbol variation display game is executed by the general symbol display 121. If the common random number counter value is a predetermined value, a hit state related to the normal figure is entered, and a parameter is set for stopping the fluctuation display of the normal symbol in the win state.

  Next, the game control device 100 performs processing for editing a signal that is provided in the gaming machine 1 and that is output to a segment LED (a special display display 120 and a general display display 121) that displays various information related to the game (1421). ). Specifically, when the special symbol variation display game is started, the special symbol winning memory number obtained by subtracting the number of executions of the special symbol variation display game started this time is displayed on the special symbol memory display unit of the special symbol display 120. Edit the parameters for: Similarly, when the normal symbol variation display game is started, the normal symbol winning memory number obtained by reducing the number of times of execution of the normal symbol variation display game started this time is displayed on the general symbol display of the general symbol display 121. Edit the parameters.

  Thereafter, external information editing processing for editing external information for outputting the state of the gaming machine 1 to the management computer connected via the inspection apparatus connection terminal 107 is performed (1422). External information includes information related to the progress status of the variable display game, such as whether the symbol has been confirmed, winning, changing the probability, shortening the variable time, starting the variable display game, etc. It is. An error signal indicating that an error has occurred is also included.

  Next, the end of the timer interrupt process is declared (1423).

  Thereafter, a return process (1424) for restoring the temporarily saved register and a process for setting permission of the interrupt that has been prohibited are performed (1425). Then, the timer interrupt process is terminated, and the process returns to the game control apparatus main process (FIGS. 10 and 11). Then, the initial value random number update process and the like (the processes of steps 1020 to 1022 in FIG. 11) are repeated until the next timer interrupt occurs.

  FIG. 15 illustrates processing performed by the game control device 100, the payout control device 210, and the effect control device 150 when the power is turned on according to the embodiment of the present invention, and the timing of the states of the communication ports 670 and 680 provided in the game control device 100. It is a chart.

  When the reset signal is transmitted to the payout control communication port 680 and the effect control communication port 670, Q0 to Q0 provided in each of the payout control communication port 680 and the effect control communication port 670 are processed by the process of step 902 shown in FIG. By setting all the voltage levels of the Q7 terminal to the low level, the payout control communication port 680 and the effect control communication port 670 are changed from the undefined state (1501) to the initial state (1502).

  In the initial state of the payout control communication port 680 and the effect control communication port 670, the game control device 100 transmits an initialization command in the process of step 1011 shown in FIG. It continues until it is set to the production control communication port 670 (1503).

  On the other hand, when the reset signal is transmitted to the security circuit 630 of the game control apparatus 100, the self-diagnosis process is executed in the process of step 904 shown in FIG. 9, and the security check process is executed in the process of step 905 (1504). After the security check process is executed, the CPU 102 is activated, and the game control apparatus main process (FIGS. 10 and 11) is executed by the CPU 102.

  The CPU 102 fetches the first RAM clear signal (1505) before executing the delay process (1506) and fetches the second RAM clear signal (1507) after executing the delay process. In other words, the first RAM clear signal fetch (1505) and the second RAM clear signal fetch (1507) are executed with a delay process (1506) in between.

  As described above, since the delay process is executed during the RAM clear signal fetching executed at each time point 1505 and 1507, the chattering removal etc. fetched by the first RAM clear signal fetching is performed during the delay process. be able to.

  After waiting for processing in the delay processing (1506), initialization processing of the RAM 104 is performed in processing of steps 1016 and 1010 shown in FIG. 10 (1508), and an initialization command is transmitted in processing of step 1011. The game control is performed (1509).

  When normal game control is executed, a payout control command is set in the payout control communication port 680 in order to transmit a payout control command to the payout control device 210 in accordance with the gaming state (1510). Further, during the execution of the normal game control, the effect control command is set in the effect control communication port 670 in order to transmit the effect control command to the effect control device 150 according to the game state (1511).

  On the other hand, when the reset signal is transmitted to the security circuit of the payout control device 210, the security circuit of the payout control device 210 executes a self-diagnosis process in the process of step 914 shown in FIG. Check processing is executed (1512). After executing the security check process, the CPU 212 is activated, and the CPU 212 executes the initialization process at the time of power-on in the process of step 916 in FIG. 9 (1513). When the initialization process of the payout control device 210 is executed, the state of the receiving port of the payout control device 210 is set to a state in which an instruction from the game control device 100 can be received (1514).

  When the reset signal is transmitted to the production control device 150, the production control device 150 executes the initialization process at the time of power-on in the process of step 923 in FIG. 9 (1515). When the initialization process of the effect control device 150 is executed, the state of the reception port of the effect control device 150 is changed to a state in which an instruction from the game control device 100 can be received (1516).

  The game control apparatus 100 delays the execution start timing of the initialization process of the RAM 104 by executing the delay process. In other words, the timing for transmitting the initialization command to the effect control device 150 and the payout control device 210 is delayed by the delay process.

  For this reason, the delay process ensures sufficient time for the payout control communication port 680 and the effect control communication port 670 to maintain the initial state, during which the payout control device 210 and the effect control device 150 execute the initialization process. Then, it is possible to make the reception port of itself receive a command from the game control device 100.

  Therefore, by providing a delay process, as shown in FIG. 15, even if the gaming machine has a configuration in which the reset signal is simultaneously transmitted to the game control device 100, the payout control device 210, and the effect control device 150, hardware or the like The timing at which each control device starts to start can be appropriately set without providing the delay circuit configured as described above.

  Therefore, as shown in FIG. 15, first, the payout control communication port 680 and the effect control communication port 670 are maintained in the initial state, and in this state, the receiving ports of the payout control device 210 and the effect control device 150 are in a command receivable state. Then, it becomes possible to reliably execute transmission of the initialization command to the payout control device 210 and the effect control device 150.

  If the gaming machine 1 immediately after power-on, the payout control device 210 or the effect control device 150 receives the payout control communication port 680 and the effect control communication port 670 of the game control device 100 before the game control device 100 is maintained in the initial state. Since the signal level output from the payout control communication port 680 and the effect control communication port 670 is unstable when the command port is ready for command reception, the payout control device 210 or the effect control device 150 causes the unstable signal to be output. The level information may be erroneously received as a legitimate signal, which may cause a malfunction.

  Also, if an initialization command is transmitted from the game control device 100 to the payout control device 210 or the effect control device 150 before the receiving port of the payout control device 210 or the effect control device 150 becomes ready for command reception. The payout control device 210 and the production control device 150 cannot receive the initialization command, which may cause a malfunction.

  In particular, as in the gaming machine of the present embodiment, a configuration in which a command is transmitted from the game control device 100 to the payout control device 210 in a single direction, or a configuration in which a command is transmitted from the game control device 100 to the effect control device 150 in a single direction. In this case, since there is no way to confirm whether the commanded information is correctly transmitted, such a configuration is very effective.

  10 and 15 show an example in which the RAM clear signal is fetched twice, but may be a plurality of times. By executing the delay processing between the plurality of times, the time required for chattering removal of the RAM clear signal fetching immediately before the execution of the delay processing can be overlapped with the delay time by the delay processing, so that the processing becomes efficient.

  FIG. 16 is a flowchart for explaining a procedure when a command is transmitted from the game control device 100 to the effect control device 150 and the payout control device 210.

  In the present embodiment, when the initialization command signal is transmitted from the game control device 100 to the effect control device 150 and the payout control device 210, the normal control signal is sent from the game control device 100 to the effect control device 150 and the payout control device 210. A description will be given in comparison with a case where a command (production command signal, payout command signal) is transmitted.

  (A) of FIG. 16 is a flowchart in the case of transmitting an initialization command signal, and corresponds to the initialization command communication process in step 1011 of FIG. (B) of FIG. 16 is a flowchart in the case of transmitting a normal command (effect command signal, payout command signal), and corresponds to the command transmission processing in step 1413 of FIG.

  First, in (a) of FIG. 16, the initialization command signal transmitted first to the production control device 150 is selected (1601A), and the data corresponding to the mode (MODE) portion of the selected initialization command signal is produced. The data is output to the control communication port 670, and the output state is maintained for a predetermined time (1602A). The mode part will be described later.

  Next, the bit corresponding to the strobe (STB) signal of the production control communication port 670 is set to ON and the output state is maintained for a certain time (1603A), and then the bit corresponding to the strobe signal is set to OFF. The output state is maintained for a certain time (1604A).

  Next, data corresponding to the action (ACTION) part of the initialization command signal transmitted to the effect control device 150 is output to the effect control communication port 670, and the output state is maintained for a predetermined time (1605A). The action part will be described later.

  Next, the bit corresponding to the strobe (STB) signal of the effect control communication port 670 is set to ON, the output state is maintained for a certain time (1606A), and then the bit corresponding to the strobe signal is set to OFF. The output state is maintained for a certain time (1607A). Next, it waits for a predetermined time d (details will be described later) (1608A), and if there is an initialization command signal to be transmitted next (1609A), it returns to step 1601A and transmits the next initialization command signal. Are repeated (1601A to 1609A).

  If all initialization command signals have been transmitted to the production control device 150 at step 1609A, the process returns to step 1601A to select the initialization command signal to be transmitted first to the payout control device 210. Then, the processing of 1602A to 1609A is repeated. However, the initialization command signal to the payout control device 210 is output not to the production control communication port 670 but to the discharge control communication port 680, and the strobe (STB) signal also uses the bit of the discharge control communication port 680.

  After that, when all the initialization command signals have been transmitted to the payout control device 210 at the output step 1609A to the effect control communication port 670, the caller (the next processing of the initialization command communication processing at step 1011 in FIG. 11) Return to).

  On the other hand, in (b) of FIG. 16, it is determined whether it is timing to transmit the effect command signal to the effect control device 150 (1601 B), and if it is the transmission timing of the effect command signal, the mode (MODE) of the effect command signal to be transmitted. The data corresponding to the section is output to the production control communication port 670 and the output state is maintained for a certain time (1602B).

  Next, the bit corresponding to the strobe (STB) signal of the effect control communication port 670 is set to ON, the output state is maintained for a certain time (1603B), and then the bit corresponding to the strobe signal is set to OFF. The output state is maintained for a certain time (1604B).

  Next, data corresponding to the action (ACTION) part of the initialization command signal transmitted to the effect control device 150 is output to the effect control communication port 670, and the output state is maintained for a certain time (1605B).

  Next, the bit corresponding to the strobe (STB) signal of the effect control communication port 670 is set to ON, the output state is maintained for a certain time (1606B), and then the bit corresponding to the strobe signal is set to OFF. The output state is maintained for a certain time (1607B), and the process returns to the caller (the process next to the command transmission process in step 1413 in FIG. 14).

  On the other hand, if it is not time to transmit the production command signal to the production control device 150 in step 1601B, it is determined whether it is time to send the emission command signal to the emission control device 150 (1608B), and transmission of the emission command signal is performed. If it is timing, a discharge command signal is transmitted (1609B). At this time, the discharge command signal is output from the discharge control communication port 680 in the same procedure as the procedure of 1602B to 1607B described above.

  In step 1601B, if it is not time to transmit a discharge command signal to the discharge control device 150, and if the discharge command transmission processing in step 1608B is completed, the caller (next to the command transmission processing in step 1413 in FIG. Return to processing.

  FIG. 17 is an explanatory diagram of command signals transmitted from the game control device 100 to the payout control device 210 and the effect control device 150 according to the embodiment of this invention. In particular, FIG. 17A is an explanatory diagram of an initialization command signal transmitted from the game control device 100 according to the embodiment of the present invention to the payout control device 210 and the effect control device 150, and FIG. It is explanatory drawing of the payout command signal and effect command signal which are transmitted to the payout control apparatus 210 and the effect control apparatus 150 from the game control apparatus 100 of embodiment of this invention.

  First, the initialization command signal will be described with reference to FIG. This corresponds to the processing of the procedure according to the flowchart of FIG.

  The initialization command signal includes a mode (MODE) part and an action (ACTION) part, and is transmitted in the initialization command communication process of step 1011 shown in FIG.

  As shown in FIG. 16A, the initialization command communication process in step 1011 shown in FIG. 10 includes a plurality of transmission processes for transmitting the mode part and the action part until the transmission of the initialization command signal is completed. It is a loop process that is repeated once. In FIG. 17A, the initialization command signal is transmitted by repeating the transmission process three times.

  The Q0 to Q6 terminals of the communication ports 670 and 680 are used to transmit data of the mode part and the action part, and the Q7 terminal is used to transmit a strobe signal that is a timing signal for reading.

  In each transmission process, the strobe signal is output from the Q7 terminal for a predetermined time, and the mode part and the action part are transmitted from the Q0 to Q6 terminals. When the strobe signal is input from the Q7 terminal, the payout control device 210 or the effect control device 150 to be received takes in the mode part or action part input from the Q0 to Q6 terminals.

  As described above with reference to FIG. 16A, in the initialization command communication process, after executing the transmission process, the software timer delay process for waiting the process for software for a predetermined time (d) is executed, and the transmission process is performed again. Execute.

  On the other hand, if all the data of the initialization command signal is transmitted, the initialization command communication process is exited and the process returns to the game control apparatus main process shown in FIG.

  In FIG. 17A, software delay processing of time value d is executed every time an initialization command signal is transmitted. For this reason, the transmission cycle of the initialization command signal is f1, and the time until the transmission of all data of the initialization command signal is completed (the time until the third transmission process is completed) is T. ing.

  Next, a command signal transmitted to the payout control device 210 or the effect control device 150 at the normal time will be described with reference to FIG.

  This normal command signal is transmitted in the command transmission process of step 1413 shown in FIG.

  Transmission of all data of the command signal is completed by command transmission processing by a plurality of timer interruptions, without completion of transmission by command transmission processing by one timer interruption. In other words, the command signal is transmitted across a plurality of timer interruption processes. In FIG. 16B, it is assumed that the transmission of all data of the command signal is completed by the command transmission process with three timer interruptions.

  The execution period (f2) of each command transmission process is synchronized with the generation period of the timer interrupt and is a period of 4 milliseconds.

  In addition, the normal command signal includes a mode part and an action part, like the initialization command signal. In other words, the normal command signal and the initialization command signal have the same time during which the mode section is output, the time during which the action section is output, and the output time of the strobe signal, that is, the format is the same. It is common.

  Therefore, transmitting the data of the mode part and the action part from the Q0 to Q6 terminals of the communication ports 670 and 680 and outputting the strobe signal from the Q7 terminal is the same as in the case of the initialization command signal.

  In FIGS. 17A and 17B, when the initialization command signal sets the delay time (d) by the software delay processing of the loop processing, the transmission cycle (f1) of the initialization command signal is the normal command. It is set to be shorter than the signal transmission cycle (f2).

  For this reason, the initialization command signal can be transmitted at a higher speed than the normal command signal, and the time required to complete the transmission of all the data of the initialization command signal is the same as that of one normal command signal. This can be shorter than the time required to complete the data transmission.

  Therefore, it is possible to shorten the time from when the power is turned on until the payout control device 210 and the effect control device 150 perform control based on the normal command signal.

  FIG. 18 is an explanatory diagram of signals transmitted to the payout control apparatus 210 according to the embodiment of this invention.

  Signals transmitted to the payout control device 210 include an initialization command signal and a payout command signal that is a normal command signal, and these signals are transmitted in a common format including a mode portion and an action portion.

  First, the initialization command signal will be described.

  The initialization command signal is composed of a first half initialization command signal and a second half initialization command signal.

  The initialization command signal in the first half has a value of “40H” in the mode portion and any value from “00H to 7FH” in the action portion. The action part of the initialization command signal in the first half is a value corresponding to the authentication code set in the payout control device 210 (any value of “00H to 7FH”). It is assumed that a value corresponding to the authentication code set in the payout control device 210 is set in the RAM 104, for example.

  The output timing of the initialization command signal in the first half is when the game control apparatus 100 is powered on, and specifically, is the processing of step 1011 shown in FIG.

  In the initialization command signal in the latter half, the mode portion has a value of “40H” and the action portion has any value of “70FH to 00H”. The action part of the initialization command signal in the latter half is a negative logic value (inverted bit) of the value of the action part of the initialization signal in the first half.

  The output timing of the latter half of the initialization command signal is immediately after the output of the first half of the initialization command signal is completed.

  Upon receiving the first half initialization command signal, the payout control device 210 authenticates whether the value of the action part of the received initialization command signal matches the authentication code set in itself.

  When the value of the action part of the received initialization command signal does not match the authentication code set in itself, the payout control device 210 prohibits the control based on the normal command signal. That is, payout of game media based on the payout command signal is prohibited.

  On the other hand, when the value of the action part of the received initialization command signal matches the authentication code set in itself, the payout control device 210 receives the initialization command signal in the latter half and receives the initial It authenticates whether the negative logic value of the action part value of the commutation command signal matches the authentication code set in itself.

  If the value that is the negative logic of the action part of the received initialization command signal in the latter half does not match the authentication code set in itself, the latter initialization command signal has not been correctly received, Since there is a possibility that a disconnection has occurred between the game control device 100 and the payout control device 210, the payout control device 210 reports an error.

  Next, the payout command signal will be described.

  Fifteen payout control command signals are prepared corresponding to the number of game media to be paid out by the payout control device 210.

  The mode part of the payout command signal is “21H to 2FH”. Note that the second digit of the mode portion matches the number of game media whose payout command signal commands payout. The action part of the payout command signal is “5EH to 50H”. This action part is a negative logic of the value of the mode part.

  For example, the mode part of the payout command signal for instructing payout of one game medium is “21H”, and the action part is “5EH”.

  The output timing of the payout command signal is output at the timing when the game ball wins the general winning opening 32, the start winning opening 34, and the special variable winning apparatus (large winning opening) 36.

  Further, when the payout control device 210 receives the payout command signal, the payout command signal received when the negative logic value of the mode portion of the received payout command signal does not match the negative logic value of the action portion. Dispensing of the number of game media corresponding to is not permitted.

  FIG. 19 is an explanatory diagram of signals transmitted to the effect control device 150 according to the embodiment of this invention.

  The signals transmitted to the effect control device 150 include an initialization command signal and an effect command signal that is a normal command signal, and are transmitted in a common format including these mode part and action part.

  First, the initialization command signal will be described.

  The initialization command signal includes a power-on notification signal indicating whether or not all areas of the RAM 104 have been initialized, and a series identification signal for identifying the series of the gaming machine 1. In addition, a signal for notifying the gaming state (low probability state, high probability state, winning suppression state, winning promotion state) of the gaming machine 1 at the time of the previous power interruption, and the number of special symbol winning memories at the time of the previous power interruption. The signal to be notified is also included in the initialization command signal.

  The mode part of the power-on signal indicating that all areas of the RAM 104 are initialized is “10H”, and the action part is “01H”. The fact that all areas of the RAM 104 have been initialized means that the processing of step 1010 shown in FIG. 10 has been executed.

  On the other hand, the mode part of the power-on signal indicating that all areas of the RAM 104 are not initialized, that is, a part of the area of the RAM 104 is initialized is “10H”, and the action part is “02H”. It is. That all areas of the RAM 104 have not been initialized, that is, that a part of the area of the RAM 104 has been initialized means that the processing of step 1014 shown in FIG. 10 has been executed.

  Therefore, when the process of step 1010 shown in FIG. 10 is executed, an initialization command signal in which the mode part is “10H” and the action part is “01H” is transmitted in the process of step 1011. When the process of step 1014 shown in FIG. 10 is executed, in step 1011, an initialization command signal having a mode part “10H” and an action part “02” H is transmitted.

  When the effect control device 150 receives a power-on signal indicating that all areas of the RAM 104 have been initialized, the effect control apparatus 150 displays on the display device 8 that all areas of the RAM 104 have been initialized.

  In addition, when receiving the power-on signal indicating that all areas of the RAM 104 are not initialized, the effect control apparatus 150 displays on the display device 8 that all areas of the RAM 104 have not been initialized.

  Further, the mode part of the series machine specific signal is “11H”, and the action part is “01H to 7FH”. The action part is one of values “01H to 7FH” corresponding to the series of gaming machines 1. Note that values corresponding to the series of gaming machines 1 are set in the ROM 103.

  In addition, the signal for notifying the gaming state (low probability state, high probability state, winning suppression state, winning promotion state) has a mode portion of “20H”, and the action portion has a game at the time of the previous power cut-off. A value associated with each state is stored. For example, the action part is “01H” in the low probability state, and the action part is “02H” in the high probability state. When receiving the signal for notifying the gaming state, the effect control device 150 performs an effect for notifying the gaming state.

  In addition, the signal for notifying the number of special symbol winning memories is “30H” in the mode portion and any value from “00H to 04H” in the action portion. The action part is a value corresponding to the starting memory number (0 to 4) at the time of the previous power shutdown. When receiving the start memory number effect command signal, the effect control device 150 displays the start memory number corresponding to the received start memory number effect command signal on a decoration start memory number display unit (not shown) of the display device 8.

  The output timing of these series machine specific signals, signals notifying the gaming state, and signals notifying the number of special symbol winning memories is when the power is turned on, and is transmitted in the process of step 1011 shown in FIG. Note that the output order of each of these signals and the power-on notification signal may be first or later. Furthermore, when there is other information to be notified from the game control device 100 to the effect control device 150 when the power is turned on, it may be transmitted together as an initialization command signal.

  As described above, in this embodiment, even when the types of initialization command signals (power-on notification signal, series machine identification signal, game state notification signal, and signal indicating the number of special symbol winning memories) increase, Since the initialization command signal is sequentially transmitted in the main processing loop, the time until all the initialization command signals are transmitted is shortened.

  Next, each effect command signal will be described.

  First, the variation start effect command signal for instructing the symbol variation start in the variation display game executed on the display device 8 will be described.

  The mode part of the change start effect command signal is “40H”, and the action part is any value of “01H to 7FH”. The action part is a value corresponding to the fluctuation time from the start of the symbol fluctuation display to the stop.

  When the effect control device 150 receives the change start effect command signal, the display device 8 starts changing the symbol display on the display device 8 and starts the change display game.

  The variation start effect command signal is transmitted at a timing at which the display device 8 starts the variation display of the symbol of the variation display game. Specifically, when the display device 8 finishes the variable display game, there is a start memory, or when the display device 8 does not execute the variable display game, the game ball is won at the start winning opening 34. is there.

  A stop symbol effect command signal for specifying a stop symbol in the variable display game on the display device 8 will be described.

  The mode part of the stop symbol effect command signal is “41H”, and the action part is any value of “01H to 7FH”. The action part is a value corresponding to the stop symbol.

  When receiving the stop symbol effect command signal, the effect control device 150 specifies the stop symbol of the variable display game on the display device 8 based on the received stop symbol effect command signal.

  The stop symbol effect command signal is transmitted when starting the variable display of the variable display game on the display device 8 and immediately after the transmission of the change start effect command signal is completed.

  A stop notification effect command signal for stopping the symbol whose change time has elapsed and whose change is being displayed will be described.

  The mode part of the stop notification effect command signal is “50H”, and the action part is “01H”.

  When receiving the stop notification effect command signal, the effect control device 150 stops the symbols that are variably displayed on the display device 8.

  The stop notification effect command signal is transmitted at the timing when the fluctuation time has elapsed.

  The jackpot related effect command signal transmitted during the occurrence of the special gaming state will be described.

  The mode portion of the jackpot related effect command signal is “60H”, and the action portion is any value of “01H to 7FH”. The action part is a value corresponding to the progress status of the special game state.

  When receiving the jackpot related effect command signal, the effect control device 150 performs an effect related to the special gaming state based on the received jackpot related effect command signal.

  An error-related effect command signal for notifying the occurrence of an error when an error occurs in the gaming machine 1 will be described.

  The mode part of the error-related effect command signal is “70H”, and the action part is one of the values “01H to 7FH”. The action part is a value corresponding to the error that has occurred.

  When receiving the error-related effect command signal, the effect control device 150 performs an effect for notifying the error that has occurred based on the error-related effect command signal.

  The error-related effect command signal is transmitted at a timing when the game control device 100 detects an error.

  Note that the above-described signal for notifying the gaming state (mode part = “20H”) is transmitted not only when the power is turned on, but also when the gaming state changes during normal gaming. For example, when a low probability state occurs during a game, a signal of mode portion = “20H” and an action portion = “01H” is transmitted, and when a high probability state occurs during a game, the mode portion = “ 20H "and action part =" 02H "are transmitted.

  In addition, the signal (mode part = “30H”) for notifying the number of special symbol winning memories mentioned above is not only when the power is turned on, but when the game ball wins the starting winning opening 34 during the normal game, the starting memory number The command signal is also transmitted when the value increases. For example, when a game ball is won at the start winning opening 34 and the start memory number is changed to “3” during the game, a signal of mode portion = “30H” and action portion = “03H” is transmitted.

  Accordingly, the signal for notifying the gaming state and the signal for notifying the number of special symbol winning memories also function as an effect command signal.

  According to the present embodiment, when power is turned on to the game control device 100, the delay process is performed without using the storage area of the RAM 104 whose validity is determined, so the communication ports 670 and 680 are maintained in the initial state. The subordinate control device (the effect control device 150 and the payout control device 210) can receive the command from the game control device 100 during the extended time period.

  As a result, immediately after the power is turned on, the communication port is in the initial state and held for a predetermined time. During this time, the dependent control device is ready to receive a command, so the communication port is in an unstable state when the dependent control device is started. It is possible to prevent erroneous data from being transmitted. In addition, by performing delay processing for a predetermined time using software, the state in which the communication port is in the initial state is maintained for a predetermined time, so that a configuration that is less expensive than a method using hardware is sufficient. Further, since the delay process is performed without using the validity determination storage area, the correctness determination process can also be performed accurately.

  Further, according to the present embodiment, the initialization command signal is transmitted by the game control device main processing loop, and the command signal to the subordinate control device at the normal time is transmitted by the timer interrupt processing. The transmission cycle can be made shorter than the normal command signal transmission cycle.

  As a result, the time until all initialization commands are transmitted is also shortened, so that it is possible to prevent a delay in starting the entire gaming machine when the power is turned on.

  The embodiment disclosed this time is illustrative in all points and is not restrictive. The scope of the present invention is shown not by the above description of the invention but by the scope of claims, and is intended to include all modifications within the scope and meaning equivalent to the scope of claims.

  As described above, the present invention can be applied to a gaming machine including a game control device and a subordinate control device that performs control according to a command from the game control device.

1 gaming machine 2 body frame (outer frame)
3 Front Frame 4 Hinge 5 Game Board 6 Game Device 8 Display Device 31 Normal Symbol Start Gate 32 General Winning Port 33 Regular Variable Winning Device 34 Start Winning Port 36 Special Variable Winning Device (Large Winner)
DESCRIPTION OF SYMBOLS 100 Game control apparatus 150 Production control apparatus 210 Delivery control apparatus 600 Game arithmetic processing apparatus 640 RAM access control circuit 641 Flip-flop circuit 642 OR gate circuit 670 Production control communication port 680 Delivery control communication port 701 First power failure recovery area 702 Work area 703 Checksum area 704 Second power failure recovery area 705 Unusable area 706 Stack area

Claims (7)

In a gaming machine capable of generating a special game state in which an auxiliary game is executed in a game area based on the establishment of a predetermined start condition and a privilege is given to a player in accordance with the result of the auxiliary game,
A game control device for comprehensively controlling games in the game area;
A subordinate control device that performs necessary control related to the gaming machine in response to a command from the gaming control device,
The game control device includes:
A communication port for outputting a command to the subordinate control device;
Initialization means for setting the communication port in an initial state in response to a predetermined activation signal;
Arithmetic processing means for performing required arithmetic processing by a game control program;
Information that is updated by the arithmetic processing means is stored, and storage means that can store the stored information even if power supply to the gaming machine is stopped,
Legitimacy judging means for judging legitimacy of information stored and held in the storage means after generation of the activation signal;
Timer counting means for timing a maintenance timer for maintaining the communication port in the initial state for a predetermined time, and
The slave control device is activated while the communication port maintains the initial state, and enters a command receivable state in which a command from the communication port can be received.
The gaming machine according to claim 1, wherein the timer timing unit counts the maintenance timer without updating the information stored in the storage unit whose validity is determined by the validity determination unit. The game control device is provided with a non-determination storage area in which updatable information is stored and which is not subject to validity determination by the validity determination means,
2. The gaming machine according to claim 1, wherein the timer timing unit counts the maintenance timer using the non-determination target storage area.   The gaming machine according to claim 2, wherein the non-determination storage area is a register provided in the arithmetic processing unit. The game control device includes:
Update restriction means for restricting update of information stored in the storage means;
Storage means initialization means for initializing the storage means in accordance with the validity determined by the validity determination means,
The update restriction means restricts the update of the storage means by the arithmetic processing means when the activation signal is generated, and updates the storage means when the storage means is initialized by the storage means initialization means. The game machine according to any one of claims 1 to 3, wherein the restriction is released.   5. The gaming machine according to claim 4, wherein the update restricting means restricts updating of the storage means while the timer timing means keeps counting the maintenance timer. The storage means includes a stack area for saving information,
The validity determination means determines the validity of information stored in an area other than the stack area of the storage means,
The update restricting means cancels the restriction of the update of the storage means before the validity determining means determines the validity,
5. The gaming machine according to claim 4, wherein the arithmetic processing means executes a setting process based on the stack area when the update restriction of the storage means is released by the update restriction means. Initialization instruction receiving means for receiving an initialization instruction for initializing all areas of the storage means,
The arithmetic processing means uses the storage means to perform a read process for reading the initialization instruction from the initialization instruction receiving means in order to confirm whether or not the initialization instruction receiving means has received the initialization instruction. Run multiple times without
The gaming machine according to claim 1, wherein the timer timing unit counts the maintenance timer during the reading process that is executed a plurality of times.

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