JP3813125B2 - 可変フルスケールを有するマルチビット・シグマデルタ・アナログ・ディジタル変換器 - Google Patents
可変フルスケールを有するマルチビット・シグマデルタ・アナログ・ディジタル変換器 Download PDFInfo
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- JP3813125B2 JP3813125B2 JP2002563604A JP2002563604A JP3813125B2 JP 3813125 B2 JP3813125 B2 JP 3813125B2 JP 2002563604 A JP2002563604 A JP 2002563604A JP 2002563604 A JP2002563604 A JP 2002563604A JP 3813125 B2 JP3813125 B2 JP 3813125B2
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- Prior art keywords
- gain
- analog
- digital
- quantizer
- full scale
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
- H03M3/478—Means for controlling the correspondence between the range of the input signal and the range of signals the converter can handle; Means for out-of-range indication
- H03M3/48—Means for controlling the correspondence between the range of the input signal and the range of signals the converter can handle; Means for out-of-range indication characterised by the type of range control, e.g. limiting
- H03M3/482—Means for controlling the correspondence between the range of the input signal and the range of signals the converter can handle; Means for out-of-range indication characterised by the type of range control, e.g. limiting by adapting the quantisation step size
- H03M3/484—Means for controlling the correspondence between the range of the input signal and the range of signals the converter can handle; Means for out-of-range indication characterised by the type of range control, e.g. limiting by adapting the quantisation step size by adapting the gain of the feedback signal, e.g. by adapting the reference values of the digital/analogue converter in the feedback path
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
- H03M3/478—Means for controlling the correspondence between the range of the input signal and the range of signals the converter can handle; Means for out-of-range indication
- H03M3/48—Means for controlling the correspondence between the range of the input signal and the range of signals the converter can handle; Means for out-of-range indication characterised by the type of range control, e.g. limiting
- H03M3/482—Means for controlling the correspondence between the range of the input signal and the range of signals the converter can handle; Means for out-of-range indication characterised by the type of range control, e.g. limiting by adapting the quantisation step size
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Description
本願は、2001年2月8日に出願された米国仮特許出願第60/267,327号の優先権を主張するものである。該仮特許出願の全記載内容を本願明細書の一部としてここに援用する。
Claims (13)
- 量子化器と、ループフィルタ回路と、ディジタル・アナログ・フィードバック回路とを有するマルチビットシグマデルタアナログディジタル変換器の入力フルスケールレベルを変える方法であって、
前記量子化器、ループフィルタ回路及びディジタル・アナログ・フィードバック回路は、これらによってもたらされる第1の利得を有し、
前記量子化器及びループフィルタ回路は、これらによってもたらされる第2の利得を有し、
前記方法は、
(a)前記ディジタル・アナログ・フィードバック回路のフルスケールを変えるステップと、
(b)前記量子化器の閾値を変えることにより前記量子化器とループフィルタ回路の第2の利得を、前記ディジタル・アナログ・フィードバック回路のフルスケールに反比例して変え、前記第1の利得を一定のレベルに維持するステップと、
を含む、方法。 - 請求項1に記載の方法において、
前記ディジタル・アナログ・フィードバック回路の出力から前記ループフィルタ回路を通過して前記量子化器の入力までと、定められた回路パスは、これらによってもたらされる第3の利得を有し、前記ステップ(b)は、前記回路パスの第3の利得を変更して第1の利得を一定のレベルに維持する、方法。 - 請求項1に記載の方法において、前記マルチビット・シグマデルタ・アナログ・ディジタル変換器は可変利得素子を含み、前記ステップ(b)は該可変利得素子の利得を変えることにより前記第1の利得を一定のレベルに維持する、方法。
- 請求項3に記載の方法において、前記ステップ(b)は、前記可変利得素子の利得を変更し、前記量子化器の複数の閾値を変えて、前記第1の利得を一定のレベルに維持する、方法。
- 請求項4に記載の方法であって、さらに、
(c)前記可変利得素子の利得を追跡するステップと、
(d)追跡した利得値にもとづき、前記ディジタル・アナログ・フィードバック回路のフルスケールをさらに修正するステップと、
を含む、方法。 - マルチビット・シグマデルタ・アナログ・ディジタル変換器であって、
量子化器と、
前記量子化器に接続され、ディジタル・アナログ・フィードバック回路を含むループ回路と、
基準信号を提供する基準信号源と、
を含み、
前記量子化器及び前記ループ回路は前記第1の利得を有し、
前記ディジタルアナログ回路は、前記基準信号に応答して、その第1の利得を変更し、
前記量子化器は、前記基準信号に応答して、その閾値を変えて第1の利得を一定のレベルに維持する、マルチビット・シグマデルタ・アナログ・ディジタル変換器。 - 請求項6に記載のマルチビット・シグマデルタ・アナログ・ディジタル変換器において、
前記ループ回路は可変利得素子と、
利得制御信号とフルスケール制御信号とを提供する利得制御信号源と、
を含み、
前記可変利得素子は、前記利得制御信号に応答して、第1の利得を変更する、マルチビット・シグマデルタ・アナログ・ディジタル変換器。 - 請求項6に記載のマルチビット・シグマデルタ・アナログ・ディジタル変換器において、
前記可変利得素子は、前記ディジタル・アナログ・フィードバック回路のフルスケールの変更に反比例してその利得を変更し、前記第1の利得を一定のレベルに維持する、マルチビット・シグマデルタ・アナログ・ディジタル変換器。 - 請求項7に記載のマルチビット・シグマデルタ・アナログ・ディジタル変換器において、前記可変利得素子は、可変利得増幅器である、マルチビット・シグマデルタ・アナログ・ディジタル変換器。
- 請求項7に記載のマルチビット・シグマデルタ・アナログ・ディジタル変換器において、前記可変利得素子は、可変抵抗である、マルチビット・シグマデルタ・アナログ・ディジタル変換器。
- 請求項7に記載のマルチビット・シグマデルタ・アナログ・ディジタル変換器において、前記可変利得素子は、可変容量である、マルチビット・シグマデルタ・アナログ・ディジタル変換器。
- 請求項7に記載のマルチビット・シグマデルタ・アナログ・ディジタル変換器において、前記可変利得素子は、可変相互コンダクタンスである、マルチビット・シグマデルタ・アナログ・ディジタル変換器。
- 請求項7に記載のマルチビット・シグマデルタ・アナログ・ディジタル変換器において、前記可変利得素子は、可変減衰器である、マルチビット・シグマデルタ・アナログ・ディジタル変換器。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US26732701P | 2001-02-08 | 2001-02-08 | |
PCT/US2002/003851 WO2002063773A2 (en) | 2001-02-08 | 2002-02-05 | Multi-bit sigma-delta analog to digital converter with a variablefull scale |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004533136A JP2004533136A (ja) | 2004-10-28 |
JP3813125B2 true JP3813125B2 (ja) | 2006-08-23 |
Family
ID=23018319
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2002563604A Expired - Lifetime JP3813125B2 (ja) | 2001-02-08 | 2002-02-05 | 可変フルスケールを有するマルチビット・シグマデルタ・アナログ・ディジタル変換器 |
Country Status (6)
Country | Link |
---|---|
US (1) | US6567025B2 (ja) |
EP (1) | EP1402647B1 (ja) |
JP (1) | JP3813125B2 (ja) |
CN (1) | CN1582534B (ja) |
DE (1) | DE60210972T2 (ja) |
WO (1) | WO2002063773A2 (ja) |
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WO2005002059A1 (en) * | 2003-06-27 | 2005-01-06 | Koninklijke Philips Electronics N.V. | An analog-to-digital-converter comprising a sigma-delta-modulator and receiver with such analog-to-digital-converter |
US6937176B2 (en) * | 2003-09-30 | 2005-08-30 | Koninklijke Philips Electronics, N.V. | Ultrasonic signal acquisition in the digital beamformer |
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US6999011B2 (en) * | 2003-12-15 | 2006-02-14 | Finisar Corporation | Microcode driven adjustment of analog-to-digital converter |
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US7193548B2 (en) * | 2004-01-30 | 2007-03-20 | Hrl Laboratories, Llc | Switching arrangement and DAC mismatch shaper using the same |
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-
2002
- 2002-02-05 JP JP2002563604A patent/JP3813125B2/ja not_active Expired - Lifetime
- 2002-02-05 DE DE60210972T patent/DE60210972T2/de not_active Expired - Lifetime
- 2002-02-05 WO PCT/US2002/003851 patent/WO2002063773A2/en active IP Right Grant
- 2002-02-05 US US10/071,983 patent/US6567025B2/en not_active Expired - Lifetime
- 2002-02-05 EP EP02706216A patent/EP1402647B1/en not_active Expired - Lifetime
- 2002-02-05 CN CN02804706.0A patent/CN1582534B/zh not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP2004533136A (ja) | 2004-10-28 |
US20020105449A1 (en) | 2002-08-08 |
CN1582534B (zh) | 2010-05-12 |
DE60210972D1 (de) | 2006-06-01 |
DE60210972T2 (de) | 2007-05-24 |
EP1402647B1 (en) | 2006-04-26 |
WO2002063773A2 (en) | 2002-08-15 |
CN1582534A (zh) | 2005-02-16 |
WO2002063773A3 (en) | 2004-01-22 |
EP1402647A2 (en) | 2004-03-31 |
US6567025B2 (en) | 2003-05-20 |
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EXPY | Cancellation because of completion of term |