JP3778228B2 - Command pulse generator - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a command pulse generator that generates a command pulse for driving a pulse motor.
[0002]
[Prior art]
Conventionally, in order to drive a pulse motor, a command pulse generator mounted on the controller board generates a command pulse for driving the pulse motor, and the pulse motor is driven based on the generated command pulse. ing.
Here, since the command pulse generator is mounted in the controller board as described above, the clock signal in the controller board is commonly used as a clock, and there is no need to synchronize again.
[0003]
[Problems to be solved by the invention]
In recent years, a system has been proposed in which controller boards and command pulse generators are distributed and connected by a high-speed transmission path, and is registered as a “distributed numerical controller” (Japanese Patent No. 1898840).
However, in such a system, there is a problem that a slight error occurs in the clock between the upper controller and the lower apparatus coupled by the high-speed transmission path.
The present invention has been made in view of the problems of the prior art as described above, and is capable of generating a command pulse in synchronization with the controller even when coupled to the controller via a transmission line. An object is to provide a pulse generator.
[0004]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides:
A counter that corrects the counting operation according to the first signal having a constant period that is input;
A semi-integrator that repeatedly performs an addition operation based on the input second signal and outputs an overflow caused by the addition operation;
A buffer for storing data input to the semi-integrator;
A Q buffer for presetting externally input data in the buffer;
A command pulse generator having a logic gate for generating and outputting a command pulse for driving a pulse motor based on a count value in the counter and a signal output from the semi-integrator,
The first signal is a signal synchronized with a clock signal in a host controller that gives a command to the command pulse generator;
The second signal is a count value in the counter.
[0005]
Further, when the data set in the buffer is negative data, the signal output from the semi-integrator is inverted.
A counter for correcting the counting operation in accordance with the first signal having a constant period input;
A BRM that converts the input second signal into a serial signal and outputs the serial signal;
A buffer for storing data input to the BRM;
A Q buffer for presetting externally input data in the buffer;
A command pulse generator comprising a logic gate for generating and outputting a command pulse for driving a pulse motor based on a count value in the counter and a signal output from the BRM,
The first signal is a signal synchronized with a clock signal in a host controller that gives a command to the command pulse generator;
The second signal is a count value in the counter;
The BRM is cleared by the first signal.
[0006]
(Function)
In the present invention configured as described above, in the counter, the counting operation is performed based on a signal synchronized with the clock signal in the host controller that gives a command to the command pulse generator. In the semi-integrator, the count value in the counter Is added, and a command pulse for driving the pulse motor is generated based on the count value in the counter and the overflow caused by the addition operation in the semi-integrator.
Thus, since the count cycle of the counter is synchronized with the cycle of the semi-integrator, a command pulse synchronized with the host controller is generated even when the host controller and the command pulse generator are coupled by a transmission line. .
[0007]
Also, if the data set in the buffer is negative data, the data set in the buffer becomes 2's complement by inverting the signal output from the semi-integrator, and the command pulse consisting of negative data is Is output.
Further, when BRM is used instead of the semi-integrator, the same operation as described above occurs.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
FIG. 1 is a diagram showing an embodiment of a command pulse generator of the present invention, and FIG. 2 is a diagram showing a configuration of a semi-integrator 20 shown in FIG.
In this embodiment, as shown in FIG. 1, a counter 10 that corrects a count operation in accordance with a signal having a fixed period inputted from the outside, and an addition operation is repeatedly performed based on the count value in the counter 10, and the addition operation results. In the semi-integrator 20 that outputs an overflow, a buffer 30 that stores data input to the semi-integrator 20, a Q buffer 40 that presets data input from the outside in the buffer 30, and a counter 10 NAND gates 50a and 50b that respectively output signals obtained by inverting the logical product of the count value and the signal output from the semi-integrator 20, and the logical sum of the RXINT signal transmitted from the outside and the overflow in the counter 10 A NOR gate 60 for outputting the inverted signal to the counter 10, and a NOR gate; A delay circuit 70 to be input to the Q buffer 40 delays the signal output from the preparative 60 for a predetermined time, the inverter gates 80a, is composed of a 80b. As shown in FIG. 2, the semi-integrator 20 in the present embodiment is a DDA (Digitai Dif-ferentiai Anaiyzer) composed of an adder 21 and a D-FF 22, and is a known one.
[0009]
The operation of the command pulse generator configured as described above will be described below.
First, when the clock signal CP used in the host controller (not shown) is transmitted at a constant period, the count operation is performed in the counter 10 based on the transmitted clock signal CP. An RXINT signal synchronized with a clock signal used in the controller is also transmitted at a constant cycle, and the counter 10 corrects the counting operation based on the transmitted RXINT signal. Then, the count value in the counter 10 is input to the semi-integrator 20.
The overflow in the counter 10 is fed back to one input terminal of the NOR gate 60, and a signal obtained by inverting the logical sum of the RXINT signal and the overflow in the counter 10 is output to the counter 10 in the NOR gate 60. .
[0010]
Further, data is written in the Q buffer 40 by the / WRQ signal, and the data written in the Q buffer 40 moves to the buffer 30 in accordance with a signal output from the NOR gate 60.
When the count value in the counter 10 is input to the semi-integrator 20, an addition operation is performed in the semi-integrator 20. In the addition operation in the semi-integrator 20, the count value input from the counter 10 is determined in advance. In other words, when n pulses are input, the overflow is output as an output signal of the semi-integrator 20. Since this operation is a known one, further detailed description is omitted.
Here, if a pulse of 512 Kpps is output from the counter 10 as a count value and calculation is performed at a cycle of 2 msec, the frequency of a signal having a cycle of 2 msec is 500 Hz, so 512 K / 500 = 1024, that is, half If a 10-bit integrator is used for the integrator 20, the calculation is completed. This means that the content of the D-FF 22 becomes zero.
[0011]
When the calculation is completed, the same number of overflows as the data set in the semi-integrator 20 are generated and output.
Here, the overflow in the semi-integrator 20 may occur continuously. Therefore, only the overflow output from the semi-integrator 20 is not used as a command pulse, and the overflow generated in the semi-integrator 20 and the count value in the counter 10 are input to the NAND gates 50a and 50b. The logical product of the overflow generated in the semi-integrator 20 and the count value in the counter 10 is inverted, and the signal is output as a command pulse.
At this time, the setting data is the number of moving pulses of 2 msec and is distributed by interpolating this time interval, and new data in the Q buffer 40 is set in the buffer 30 by the / INT signal output from the NOR gate 60. At the same time, new data is written into the Q buffer 40 in response to an interrupt signal / WRQ from the CPU.
[0012]
Hereinafter, the distinction between the positive and negative directions of the command pulses output from the NAND gates 50a and 50b will be described.
The MSB of the data in the buffer 30 is used as a data bit in the positive / negative direction.
When the data set in the buffer 30 is positive data, the calculation result A−B = Q (A and B are data values at the start and end of one cycle of calculation) is directly semi-integrated. The overflow is input to the NAND gate 50a.
On the other hand, when the data set in the buffer 30 is negative data, the overflow in the semi-integrator 20 is inverted by the inverter 80b and used as in the “bidirectional BRM circuit” (utility model No. 2059608). As a result, the data set in the buffer 30 is set to 2's complement and output as a command pulse composed of negative data.
[0013]
In the command pulse generator configured as described above, if the error between the clock in the host controller and the clock in the command pulse generator shown in FIG. 1 is normally about 100 PPM, it can be absorbed. That is, when the RXINT signal is input at a cycle of 2 msec, the error that can be absorbed is 200 PPM, and the error of 0.4 μsec can be absorbed.
(Other embodiments)
The command pulse generator of the present invention can also be configured using known BRM (Binary Rate Multipliers).
FIG. 3 is a diagram showing another embodiment of the command pulse generator of the present invention.
In this embodiment, a BRM 120 is provided instead of the semi-integrator 20 as compared with that shown in FIG. 1, and a clear signal generated based on the / RES signal and the / RXINT signal input from the outside is provided. The only difference is that the data that is input and stored in the Q buffer 40 moves to the buffer 30 based on the signal output from the EXOR gate 130b, and the other components are the same. Omitted.
[0014]
In the present embodiment, synchronization with a controller (not shown) is achieved by clearing the BRM 120 in synchronization with an externally input / RXINT signal.
[0015]
【The invention's effect】
Since the present invention is configured as described above, the following effects can be obtained.
Since the count cycle of the counter is synchronized with the cycle of the semi-integrator, even when the host controller and the command pulse generator are coupled by a transmission line, the counter is synchronized with the host controller. Command pulses can be generated.
According to the second aspect of the present invention, when the data set in the buffer is negative data, since the signal output from the half integrator is inverted, the data set in the buffer is a 2's complement. A command pulse composed of negative data can be output.
[0016]
According to the third aspect, the same effect as the first aspect can be obtained.
[Brief description of the drawings]
FIG. 1 is a diagram showing an embodiment of a command pulse generator of the present invention.
FIG. 2 is a diagram showing a configuration of a semi-integrator shown in FIG.
FIG. 3 is a diagram showing another embodiment of the command pulse generator of the present invention.
[Explanation of symbols]
10 counter 20 half integrator 21 adder 22 D-FF
30 buffer 40 Q buffer 50a, 50b NAND gate 60 NOR gate 70 delay circuit 80a, 80b inverter 120 BRM
130a, 130b EXOR gate

Claims (3)

A counter that corrects the counting operation in accordance with the first signal having a constant period input;
A semi-integrator that repeatedly performs an addition operation based on the input second signal and outputs an overflow caused by the addition operation;
A buffer for storing data input to the semi-integrator;
A Q buffer for presetting externally input data in the buffer;
A command pulse generator having a logic gate for generating and outputting a command pulse for driving a pulse motor based on a count value in the counter and a signal output from the semi-integrator,
The first signal is a signal synchronized with a clock signal in a host controller that gives a command to the command pulse generator;
The command pulse generator, wherein the second signal is a count value in the counter. The command pulse generator according to claim 1, wherein
A command pulse generator for inverting the signal output from the semi-integrator when the data set in the buffer is negative data. A counter that corrects the counting operation in accordance with the first signal having a constant period input;
A BRM that converts the input second signal into a serial signal and outputs the serial signal;
A buffer for storing data input to the BRM;
A Q buffer for presetting externally input data in the buffer;
A command pulse generator comprising a logic gate for generating and outputting a command pulse for driving a pulse motor based on a count value in the counter and a signal output from the BRM,
The first signal is a signal synchronized with a clock signal in a host controller that gives a command to the command pulse generator;
The second signal is a count value in the counter;
The command pulse generator, wherein the BRM is cleared by the first signal.

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