JP2992306B2 - Line disconnection detection circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] In an apparatus having a decoder such as an audio codec,
A line disconnection detection circuit that detects a line disconnection on the input side of the decoder.The purpose of this circuit is to detect line disconnection due to clock disconnection and to cope with multiple transmission speeds, and to synchronize data input via the line. A differentiating means for differentiating a first control signal to be taken based on a clock extracted from a line, and a first control signal which is used when decoding data and has an equal cycle and an asynchronous relationship with the first control signal. A signal generating means for receiving a second control signal which is continuously output even when the line is disconnected and generating a third control signal used for monitoring the cycle of the differential output; And a period monitoring means for monitoring based on the control signal of No. 3 and detecting a line disconnection when the period is not normal.

[Industrial applications]

The present invention relates to a line disconnection detection circuit for detecting a line disconnection on the input side of a decoder in an apparatus having a decoder such as an audio codec.

[Conventional technology]

In an audio codec, when the input of a decoded data control signal for synchronizing clocks and data to the decoder side is stopped due to line disconnection, the output sound of the decoder oscillates, and the audio receiving side receives the sound. Therefore, when a line disconnection occurs, silence processing, that is, muting processing is forcibly performed.

FIG. 5 shows the configuration of the audio codec. In the figure, 511 is a voice codec, 521 is an encoder, 531 is a decoder, 541 is a line disconnection detection circuit, 551 is an AND gate, and 561 is an analog-digital conversion circuit (A / D circuit).
571 indicates a digital-analog conversion circuit (D / A circuit).

The audio codec 511 converts, for example, a voice analog signal input from a microphone (not shown) to digital data in a video conference system and sends the digital data to the line side, and also converts the digital data input from the line side into an audio analog signal. And supplies it to a speaker (not shown).

The encoder 521 encodes audio data input from the A / D circuit 561 by a high-efficiency encoding method such as adaptive differential encoding. The head position of the encoded data is synchronized by the encoded data control signal input from the line side, and the encoded data in which each bit is synchronized with the clock input from the line side is output.

Also, the decoder 531 is for decoding the decoded data input from the line side opposite to the encoder 521,
The head position of the decoded data is recognized by the decoded data control signal input from the line side, and each bit of the decoded data is fetched in synchronization with a clock input from the line side to perform a decoding process. The decoded data is further transmitted to an audio codec 511 via an AND gate 551 and a D / A circuit 571.
Output from

Further, the line disconnection detection circuit 541 performs line disconnection detection based on the decoded data control signal and the clock input to the decoder 531. When the line disconnection is detected, the logic of the signal input to the AND gate 551 is detected. To “0” (line disconnection detection signal)
Then, the data output from the encoder 531 is forcibly replaced with “0” and the muting process of the output sound is performed.

FIG. 6 shows a detailed configuration of the line disconnection detection circuit 541, and FIG. 7 shows its operation timing. In FIG. 6, 611 is a differentiating circuit, 613 and 631 are flip-flops (FF),
615 indicates a NAND gate, and 621 indicates a counter.

The differentiating circuit 611 periodically (eg, at a cycle of 125 μs)
The input decoded data control signal is differentiated by a clock, and the differentiated output is input to the counter 621 as a load pulse (FIGS. 7A, 7B, and 7C).
(C)). The counter 621 performs a counting operation in synchronization with a clock. When a load pulse is input, a predetermined initial value is set, and a line disconnection detection clock is output after a predetermined time equal to the cycle of the decoded data control signal. (FIG. 7 (d)). The flip-flop 631 takes in the decoded data control signal input to the input terminal D in synchronization with the rise of the line disconnection detection clock (FIG. 7 (e)). When the decoded data control signal is input normally and the clock is input at normal timing and the line disconnection detection clock is generated at normal intervals, the logic of the output signal of the flip-flop 631 is “ The state of "1" is maintained, and when a line disconnection occurs, this logic is changed to "0" and a line disconnection detection signal is output.

[Problems to be solved by the invention]

By the way, in the conventional method described above, when only the clock is not supplied due to the line disconnection and the line disconnection detection clock is not generated, the state before the line disconnection is maintained in the flip-flop 631, There is a problem that disconnection cannot be detected.

Further, the output timing of the line disconnection detection clock is determined by the initial value of the counter 621 captured by the load pulse. Therefore, when the transmission speed on the line side is changed and the period of the decoded data control signal is changed, the above-described initial value is used each time. Therefore, there is a problem that it is not possible to cope with a plurality of transmission speeds. Therefore, in order to cope with a plurality of transmission speeds, it is necessary to provide a counter corresponding to each transmission speed, or to add an initial value switching circuit corresponding to each transmission speed.

The present invention has been made in view of such a point, and an object of the present invention is to provide a line disconnection detection circuit which can detect a line disconnection due to a clock disconnection and can cope with a plurality of transmission speeds.

[Means for solving the problem]

FIG. 1 is a block diagram showing the principle of a line disconnection detection circuit according to the present invention.

In the figure, a differentiator 111 differentiates a first control signal for synchronizing data input via a line based on a clock extracted from the line.

The signal generation means 121 is used when decoding data, and receives a second control signal which has the same synchronization as the first control signal and has an asynchronous relationship with each other, and is continuously output even if the line is disconnected. , A third control signal used for monitoring the cycle of the differential output.

The cycle monitoring means 131 monitors the cycle of the differential output of the differentiating means 111 based on the third control signal, and if the cycle is not normal, detects line disconnection.

Therefore, as a whole, when at least one of the first control signal and the clock is not input, the line disconnection is detected.

(Operation)

When the first control signal is differentiated by the clock by the differentiating means 111, a differentiated output having a period equal to the first control signal is obtained. Further, a third control signal is generated by the signal generation unit 121 based on the second control signal used in the data decoding process. The second control signal is a control signal for determining a data cycle in the decoding process, and has a cycle equal to the first control signal and is asynchronous with each other. For example, the second control signal is obtained by dividing a clock in the apparatus. It is obtained. The third control signal is used to monitor the cycle of the differential output of the differentiating means 111. For example, the third control signal shifts the phase of the second control signal or does not perform any operation. Sent to 131. This second
Is a signal used for the decoding process, and is input regardless of line disconnection.

The cycle monitoring means 131 monitors the cycle of the differential output of the differentiating means 111 based on the third control signal, and when at least one of the first control signal and the clock is not input due to the line disconnection, the cycle monitoring means 131 described above. Is not normal, so it is detected as line disconnection.

According to the present invention, the period of a signal obtained by differentiating the first control signal with a clock is monitored based on the second control signal used for the decoding process. Line disconnection detection becomes possible.

Further, since the cycle of the second control signal used for the decoding process corresponds to the transmission rate, it is possible to correspond to a plurality of transmission rates without particularly changing the configuration.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 2 shows a configuration of a line disconnection detection circuit in one embodiment of the present invention.

The line disconnection detection circuit shown in FIG. 11 includes a differentiating circuit 211, a control signal generation circuit 221, and an access cycle detection circuit 241.

The differentiating circuit 211 includes a flip-flop (FF) 213 and a NAND gate 215, and is for differentiating the decoded data control signal by a clock.

The flip-flop 213 receives a decoded data control signal at an input terminal D and a clock at a clock terminal, and takes in the decoded data control signal in synchronization with the clock. The NAND gate 215 has one input terminal to which the decoded data control signal is input and the other input terminal to which the inverted output from the output terminal of the flip-flop 213 is input, and outputs a signal obtained by inverting the logical product of two inputs. Output as a control pulse.

The control signal generation circuit 221 includes a pulse generation unit (PG) 2
23, two AND gates 225 and 227, a set-reset type flip-flop (RS-FF) 229, a selector 231 and an inverter 233, and the non-inverted signal thereof according to the phase state of the inputted decoder control signal. Alternatively, it is for generating and outputting an inverted signal.

Here, the "decoder control signal" is a signal for setting the timing of the decoding process in the decoder, and is obtained by, for example, dividing the clock in the device. Therefore, the decoder control signal and the decoded data control signal transmitted from the line side are asynchronous with each other at the same speed. Also, this decoder control signal is, for example, inside the decoder 531 in the audio codec shown in FIG.
Alternatively, the control signal is generated by another control unit (not shown) or the like, and the supply of the control controller control signal is continued even when the supply of the decoded data control signal or the clock is interrupted due to the line disconnection.

The pulse generator 223 outputs a signal including the rising edge of the decoder control signal in the prohibited area from the first output terminal, and outputs a signal including the falling edge in the prohibited area from the second output terminal.

The AND gate 225 has a pulse generator 2 at one input terminal.
The signal output from the first output terminal 23 is input to the other input terminal, and the control pulse output from the differentiating circuit 211 is input to the other input terminal. The logical product of these signals is input to the set terminal S of the RS-FF229. The AND gate 227 receives a signal output from the second output terminal of the pulse generation unit 223 at one input terminal and a control pulse output from the differentiating circuit 211 at the other input terminal. To RS−
Input to the reset terminal R of FF229.

The selector 231 selects and outputs one of the two inputs according to the logic of the signal output from the output terminal Q of the RS-FF229. When the logic of this signal is "1", a signal obtained by inverting the decoder control signal by the inverter 233 is selected, and when the logic is "0", the decoder control signal itself is selected.

Further, the access cycle detection circuit 241 is composed of three flip-flops 243, 245, 249 and an exclusive OR gate 247, and detects that the cycle of the control pulse output from the differentiation circuit 211 is normal. To output a line disconnection detection signal to the

The flip-flop 243 has a differentiator 211 connected to the clock terminal.
, The output of its own output terminal is input to the input terminal D, and a signal obtained by dividing the control pulse by two is output from the output terminal Q. Flip-flops24
5 is a selector connected to the clock terminal in the control signal generation circuit 221.
The output signal of the selector 231 is input to the input terminal D of the output signal of the selector 231.
The frequency-divided signal is output from the output terminal Q. The exclusive OR gate 247 calculates and outputs an exclusive OR of these two frequency-divided outputs.

In the flip-flop 249, the output of the exclusive OR gate 247 is provided at the input terminal D, and the control signal generation circuit 2 is provided at the clock terminal.
The output signal of the selector 231 in the circuit 21 is input, and the inverted output from the output terminal is output as a line disconnection detection signal. Also, this inverted output is supplied to the flip-flop 243,
The flip-flops 243 and 245 are reset when the logic of the inverted output becomes "0".

 Next, the operation of the above-described embodiment of the present invention will be invented.

FIG. 3 shows operation timings of the differentiating circuit 211 and the control signal generating circuit 221. FIG. 4 shows the operation timing of the access cycle detection circuit 241. It is assumed that the decoded data control signal is output once every eight bits of the decoded data (serial data) synchronized with the clock.

 Hereinafter, FIG. 2 to FIG. 4 will be referred to.

The differentiating circuit 211 outputs a differentiated signal for a half cycle of the clock when the decoded data control signal is input,
This differential signal is output as a control pulse (negative logic) (FIGS. 3 (a), (b), (c)).

The control signal generation circuit 221 generates an inverted signal and a non-inverted signal of the input decoder control signal, and selects and outputs a signal whose rising timing does not match the output timing of the decoded data control signal. .

Specifically, a pulse having a predetermined width is input from the first output terminal of the pulse generator 223 to the AND gate 225 at the time of the rise of the normal rotation signal, and when a control pulse is output synchronously at this time, RS -FF229 is set, and a signal of logic "1" is input to the selector 231 (FIG. 3 (d),
(E), (g), (h)). At this time, the selector 231 selects an inverted signal of the decoder control signal via the inverter 233 (FIGS. 3 (i) and 3 (k)). Conversely, a pulse having a predetermined width is input from the second output terminal of the pulse generator 223 to the AND gate 227 at the time of the rise of the above-mentioned inverted signal.
-FF229 is reset and a signal of logic "0" is input to the selector 231 (FIGS. 3 (d), (f), (g),
(H)). At this time, the selector 231 selects the decoder control signal itself (forward signal) (FIG. 3 (j),
(K)).

The control pulse output from the differentiating circuit 211 is divided into two by the flip-flop 243 in the access period detecting circuit 241 and then input to one input terminal of the exclusive OR gate 247 (FIG. 4 (a) ), (B)). Further, the signal output from the selector 231 in the control signal generation circuit 221 is frequency-divided by 2 in the flip-flop 245 in the access cycle detection circuit 241 and then input to the other input terminal of the exclusive OR gate 247. (FIGS. 4 (c) and (d)).

These two frequency-divided outputs repeat the logic inversion at the same cycle. The logic of the exclusive OR gate 247 changes from “1” to “0” at the rising edge of the control pulse, and the output of the selector 231 is output. Logic is “0” at the rising edge of the signal
The exclusive OR output that changes from "1" to "1" is obtained (fourth
Figure (e).

The flip-flop 249 outputs the exclusive OR output (selector 231) in synchronization with the rise of the output signal of the selector 231.
("0") before the output signal rises, and outputs an inverted output "1" from the output terminal (FIG. 4 (f)). On the other hand, when a state occurs in which either the decoded data control signal or the clock is not input due to a line disconnection, the differentiating circuit
Since the output of the control pulse output from 211 stops, the frequency division operation by flip-flop 243 also stops, and selector 2
An exclusive OR output in which the logic is alternately inverted only at the rising edge of the output signal at 31 is obtained. At this time, the flip-flop 249 takes in the exclusive OR output “1” before the logic changes to “0”, and outputs a line disconnection detection signal of logic “0” from the output terminal (FIG. 4 (f)). ).

As described above, the differentiating circuit 211 differentiates the decoded data control signal with the clock, and inputs the control pulse, which is the differential output, to the access cycle detecting circuit 241.
Numeral 21 inputs the decoder control signal to the access cycle detection circuit 241 as it is or after inverting it. The access cycle detection circuit 241 separately divides each of the two inputs into two, calculates the exclusive OR, and takes in the flip-flop 249 to confirm that the cycle of the control pulse output from the differentiation circuit 211 is normal. Has been detected. If this cycle is not normal, a line disconnection detection signal is output.

Therefore, even when a state where only the clock is not input occurs, the cycle of the control pulse output from the differentiating circuit 211 is not normal, so that it is possible to detect a circuit break due to a clock break. Further, when the transmission rate changes, the timing of the decoder control signal changes along with the timing of the decoded data control signal, so that it is possible to cope with a plurality of transmission rates without particularly changing the constituent circuits.

In the above-described embodiment of the present invention, the line disconnection detection circuit used for the audio codec is considered. However, the line disconnection detection circuit may be used for an apparatus that performs only the decoding process.

〔The invention's effect〕

As described above, according to the present invention, the period of the signal obtained by differentiating the first control signal with the clock is monitored based on the second control signal used for the decoding process. In this case, line disconnection can be detected. Further, since the cycle of the second control signal used for the decoding process corresponds to the transmission rate, it is possible to correspond to a plurality of transmission rates without particularly changing the configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the principle of a line disconnection detection circuit according to the present invention, FIG. 2 is a block diagram of a line disconnection detection circuit according to an embodiment of the present invention, and FIG. FIG. 4 is an operation timing diagram of an access cycle detection circuit of one embodiment, FIG. 5 is a configuration diagram of a voice codec, FIG. 6 is a configuration diagram of a conventional line disconnection detection circuit, and FIG. FIG. 11 is an operation timing chart of a conventional example. In the figure, 111 is differentiating means, 121 is signal generating means, 131 is cycle monitoring means, 211 is differentiating circuits, 213, 243, 245, 249 are flip-flops (FF), 215 is a NAND gate, 221 is a control signal generating circuit, and 223 is a pulse generating unit ( PG), 225 and 227 are AND gates, 229 is an RS flip-flop (RS-FF), 231 is a selector, 233 is an inverter, 241 is an access period detection circuit, and 247 is an exclusive OR gate.

Claims (1)

(57) [Claims] 1. A differentiating means for differentiating a first control signal for synchronizing data input via a line based on a clock extracted from the line, and a decoding unit for decoding the data. Receiving a second control signal that is used and has the same cycle as the first control signal and is asynchronous with each other, and is continuously output even when the line is disconnected;
A signal generating means for generating a third control signal used for monitoring the cycle of the differential output; and monitoring the cycle of the differential output of the differentiating means based on the third control signal. A line disconnection detection circuit, comprising: a period monitoring means for detecting a line disconnection.