JPS5943018B2 - Modem timing clock pulse generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a modem (hereinafter referred to as a modem) that modulates or demodulates data to be transmitted when transmitting data via a transmission medium such as a public telephone line, and in particular a timing clock pulse of a low-speed modem. This relates to a creation device.

Conventionally, when data is transmitted via a transmission medium such as a public telephone line using a facsimile device that can send and receive, for example, a device that creates a modulation timing clock pulse used for transmission and a device that generates a timing clock pulse for reception are used. Separate devices are provided for creating demodulation timing clock pulses to be used.

In addition, PLL (Phase
-LockedLoop) timing clock pulse generators are often used in low-speed modems, but they have the disadvantage that the circuit configuration becomes complicated. The present invention has been made in view of the above points, and is a modem timing clock pulse generating device that can generate timing clock pulses for modulation and demodulation with one timing clock pulse generating device, and has a simple circuit configuration. It provides:

Hereinafter, one embodiment of the present invention will be described based on the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention in a facsimile receiving apparatus, and FIG. 2 is a signal waveform diagram in FIG. 1. A signal transmitted from the transmitting side via a transmission medium is input to a differentiating circuit 2 via an input terminal 1. Further, a clock signal A having a sufficiently high frequency and highly stable relative to the signal port is inputted to the differentiating circuit 2 from an oscillation circuit 3 such as a crystal oscillation circuit. By the way, the pulse width of this signal port is such that the length per 1 bit corresponds to "3333" clock signal A as shown in FIG. When the differentiating circuit 2 receives the clock signal A from the oscillation circuit 3, it outputs a signal C synchronized with the rising and falling points of the signal port. The output signal C from the differentiating circuit 3 corresponds to one clock of the clock signal A output from the oscillation circuit 3, and is input to one input terminal of a negative OR circuit (hereinafter referred to as NOR) 4. The other input terminal of the NOR 4 is input with a carry signal 2 output from a counter 5, which will be described later.
The output of NOR4 is input to the load terminal of counter 5. A clock signal A from the oscillation circuit 3 is input to the clock terminal of the counter 5. Furthermore, preset data predetermined by a group of switches (not shown) or the like is input to the data terminal via the control circuit 7. The output signal C of the differentiating circuit 2 is input to the control circuit 7, and when the signal C is input, the value of the data output to the counter 5 is changed only during the input period of the signal C. When a signal is input to the load terminal, the counter 5 inputs data from the control circuit 7 to its data terminal and starts counting the clock signal A input to its clock terminal. When the counted value reaches the data value set at the data terminal, a carry signal 2 is output. The carrier signal 2 is input to one input terminal of the NOR 4, and is used as a modem timing clock pulse outputted through the output terminal 6. Here, a case where the frequency of the clock signal A of the oscillation circuit 3 is 1 MHz and a timing clock pulse of 300 Hz is desired to be obtained at the output terminal 6 will be explained.

In order to satisfy the above assumption, first, in the receiving state, if there is no output signal of the differentiating circuit 2 (the signal port is "0")
or if there are consecutive "1"), the counter 5
Set the data value of the data terminal to "3333". This data value is the preset data value. Also, the signal port changes from "0" to "1" or from [l] to "0".
, the control circuit 7 uses the output signal C of the differentiating circuit 2 to change the value of the data output to the counter 5 to "1".
666]. That is, the control circuit 7
When the output signal C is input, the output is "1666"
At other times, "3333" is output to the counter 5. Therefore, the frequency of the carry signal 2 (timing clock pulse) output from the output terminal 6 is 30.
The error is 0.010t).

The carry signal 2 obtained in this way is controlled so as to be sampled almost at the center of the 1-bit width of the input signal port (in the case of this embodiment, [3333] clock signal A). ing. In the carry signal 2 in Fig. 2, the shaded signal is connected to the data terminal of the counter 5.
3333] is the carry signal 2 that is output when it is set. The other signals are the carry signal 2 which is controlled by the control circuit 7 by the output signal C of the differentiating circuit 2 and is output when 1666 is set to the data terminal of the counter 5. Next, in the transmitting state, since no signal is input from the input terminal 1, the control circuit 7 does not change the value of the preset data, and the preset data value "3333" is always set at the data terminal of the counter 5. ing.

The counter 5 counts the clock signal A from the oscillation circuit 3, and outputs the carry signal 2 when the count value reaches [3333]. The carrier signal 2 is input to one input terminal of the NOR 4 and output from the output terminal 6.
NOR4 is the counter 5 when the signal 2 is input.
When the signal is input to the load terminal, the counter 5 starts counting the clock signals again, and when the count reaches [3333], it outputs the carry signal 2. By repeating the above operations, the same timing clock pulse as the signal shown in FIG. 2 can be generated. As described above, according to the present invention, 1
Timing clock pulses for modulation and demodulation can be created using a single timing clock pulse creation device, and the circuit configuration thereof can be significantly simpler than that of PI2L or the like. In addition, since the timing clock pulse created according to the present invention is designed to rise at the center of the transmitted unit signal (for example, a 1-bit pulse of an image signal), it is not affected by noise such as phase jitter caused by the transmission medium. becomes difficult to receive.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the timing clock pulse generation device of the present invention, and FIG. 2 is a signal waveform diagram in FIG. 1. 1...Input terminal, 2...Differential circuit, 3
...Oscillation circuit, 4 ...NOR circuit, 5 ...Counter, 6 ...Output terminal,
7... Control circuit.

Claims (1)

[Claims] 1. An oscillation circuit that outputs a high frequency and highly stable clock signal, and a width per bit of n of the clock signal.
a differentiating circuit that differentiates a signal transmitted from the transmitting side, a counter that counts the clock signal, and a control circuit that changes the value of data preset in the counter based on the output of the differentiating circuit; A gate circuit is provided that gives an instruction to start the operation of the counter based on the preset data based on the output of the differentiating circuit and the output of the counter, and the control circuit is configured to perform the presetting when the output of the differentiating circuit is received. set the data value to n/2 of the clock signals, and otherwise set the data value to n/2 clock signals.
A modem timing clock pulse generation device characterized in that the value is controlled to correspond to each pulse.