JP3739797B2 - 縮小命令セット・コンピューター・マイクロプロセッサーの構造 - Google Patents
縮小命令セット・コンピューター・マイクロプロセッサーの構造 Download PDFInfo
- Publication number
- JP3739797B2 JP3739797B2 JP51584897A JP51584897A JP3739797B2 JP 3739797 B2 JP3739797 B2 JP 3739797B2 JP 51584897 A JP51584897 A JP 51584897A JP 51584897 A JP51584897 A JP 51584897A JP 3739797 B2 JP3739797 B2 JP 3739797B2
- Authority
- JP
- Japan
- Prior art keywords
- memory
- bit
- address
- stack
- bus
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0875—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with dedicated cache, e.g. instruction or stack
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
- G06F9/3001—Arithmetic instructions
- G06F9/30014—Arithmetic instructions with variable precision
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30003—Arrangements for executing specific machine instructions
- G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30098—Register arrangements
- G06F9/3012—Organisation of register space, e.g. banked or distributed register file
- G06F9/30134—Register stacks; shift registers
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
- G06F9/3016—Decoding the operand specifier, e.g. specifier format
- G06F9/30167—Decoding the operand specifier, e.g. specifier format of immediate specifier, e.g. constants
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
- G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
- G06F9/323—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for indirect branch instructions
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3824—Operand accessing
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3861—Recovery, e.g. branch miss-prediction, exception handling
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a secondary processor, e.g. coprocessor
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a secondary processor, e.g. coprocessor
- G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a secondary processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/363—Graphics controllers
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
- G09G5/393—Arrangements for updating the contents of the bit-mapped memory
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2360/00—Aspects of the architecture of display systems
- G09G2360/12—Frame memory handling
- G09G2360/121—Frame memory handling using a cache memory
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2360/00—Aspects of the architecture of display systems
- G09G2360/12—Frame memory handling
- G09G2360/126—The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Software Systems (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Mathematical Optimization (AREA)
- Mathematical Analysis (AREA)
- Pure & Applied Mathematics (AREA)
- Computer Graphics (AREA)
- Computational Mathematics (AREA)
- Executing Machine-Instructions (AREA)
- Microcomputers (AREA)
- Advance Control (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Memory System (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US540895P | 1995-10-06 | 1995-10-06 | |
| US60/005,408 | 1995-10-06 | ||
| PCT/US1996/016013 WO1997015001A2 (en) | 1995-10-06 | 1996-10-04 | Risc microprocessor architecture |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005240441A Division JP3955305B2 (ja) | 1995-10-06 | 2005-08-22 | 縮小命令セット・コンピュータ・マイクロプロセッサーの構造 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11513825A JPH11513825A (ja) | 1999-11-24 |
| JP3739797B2 true JP3739797B2 (ja) | 2006-01-25 |
Family
ID=21715705
Family Applications (5)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP51584897A Expired - Lifetime JP3739797B2 (ja) | 1995-10-06 | 1996-10-04 | 縮小命令セット・コンピューター・マイクロプロセッサーの構造 |
| JP2005240441A Expired - Fee Related JP3955305B2 (ja) | 1995-10-06 | 2005-08-22 | 縮小命令セット・コンピュータ・マイクロプロセッサーの構造 |
| JP2006276681A Expired - Lifetime JP4859616B2 (ja) | 1995-10-06 | 2006-10-10 | 縮小命令セット・コンピュータ・マイクロプロセッサーの構造 |
| JP2008290229A Pending JP2009080827A (ja) | 1995-10-06 | 2008-11-12 | マイクロプロセッサシステム |
| JP2009141967A Pending JP2009205698A (ja) | 1995-10-06 | 2009-06-15 | 縮小命令セット・コンピュータ・マイクロプロセッサーの構造 |
Family Applications After (4)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005240441A Expired - Fee Related JP3955305B2 (ja) | 1995-10-06 | 2005-08-22 | 縮小命令セット・コンピュータ・マイクロプロセッサーの構造 |
| JP2006276681A Expired - Lifetime JP4859616B2 (ja) | 1995-10-06 | 2006-10-10 | 縮小命令セット・コンピュータ・マイクロプロセッサーの構造 |
| JP2008290229A Pending JP2009080827A (ja) | 1995-10-06 | 2008-11-12 | マイクロプロセッサシステム |
| JP2009141967A Pending JP2009205698A (ja) | 1995-10-06 | 2009-06-15 | 縮小命令セット・コンピュータ・マイクロプロセッサーの構造 |
Country Status (6)
| Country | Link |
|---|---|
| US (6) | US20070271441A1 (https=) |
| EP (1) | EP0870226B1 (https=) |
| JP (5) | JP3739797B2 (https=) |
| AT (1) | ATE241170T1 (https=) |
| DE (1) | DE69628326D1 (https=) |
| WO (1) | WO1997015001A2 (https=) |
Families Citing this family (52)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7376820B2 (en) * | 2000-03-16 | 2008-05-20 | Fujitsu Limited | Information processing unit, and exception processing method for specific application-purpose operation instruction |
| WO2002010994A1 (en) * | 2000-07-28 | 2002-02-07 | Delvalley Limited | A data processor |
| JP3857614B2 (ja) | 2002-06-03 | 2006-12-13 | 松下電器産業株式会社 | プロセッサ |
| US8612992B2 (en) * | 2003-04-09 | 2013-12-17 | Jaluna Sa | Operating systems |
| US8136096B1 (en) * | 2004-07-23 | 2012-03-13 | Green Hills Software, Inc. | Backward post-execution software debugger |
| FR2896600B1 (fr) * | 2006-01-24 | 2008-03-28 | Atmel Nantes Sa Sa | Dispositif de traitement en notation polonaise inversee pour la manipulation de tableau, et circuit integre electronique comprenant un tel dispositif de traitement |
| FR2896601B1 (fr) * | 2006-01-24 | 2008-08-15 | Atmel Nantes Sa | Dispositif de traitement en notation polonaise inversee, et circuit integre electronique comprenant un tel dispositif de traitement. |
| US7617383B2 (en) | 2006-02-16 | 2009-11-10 | Vns Portfolio Llc | Circular register arrays of a computer |
| US7913069B2 (en) | 2006-02-16 | 2011-03-22 | Vns Portfolio Llc | Processor and method for executing a program loop within an instruction word |
| KR101334172B1 (ko) * | 2007-01-05 | 2013-11-28 | 삼성전자주식회사 | 임베디드 시스템의 스택 오버플로우 방지 방법 및 장치 |
| US7555637B2 (en) | 2007-04-27 | 2009-06-30 | Vns Portfolio Llc | Multi-port read/write operations based on register bits set for indicating select ports and transfer directions |
| US8151349B1 (en) | 2008-07-21 | 2012-04-03 | Google Inc. | Masking mechanism that facilitates safely executing untrusted native code |
| US7957216B2 (en) * | 2008-09-30 | 2011-06-07 | Intel Corporation | Common memory device for variable device width and scalable pre-fetch and page size |
| WO2010078277A1 (en) * | 2008-12-29 | 2010-07-08 | Celio Technology Corporation | Graphics processor |
| US8209523B2 (en) * | 2009-01-22 | 2012-06-26 | Intel Mobile Communications GmbH | Data moving processor |
| GB2471138B (en) * | 2009-06-19 | 2014-08-13 | Advanced Risc Mach Ltd | Handling integer and floating point registers during a context switch |
| US8572357B2 (en) * | 2009-09-29 | 2013-10-29 | International Business Machines Corporation | Monitoring events and incrementing counters associated therewith absent taking an interrupt |
| US9798898B2 (en) | 2010-05-25 | 2017-10-24 | Via Technologies, Inc. | Microprocessor with secure execution mode and store key instructions |
| US8645714B2 (en) | 2010-05-25 | 2014-02-04 | Via Technologies, Inc. | Branch target address cache for predicting instruction decryption keys in a microprocessor that fetches and decrypts encrypted instructions |
| US9911008B2 (en) | 2010-05-25 | 2018-03-06 | Via Technologies, Inc. | Microprocessor with on-the-fly switching of decryption keys |
| US9967092B2 (en) | 2010-05-25 | 2018-05-08 | Via Technologies, Inc. | Key expansion logic using decryption key primitives |
| US9892283B2 (en) | 2010-05-25 | 2018-02-13 | Via Technologies, Inc. | Decryption of encrypted instructions using keys selected on basis of instruction fetch address |
| US20120059866A1 (en) * | 2010-09-03 | 2012-03-08 | Advanced Micro Devices, Inc. | Method and apparatus for performing floating-point division |
| US10838886B2 (en) | 2011-04-19 | 2020-11-17 | Micron Technology, Inc. | Channel depth adjustment in memory systems |
| US8949514B2 (en) * | 2011-05-16 | 2015-02-03 | Cypress Semiconductor Corporation | Stack processor using a ferroelectric random access memory (F-RAM) for both code and data space |
| US9910823B2 (en) | 2011-05-16 | 2018-03-06 | Cypress Semiconductor Corporation | Stack processor using a ferroelectric random access memory (F-RAM) having an instruction set optimized to minimize memory fetch |
| US9588881B2 (en) | 2011-05-16 | 2017-03-07 | Cypress Semiconductor Corporation | Stack processor using a ferroelectric random access memory (F-RAM) for code space and a portion of the stack memory space having an instruction set optimized to minimize processor stack accesses |
| US8560997B1 (en) * | 2012-07-25 | 2013-10-15 | Taiwan Semiconductor Manufacturing Company Limited | Conditional cell placement |
| WO2014085268A1 (en) * | 2012-11-30 | 2014-06-05 | Intel Corporation | Apparatus, method and system for memory device access with a multi-cycle command |
| US9535697B2 (en) * | 2013-07-01 | 2017-01-03 | Oracle International Corporation | Register window performance via lazy register fills |
| US9734326B2 (en) | 2014-02-04 | 2017-08-15 | Nxp Usa, Inc. | Dynamic interrupt stack protection |
| US9411747B2 (en) * | 2014-02-04 | 2016-08-09 | Freescale Semiconductor, Inc. | Dynamic subroutine stack protection |
| JP6128013B2 (ja) * | 2014-02-27 | 2017-05-17 | 株式会社デンソー | 回転角検出装置、および、これを用いた電動パワーステアリング装置 |
| JP6183251B2 (ja) * | 2014-03-14 | 2017-08-23 | 株式会社デンソー | 電子制御装置 |
| EP3189414A4 (en) | 2014-08-22 | 2018-04-18 | Priv8Pay, Inc. | Verification system for secure transmission in a distributed processing network |
| US9389796B1 (en) | 2015-02-23 | 2016-07-12 | International Business Machines Corporation | Efficient register preservation on processors |
| US10592252B2 (en) | 2015-12-31 | 2020-03-17 | Microsoft Technology Licensing, Llc | Efficient instruction processing for sparse data |
| US10459727B2 (en) | 2015-12-31 | 2019-10-29 | Microsoft Technology Licensing, Llc | Loop code processor optimizations |
| US11042878B2 (en) | 2016-01-19 | 2021-06-22 | Priv8Pay, Inc. | Network node authentication |
| US10649786B2 (en) * | 2016-12-01 | 2020-05-12 | Cisco Technology, Inc. | Reduced stack usage in a multithreaded processor |
| US10761999B1 (en) * | 2019-05-30 | 2020-09-01 | Western Digital Technologies, Inc. | Storage device with predictor engine of host turnaround time |
| CN111091544B (zh) * | 2019-12-12 | 2020-10-16 | 哈尔滨市科佳通用机电股份有限公司 | 铁路货车转向架侧面一体架构断裂故障检测方法 |
| US11099848B1 (en) * | 2020-01-30 | 2021-08-24 | Arm Limited | Overlapped-immediate/register-field-specifying instruction |
| CN116507999B (zh) * | 2020-09-29 | 2024-11-29 | 华为技术有限公司 | 一种处理器、处理方法及相关设备 |
| TWI764311B (zh) * | 2020-10-08 | 2022-05-11 | 大陸商星宸科技股份有限公司 | 記憶體存取方法及智慧處理裝置 |
| CN112416637A (zh) * | 2020-11-03 | 2021-02-26 | 中国航空工业集团公司西安航空计算技术研究所 | 一种基于栈技术的故障诊断方法 |
| US11782871B2 (en) | 2021-04-27 | 2023-10-10 | Microchip Technology Inc. | Method and apparatus for desynchronizing execution in a vector processor |
| DE112021006877T5 (de) * | 2021-04-27 | 2023-11-30 | Microchip Technology Inc. | System mit mehreren stapeln in einem prozessor ohne effektiven adressgenerator |
| US12175116B2 (en) | 2021-04-27 | 2024-12-24 | Microchip Technology Inc. | Method and apparatus for gather/scatter operations in a vector processor |
| US12298875B2 (en) * | 2022-06-10 | 2025-05-13 | Microsoft Technology Licensing, Llc | Employing sampled register values to infer memory accesses by an application |
| CN116627865B (zh) * | 2023-04-26 | 2024-02-06 | 安庆师范大学 | 具有多个存储装置的计算机的访问方法及装置 |
| WO2026079525A1 (ko) * | 2024-10-08 | 2026-04-16 | 주식회사 코코링크 | 오퍼랜드리스 인스트럭션 체계 기반 프로세서 및 이를 포함하는 컴퓨터 |
Family Cites Families (83)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2253425A5 (https=) * | 1973-11-30 | 1975-06-27 | Honeywell Bull Soc Ind | |
| US4104976A (en) * | 1977-03-21 | 1978-08-08 | The Singer Company | Programmable sewing machine |
| US4100865A (en) * | 1977-03-21 | 1978-07-18 | The Singer Company | Programmable sewing machine operable in a plurality of modes |
| US4092937A (en) * | 1977-03-21 | 1978-06-06 | The Singer Company | Automatic stitching by programmable sewing machine |
| US4108090A (en) * | 1977-03-21 | 1978-08-22 | The Singer Company | Programmable variable speed for sewing machine |
| US4255785A (en) * | 1978-09-25 | 1981-03-10 | Motorola, Inc. | Microprocessor having instruction fetch and execution overlap |
| US4222103A (en) * | 1978-09-25 | 1980-09-09 | Motorola, Inc. | Real time capture registers for data processor |
| US4326247A (en) * | 1978-09-25 | 1982-04-20 | Motorola, Inc. | Architecture for data processor |
| US4287560A (en) * | 1979-06-27 | 1981-09-01 | Burroughs Corporation | Dual mode microprocessor system |
| US4374418A (en) * | 1979-06-27 | 1983-02-15 | Burroughs Corporation | Linear microsequencer unit cooperating with microprocessor system having dual modes |
| US4346437A (en) * | 1979-08-31 | 1982-08-24 | Bell Telephone Laboratories, Incorporated | Microcomputer using a double opcode instruction |
| US4348720A (en) * | 1979-08-31 | 1982-09-07 | Bell Telephone Laboratories, Incorporated | Microcomputer arranged for direct memory access |
| US4306287A (en) * | 1979-08-31 | 1981-12-15 | Bell Telephone Laboratories, Incorporated | Special address generation arrangement |
| US4338675A (en) * | 1980-02-13 | 1982-07-06 | Intel Corporation | Numeric data processor |
| JPS5792475A (en) * | 1980-11-25 | 1982-06-09 | Nec Corp | Multiple stack device |
| JPS57182852A (en) * | 1981-05-07 | 1982-11-10 | Nec Corp | Stack device |
| US4887235A (en) * | 1982-12-17 | 1989-12-12 | Symbolics, Inc. | Symbolic language data processing system |
| US4922414A (en) * | 1982-12-17 | 1990-05-01 | Symbolics Inc. | Symbolic language data processing system |
| JPH0731603B2 (ja) * | 1984-11-21 | 1995-04-10 | ノビツクス | Forth特定言語マイクロプロセサ |
| US4794521A (en) * | 1985-07-22 | 1988-12-27 | Alliant Computer Systems Corporation | Digital computer with cache capable of concurrently handling multiple accesses from parallel processors |
| US4783736A (en) * | 1985-07-22 | 1988-11-08 | Alliant Computer Systems Corporation | Digital computer with multisection cache |
| GB2188759B (en) * | 1986-04-05 | 1990-09-05 | Burr Brown Ltd | Data processing with op code early comparison |
| JPS62256058A (ja) * | 1986-04-30 | 1987-11-07 | Toshiba Corp | アドレス変換バツフア制御方式 |
| US4811208A (en) * | 1986-05-16 | 1989-03-07 | Intel Corporation | Stack frame cache on a microprocessor chip |
| JPS62277006A (ja) * | 1986-05-24 | 1987-12-01 | Hitachi Ltd | 電気車用制御装置 |
| US4803621A (en) * | 1986-07-24 | 1989-02-07 | Sun Microsystems, Inc. | Memory access system |
| JPS6356449U (https=) * | 1986-09-26 | 1988-04-15 | ||
| US5091846A (en) * | 1986-10-03 | 1992-02-25 | Intergraph Corporation | Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency |
| JPH01134544A (ja) * | 1987-11-20 | 1989-05-26 | Hitachi Ltd | メモリアクセス方式 |
| EP0340901A3 (en) * | 1988-03-23 | 1992-12-30 | Du Pont Pixel Systems Limited | Access system for dual port memory |
| US5428754A (en) * | 1988-03-23 | 1995-06-27 | 3Dlabs Ltd | Computer system with clock shared between processors executing separate instruction streams |
| US5056015A (en) * | 1988-03-23 | 1991-10-08 | Du Pont Pixel Systems Limited | Architectures for serial or parallel loading of writable control store |
| GB2217058A (en) * | 1988-03-23 | 1989-10-18 | Benchmark Technologies | Processing integral transform operations |
| JPH01255035A (ja) * | 1988-04-05 | 1989-10-11 | Matsushita Electric Ind Co Ltd | プロセサ |
| US5187799A (en) * | 1988-05-17 | 1993-02-16 | Calif. Institute Of Technology | Arithmetic-stack processor which precalculates external stack address before needed by CPU for building high level language executing computers |
| US5261057A (en) * | 1988-06-30 | 1993-11-09 | Wang Laboratories, Inc. | I/O bus to system interface |
| US5109514A (en) * | 1988-07-28 | 1992-04-28 | Sun Microsystems, Inc. | Method and apparatus for executing concurrent CO processor operations and precisely handling related exceptions |
| KR0136594B1 (ko) * | 1988-09-30 | 1998-10-01 | 미다 가쓰시게 | 단일칩 마이크로 컴퓨터 |
| US4951194A (en) * | 1989-01-23 | 1990-08-21 | Tektronix, Inc. | Method for reducing memory allocations and data copying operations during program calling sequences |
| US5214767A (en) * | 1989-02-07 | 1993-05-25 | Compaq Computer Corp. | Full address and odd boundary direct memory access controller which determines address size by counting the input address bytes |
| US5768575A (en) * | 1989-02-24 | 1998-06-16 | Advanced Micro Devices, Inc. | Semi-Autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for sepculative and out-of-order execution of complex instructions |
| US5781753A (en) * | 1989-02-24 | 1998-07-14 | Advanced Micro Devices, Inc. | Semi-autonomous RISC pipelines for overlapped execution of RISC-like instructions within the multiple superscalar execution units of a processor having distributed pipeline control for speculative and out-of-order execution of complex instructions |
| JPH02239329A (ja) * | 1989-03-14 | 1990-09-21 | Toshiba Corp | スタック管理システム |
| US5107457A (en) * | 1989-04-03 | 1992-04-21 | The Johns Hopkins University | Stack data cache having a stack management hardware with internal and external stack pointers and buffers for handling underflow and overflow stack |
| US5142635A (en) * | 1989-04-07 | 1992-08-25 | Intel Corporation | Method and circuitry for performing multiple stack operations in succession in a pipelined digital computer |
| JPH02284253A (ja) * | 1989-04-26 | 1990-11-21 | Hitachi Ltd | データ転送装置 |
| JPH02304624A (ja) * | 1989-05-19 | 1990-12-18 | Hitachi Ltd | 情報処理装置 |
| US5440749A (en) * | 1989-08-03 | 1995-08-08 | Nanotronics Corporation | High performance, low cost microprocessor architecture |
| JPH03203087A (ja) * | 1989-12-28 | 1991-09-04 | Canon Inc | メモリアクセス制御装置 |
| US5546551A (en) * | 1990-02-14 | 1996-08-13 | Intel Corporation | Method and circuitry for saving and restoring status information in a pipelined computer |
| US5280615A (en) * | 1990-03-23 | 1994-01-18 | Unisys Corporation | Out of order job processing method and apparatus |
| CA2045705A1 (en) * | 1990-06-29 | 1991-12-30 | Richard Lee Sites | In-register data manipulation in reduced instruction set processor |
| EP0488566A3 (en) * | 1990-11-29 | 1992-10-21 | Sun Microsystems, Inc. | Method and apparatus for fast page mode selection |
| JPH04308953A (ja) * | 1991-04-05 | 1992-10-30 | Kyocera Corp | 仮想アドレス計算機装置 |
| US5410654A (en) * | 1991-07-22 | 1995-04-25 | International Business Machines Corporation | Interface with address decoder for selectively generating first and second address and control signals respectively in response to received address and control signals |
| JPH0553801A (ja) * | 1991-08-28 | 1993-03-05 | Seiko Epson Corp | スタツク消費検索方式 |
| DE69228980T2 (de) * | 1991-12-06 | 1999-12-02 | National Semiconductor Corp., Santa Clara | Integriertes Datenverarbeitungssystem mit CPU-Kern und unabhängigem parallelen, digitalen Signalprozessormodul |
| JPH05181778A (ja) * | 1991-12-27 | 1993-07-23 | Nec Corp | 入出力処理装置 |
| GB2266606B (en) * | 1992-04-27 | 1996-02-14 | Intel Corp | A microprocessor with an external command mode |
| US5522051A (en) * | 1992-07-29 | 1996-05-28 | Intel Corporation | Method and apparatus for stack manipulation in a pipelined processor |
| US5367650A (en) * | 1992-07-31 | 1994-11-22 | Intel Corporation | Method and apparauts for parallel exchange operation in a pipelined processor |
| US5590359A (en) * | 1992-08-05 | 1996-12-31 | Intel Corporation | Method and apparatus for generating a status word in a pipelined processor |
| US5600584A (en) * | 1992-09-15 | 1997-02-04 | Schlafly; Roger | Interactive formula compiler and range estimator |
| JPH06215559A (ja) * | 1993-01-14 | 1994-08-05 | Fuji Xerox Co Ltd | ページメモリアクセス方式 |
| US5826069A (en) * | 1993-09-27 | 1998-10-20 | Intel Corporation | Having write merge and data override capability for a superscalar processing device |
| US5369617A (en) * | 1993-12-21 | 1994-11-29 | Intel Corporation | High speed memory interface for video teleconferencing applications |
| US5537559A (en) * | 1994-02-08 | 1996-07-16 | Meridian Semiconductor, Inc. | Exception handling circuit and method |
| US5696955A (en) * | 1994-06-01 | 1997-12-09 | Advanced Micro Devices, Inc. | Floating point stack and exchange instruction |
| US5636362A (en) * | 1994-09-28 | 1997-06-03 | Intel Corporation | Programmable high watermark in stack frame cache using second region as a storage if first region is full and an event having a predetermined minimum priority |
| US6216200B1 (en) * | 1994-10-14 | 2001-04-10 | Mips Technologies, Inc. | Address queue |
| US5717952A (en) * | 1994-11-16 | 1998-02-10 | Apple Computer, Inc. | DMA controller with mechanism for conditional action under control of status register, prespecified parameters, and condition field of channel command |
| US6038643A (en) * | 1996-01-24 | 2000-03-14 | Sun Microsystems, Inc. | Stack management unit and method for a processor having a stack |
| US5930820A (en) * | 1996-03-18 | 1999-07-27 | Advanced Micro Devices, Inc. | Data cache and method using a stack memory for storing stack data separate from cache line storage |
| US6085307A (en) * | 1996-11-27 | 2000-07-04 | Vlsi Technology, Inc. | Multiple native instruction set master/slave processor arrangement and method thereof |
| US5953741A (en) * | 1996-11-27 | 1999-09-14 | Vlsi Technology, Inc. | Stack cache for stack-based processor and method thereof |
| US6289418B1 (en) * | 1997-03-31 | 2001-09-11 | Sun Microsystems, Inc. | Address pipelined stack caching method |
| US6167488A (en) * | 1997-03-31 | 2000-12-26 | Sun Microsystems, Inc. | Stack caching circuit with overflow/underflow unit |
| US6009499A (en) * | 1997-03-31 | 1999-12-28 | Sun Microsystems, Inc | Pipelined stack caching circuit |
| US6131144A (en) * | 1997-04-01 | 2000-10-10 | Sun Microsystems, Inc. | Stack caching method with overflow/underflow control using pointers |
| US5923892A (en) * | 1997-10-27 | 1999-07-13 | Levy; Paul S. | Host processor and coprocessor arrangement for processing platform-independent code |
| US7139877B2 (en) * | 2003-01-16 | 2006-11-21 | Ip-First, Llc | Microprocessor and apparatus for performing speculative load operation from a stack memory cache |
| US7139876B2 (en) * | 2003-01-16 | 2006-11-21 | Ip-First, Llc | Microprocessor and apparatus for performing fast speculative pop operation from a stack memory cache |
| US7805573B1 (en) * | 2005-12-20 | 2010-09-28 | Nvidia Corporation | Multi-threaded stack cache |
-
1996
- 1996-10-04 JP JP51584897A patent/JP3739797B2/ja not_active Expired - Lifetime
- 1996-10-04 WO PCT/US1996/016013 patent/WO1997015001A2/en not_active Ceased
- 1996-10-04 EP EP96934069A patent/EP0870226B1/en not_active Expired - Lifetime
- 1996-10-04 AT AT96934069T patent/ATE241170T1/de not_active IP Right Cessation
- 1996-10-04 DE DE69628326T patent/DE69628326D1/de not_active Expired - Lifetime
-
2005
- 2005-08-22 JP JP2005240441A patent/JP3955305B2/ja not_active Expired - Fee Related
-
2006
- 2006-10-10 JP JP2006276681A patent/JP4859616B2/ja not_active Expired - Lifetime
-
2007
- 2007-07-26 US US11/881,283 patent/US20070271441A1/en not_active Abandoned
- 2007-07-26 US US11/881,284 patent/US20070271442A1/en not_active Abandoned
- 2007-10-31 US US11/981,453 patent/US20080072021A1/en not_active Abandoned
- 2007-10-31 US US11/981,278 patent/US20080077911A1/en not_active Abandoned
- 2007-10-31 US US11/981,237 patent/US20080091920A1/en not_active Abandoned
- 2007-10-31 US US11/981,482 patent/US20080071991A1/en not_active Abandoned
-
2008
- 2008-11-12 JP JP2008290229A patent/JP2009080827A/ja active Pending
-
2009
- 2009-06-15 JP JP2009141967A patent/JP2009205698A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| US20080071991A1 (en) | 2008-03-20 |
| US20070271441A1 (en) | 2007-11-22 |
| ATE241170T1 (de) | 2003-06-15 |
| EP0870226A2 (en) | 1998-10-14 |
| EP0870226B1 (en) | 2003-05-21 |
| US20080077911A1 (en) | 2008-03-27 |
| US20080072021A1 (en) | 2008-03-20 |
| JP2009205698A (ja) | 2009-09-10 |
| WO1997015001A2 (en) | 1997-04-24 |
| DE69628326D1 (de) | 2003-06-26 |
| JP2009080827A (ja) | 2009-04-16 |
| US20070271442A1 (en) | 2007-11-22 |
| JP2006024233A (ja) | 2006-01-26 |
| WO1997015001A3 (en) | 1998-04-09 |
| JP3955305B2 (ja) | 2007-08-08 |
| JPH11513825A (ja) | 1999-11-24 |
| JP2007042131A (ja) | 2007-02-15 |
| JP4859616B2 (ja) | 2012-01-25 |
| EP0870226A4 (en) | 2001-08-08 |
| US20080091920A1 (en) | 2008-04-17 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3739797B2 (ja) | 縮小命令セット・コンピューター・マイクロプロセッサーの構造 | |
| KR100403405B1 (ko) | 분산형버스액세스및제어조정에따라다수개의내부신호버스를공유하는다수개의회로기능요소를갖는집적회로 | |
| KR100578437B1 (ko) | 다수의 스레드의 병행 실행을 지원하는 컴퓨터 시스템에서의 인터럽트 처리 메커니즘 | |
| US6311234B1 (en) | Direct memory access controller with split channel transfer capability and FIFO buffering | |
| EP0203304B1 (en) | Data processor controller | |
| US20140282312A1 (en) | Hardware simulation controller, system and method for functional verification | |
| US20120066455A1 (en) | Hybrid prefetch method and apparatus | |
| EP0859320A1 (en) | A configurable expansion bus controller | |
| JPH05502125A (ja) | 後入れ先出しスタックを備えるマイクロプロセッサ、マイクロプロセッサシステム、及び後入れ先出しスタックの動作方法 | |
| US9009420B2 (en) | Structure for performing cacheline polling utilizing a store and reserve instruction | |
| US5813041A (en) | Method for accessing memory by activating a programmable chip select signal | |
| US9983874B2 (en) | Structure for a circuit function that implements a load when reservation lost instruction to perform cacheline polling | |
| US6006288A (en) | Method and apparatus for adaptable burst chip select in a data processing system | |
| CN101313290B (zh) | 对仅m×n位外围设备执行n位写入访问的系统和方法 | |
| EP0380291A2 (en) | Pump bus to avoid indeterminacy in reading variable bit field | |
| EP0772829A1 (en) | A pipelined microprocessor that makes memory requests to a cache memory and an external memory controller during the same clock cycle | |
| EP0811921B1 (en) | Method for accessing memory | |
| US20060248318A1 (en) | Method and apparatus for sharing memory among a plurality of processors | |
| JPH02244252A (ja) | マルチプロセッサシステム | |
| US20090100220A1 (en) | Memory system, control method thereof and computer system | |
| Gupta | Computer Organization and Architecture | |
| JPS6014435B2 (ja) | 記憶装置 | |
| JPWO1996036919A1 (ja) | マイクロコンピュータ | |
| JPH08212069A (ja) | データプロセッサ |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20050222 |
|
| A601 | Written request for extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A601 Effective date: 20050523 |
|
| A602 | Written permission of extension of time |
Free format text: JAPANESE INTERMEDIATE CODE: A602 Effective date: 20050704 |
|
| A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20050822 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20051004 |
|
| A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20051104 |
|
| R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091111 Year of fee payment: 4 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101111 Year of fee payment: 5 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111111 Year of fee payment: 6 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121111 Year of fee payment: 7 |
|
| FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131111 Year of fee payment: 8 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| EXPY | Cancellation because of completion of term |