JP3726498B2 - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor device Download PDFInfo
- Publication number
- JP3726498B2 JP3726498B2 JP17292898A JP17292898A JP3726498B2 JP 3726498 B2 JP3726498 B2 JP 3726498B2 JP 17292898 A JP17292898 A JP 17292898A JP 17292898 A JP17292898 A JP 17292898A JP 3726498 B2 JP3726498 B2 JP 3726498B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- bonding
- adhesive
- wiring board
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/4501—Shape
- H01L2224/45012—Cross-sectional shape
- H01L2224/45015—Cross-sectional shape being circular
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/45124—Aluminium (Al) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4901—Structure
- H01L2224/4903—Connectors having different sizes, e.g. different diameters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/4905—Shape
- H01L2224/49051—Connectors having different shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/78—Apparatus for connecting with wire connectors
- H01L2224/787—Means for aligning
- H01L2224/78703—Mechanical holding means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/852—Applying energy for connecting
- H01L2224/85201—Compression bonding
- H01L2224/85205—Ultrasonic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/85951—Forming additional members, e.g. for reinforcing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01007—Nitrogen [N]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19107—Disposition of discrete passive components off-chip wires
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
- Die Bonding (AREA)
Description
【0001】
【発明の属する技術分野】
本発明は、基板を基板支持部材に接着した状態で、両者をワイヤボンディングして構成された半導体装置の製造方法に関する。
【0002】
【従来の技術】
例えば複数の半導体チップを搭載した配線基板をケース内に収容する場合、まず、配線基板をケースの内底部に接着剤を介して接着する。続いて、この接着した配線基板及びケースを加熱することにより、上記接着剤を硬化させる。そして、配線基板上に設けられたボンディングランドと、ケース上に設けられたボンディングランドとの間をワイヤボンディングすることにより接続するように構成されている。
【0003】
ここで、ボンディングランドは、例えばCuで形成されているため、上記接着剤を加熱硬化するときに、その表面が酸化・汚染されてしまう。ボンディングランドが酸化・汚染されたままで、ワイヤボンディングを行うと、ボンディング強度(接合強度)が不足するという不具合がある。このため、従来構成においては、接着剤を加熱硬化する工程を行った後、ボンディングランド上の酸化膜や汚染物を例えばプラズマクリーニングにより除去する工程を実行してから、ワイヤボンディングを行うようにしていた。また、他の対策として、接着剤を硬化する工程を行う前に、ボンディングランド上にストリップマスクを塗布しておくという方法もあった。この方法の場合、接着剤を硬化する工程を行った後、ストリップマスクを除去する工程を実行してから、ワイヤボンディングを行う。
【0004】
【発明が解決しようとする課題】
しかしながら、上記従来構成の各方法の場合、作業工程数が増えるという欠点があった。また、ボンディングランド上の酸化膜や汚染物をプラズマクリーニングにより除去する方法の場合、酸化膜や汚染物を完全に除去することは困難であった。更に、ボンディングランド上にストリップマスクを塗布しておく方法の場合、硬化時間の長い接着剤や硬化温度の高い接着剤を使用すると、ボンディングランドの酸化・汚染を回避することが困難であった。
【0005】
一方、ボンディングランドの酸化を防止する方法として、N2等低酸素濃度の雰囲気または還元雰囲気において接着剤を硬化させる方法がある。しかし、この方法の場合、接着剤等から発生するアウトガスや硬化炉内の汚染物がボンディングランドに付着してしまうという欠点があった。
【0006】
そこで、本発明の目的は、ワイヤボンディングのボンディング強度を十分強くすることができ、しかも、作業工程数を低減することができる半導体装置の製造方法を提供することにある。
【0007】
【課題を解決するための手段】
請求項1の発明によれば、基板を基板支持部材に接着剤を介して接着した後、接着剤を硬化させる前に、基板と基板支持部材との間をワイヤボンディングし、この後、接着剤を硬化させるように構成したので、ボンディングランドが酸化・汚染されない状態で、ワイヤボンディングを実行することができる。このため、ボンディング強度が十分強くなると共に、クリーニング工程やマスク工程等の作業工程を不要にすることができる。そして、ボンディング工程を実行するときに、前記基板が位置ずれしないように前記基板を押さえ付ける押さえ部材を、前記基板支持部材を載置固定する治具に設けたので、ワイヤボンディングを行なったときに、基板が位置ずれすることを確実に防止できる。
【0008】
請求項2の発明によれば、配線基板をケースに接着して両者の間をワイヤボンディングする構成に適用することができる。また、請求項3の発明によれば、ボンディング工程を実行するときに、基板が位置ずれしないように基板を押さえ付ける押さえ部材を、ワイヤボンダーのヘッド部に設けたので、請求項1の発明とほぼ同じ作用効果を得ることができる。
【0009】
【発明の実施の形態】
以下、本発明の第1の実施例について図1ないし図3を参照しながら説明する。まず、本実施例で使用する配線基板1について、図1(a)及び(b)に従って説明する。この配線基板1は、プリント配線基板やセラミック基板等から構成されており、その上面には、図1(a)に示すように、導体パターン2が予め形成されている。そして、配線基板1の上面には、図1(b)に示すように、各種の半導体チップ3や種々の部品(図示しない)が次に述べるようにして搭載されている。
【0010】
即ち、配線基板1の導体パターン2の上に例えばAgペースト4を塗布する。続いて、各種の半導体チップ3や種々の部品を、上記Agペースト4の上に載置することにより配線基板1の上面に貼り付ける。そして、Agペースト4が硬化したら、半導体チップ3と配線基板1の導体パターン2との間をワイヤボンディングして接続する。この場合、例えばAu線5を用いてワイヤボンディングを行っている。
【0011】
次に、このような構成の配線基板1を、基板支持部材である例えばケース6内に収容して固定する作業工程について、図1(c)、(d)、(e)を参照して説明する。まず、図1(c)に示すように、配線基板1をケース6の内底面に接着剤7を介して接着する接着工程を実行する。本実施例の場合、接着剤7として、例えばシリコーンゴム接着剤(具体的には、東レシリコーン製のCY52−223A/B;付加反応型(2液型)シリコーンゴム)を使用した。また、接着剤7の厚み寸法は例えば約200μmに設定した。
【0012】
続いて、図1(d)に示すように、上記接着剤7を硬化させる前の状態(未硬化状態)で、配線基板1とケース6との間をワイヤボンディングするボンディング工程を実行する。この場合、例えばアルミ線8を用いてワイヤボンディング(例えば超音波によるワイヤボンディング)を行っている。そして、配線基板1の上面の右端部に設けられた導体パターン2であるボンディングランド2aと、ケース6の内底部の右端部の段部6aに設けられた導体パターン9であるボンディングランド9aとを、上記アルミ線8でワイヤボンディングしている。ここで、接着剤7が硬化していない状態で、ワイヤボンディングを行うと、配線基板1が位置ずれを起こすような感じがするが、実際には位置ずれが生じなかった。
【0013】
上記配線基板1の位置ずれが生じなかった理由としては、ワイヤボンディング時に、配線基板1に作用する横向きの力が非常に弱い力であるのに対して、接着剤7が未硬化であっても、配線基板1とケース6とを接着する力がかなり強い力であるためである。この接着する力がかなり強い理由は、配線基板1の下面全体とケース6の内底面とが接着剤7を介して面で接着されているためである。尚、ワイヤボンディング時に配線基板1に作用する横向きの力は、配線基板1側のボンディングランド2aにアルミ線8を接続した後、アルミ線8を引き出すときに生じたり、また、ランド2a、9aにアルミ線8を接続した後、アルミ線8を切断したりするときに生ずる力であり、非常に弱い。そして、本実施例においては、外径寸法が例えば250μmのアルミ線を用いて、超音波ワイヤボンディングを実行したが、配線基板1は全く位置ずれしなかった。
【0014】
さて、上記ワイヤボンディング工程を実行した後は、接着剤7を硬化させる工程を実行する。この場合、周知構成の硬化炉や加熱高温槽等を用いて上記ケース6及び配線基板1を加熱することにより、接着剤7を硬化させるように構成されている。これにより、配線基板1をケース6に取り付ける作業が完了する。
【0015】
このような構成の本実施例によれば、配線基板1をケース6に取り付けるに当たって、配線基板1をケース6に接着剤7を介して接着した後、接着剤7の未硬化状態で、配線基板1とケース6との間をワイヤボンディングした。そしてこの後、接着剤7を加熱硬化させるように構成した。この構成の場合、配線基板1及びケース6の各ボンディングランド2a及び9aが酸化・汚染される前のきれいな状態で、ワイヤボンディングを実行することができる。このため、ワイヤボンディングのボンディング強度(接合強度)を十分強くすることができる。そして、このようにボンディング強度が強くなると、ワイヤボンディングのパワーを低下させても、十分なボンディング強度を容易に得ることができる。また、本実施例では、従来構成において必要としたクリーニング工程やマスク工程等の作業工程が不要になる。このため、作業工程数を低減することができる。
【0016】
ここで、本実施例のアルミ線8のボンディング強度、具体的には、アルミ線8をボンディングした部分の引っ張り強度を調べた結果を、図2に示す。この図2において、右側のデータは、比較例のアルミ線のボンディング強度を調べた結果である。この比較例は、配線基板をケースに接着剤を介して接着した後、硬化炉により接着剤を加熱硬化させ、その後、配線基板とケースとの間をワイヤボンディングした例である。この図2から、本実施例の場合のボンディング強度が十分強くなったことがわかる。
【0017】
尚、ボンディング強度を調べるに当たっては、図3に示すような構造にして、引っ張り強度の試験を行った。即ち、図3に示すように、基板載せ台である治具10の上面にケース6を両面粘着テープ11を介して接着固定した。また、比較例とクリーニング工程を行う従来構成との違いは、従来構成においては、ワイヤボンディングを行う前に、ボンディングランド上の酸化膜や汚染物を除去するクリーニング工程を行った点である。そして、クリーニング工程を行っても酸化膜や汚染物を完全には除去できないため、従来構成の場合のボンディング強度は、比較例よりも多少良くなる程度である。
【0018】
また、上記実施例では、ワイヤボンディングを実行するときに、アルミ線8を用いたが、これに代えて、Au線等を用いても良い。更に、上記実施例では、超音波を用いたワイヤボンディングに適用したが、超音波及び熱を用いたワイヤボンディングに適用しても良いし、また、熱を用いたワイヤボンディングに適用しても良い。
【0019】
更にまた、上記実施例では、配線基板1をケース6に取り付ける構成に適用したが、これに限られるものではなく、半導体チップを配線基板に取り付ける構成に適用しても良い。具体的には、半導体チップを配線基板に接着する接着剤として、例えば前述したシリコーンゴム系の接着剤を使用する場合、接着剤を加熱硬化するときに、ボンディングランドが酸化・汚染される。このため、上記実施例とほぼ同様にして、半導体チップを配線基板に接着した後、接着剤を硬化させる前の状態で半導体チップと配線基板との間をワイヤボンディングし、この後、接着剤を硬化させるように構成することが好ましい。
【0020】
さて、上述したように、配線基板1をケース6に接着した接着剤7が硬化していない状態で、ワイヤボンディングを行うと、配線基板1が位置ずれを起こす可能性がある。例えば、使用するワイヤが太くて、ワイヤボンディング時に配線基板1に対して大きな横向きの力が作用するような場合や、未硬化状態の接着剤の接着力が非常に弱い接着剤を使用しなければならない場合などが考えられる。このような場合には、図4に示す第2の実施例または図5に示す第3の実施例のように構成すれば、配線基板1の位置ずれを防止することができる。以下、これら第2及び第3の実施例について順に説明する。
【0021】
まず、第2の実施例では、図4に示すように、ケース6を載置固定する治具12に、配線基板1を押さえ付ける押さえ部材13を回動支点14の回りに回動可能に設けた。そして、配線基板1を押さえなくても良いときは、押さえ部材13を図4中2点鎖線で示す位置に回動させておく。これに対して、配線基板1をケース6に接着した接着剤7が硬化していない状態で、ワイヤボンディングを行うときは、押さえ部材13を図4中実線で示す位置に回動させる。これにより、該押さえ部材13によって配線基板1を押さえ付けることが可能な構成となっている。この結果、ワイヤボンディングを行なったときに、配線基板1が位置ずれすることを確実に防止できる。
【0022】
尚、上述した以外の第2の実施例の構成は、第1の実施例の構成と同じ構成となっている。従って、第2の実施例においても、第1の実施例と同様な作用効果を得ることができる。
【0023】
次に、第3の実施例では、図5に示すように、ワイヤボンダー15のヘッド部16に、配線基板1を押さえ付ける押さえ部材17を設けた。この構成の場合、ワイヤボンディングを行うときには、図5に示すように、ワイヤボンダー15の押さえ部材17が配線基板1を押さえ付けるように構成されている。これにより、ワイヤボンディングを行なったときに、配線基板1が位置ずれすることを確実に防止できる。尚、上述した以外の第3の実施例の構成は、第1の実施例または第2の実施例の構成と同じ構成となっている。
【図面の簡単な説明】
【図1】本発明の第1の実施例を示すものであり、製造工程を示す図
【図2】ワイヤボンディングの引っ張り強度の試験結果を示す図
【図3】引っ張り強度の試験を行なったときの構成を示す図
【図4】本発明の第2の実施例を示す縦断側面図
【図5】本発明の第3の実施例を示す図4相当図
【符号の説明】
1は配線基板、2は導体パターン、2aはボンディングランド、3は半導体チップ、6はケース(基板支持部材)、7は接着剤、8はアルミ線、9は導体パターン、9aはボンディングランド、13は押さえ部材、15はワイヤボンダー、17は押さえ部材を示す。[0001]
BACKGROUND OF THE INVENTION
The present invention, while bonding the substrate to the substrate support member relates to the production how a semiconductor device constituted both by wire bonding.
[0002]
[Prior art]
For example, when housing a wiring board on which a plurality of semiconductor chips are mounted in a case, first, the wiring board is bonded to the inner bottom portion of the case via an adhesive. Subsequently, the adhesive is cured by heating the bonded wiring board and case. The bonding lands provided on the wiring board and the bonding lands provided on the case are connected by wire bonding.
[0003]
Here, since the bonding land is made of Cu, for example, the surface of the bonding land is oxidized and contaminated when the adhesive is heated and cured. If wire bonding is performed while the bonding land remains oxidized and contaminated, there is a problem that bonding strength (bonding strength) is insufficient. For this reason, in the conventional configuration, after performing the step of heat-curing the adhesive, the step of removing the oxide film and contaminants on the bonding land by, for example, plasma cleaning is performed, and then the wire bonding is performed. It was. As another countermeasure, there is a method in which a strip mask is applied on the bonding land before the step of curing the adhesive. In the case of this method, after performing the step of curing the adhesive, the step of removing the strip mask is performed, and then the wire bonding is performed.
[0004]
[Problems to be solved by the invention]
However, each method of the conventional configuration has a drawback that the number of work steps increases. Further, in the case of the method of removing the oxide film and contaminants on the bonding land by plasma cleaning, it is difficult to completely remove the oxide film and contaminants. Furthermore, in the method of applying a strip mask on the bonding land, it is difficult to avoid oxidation and contamination of the bonding land when an adhesive having a long curing time or an adhesive having a high curing temperature is used.
[0005]
On the other hand, as a method of preventing the bonding land from being oxidized, there is a method of curing the adhesive in an atmosphere of low oxygen concentration such as N 2 or a reducing atmosphere. However, this method has a drawback that outgas generated from an adhesive or the like or contaminants in the curing furnace adhere to the bonding land.
[0006]
An object of the present invention, the bonding strength of the wire bonding can be sufficiently strong, yet, it is to provide a manufacturing how a semiconductor device capable of reducing the number of working processes.
[0007]
[Means for Solving the Problems]
According to the first aspect of the present invention, after the substrate is bonded to the substrate support member via the adhesive, the substrate and the substrate support member are wire-bonded before the adhesive is cured. Therefore, wire bonding can be performed in a state where the bonding land is not oxidized or contaminated. For this reason, the bonding strength becomes sufficiently strong, and work steps such as a cleaning step and a mask step can be eliminated. When the bonding process is performed, since a pressing member for holding the substrate so as not to be displaced is provided in a jig for mounting and fixing the substrate support member, when wire bonding is performed The substrate can be reliably prevented from being displaced.
[0008]
According to invention of
[0009]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. First, the
[0010]
That is, for example, an
[0011]
Next, an operation process in which the
[0012]
Subsequently, as shown in FIG. 1 (d), a bonding step of wire bonding between the
[0013]
The reason why the positional displacement of the
[0014]
Now, after performing the said wire bonding process, the process which hardens the
[0015]
According to the present embodiment having such a configuration, when the
[0016]
Here, FIG. 2 shows the result of examining the bonding strength of the
[0017]
When examining the bonding strength, a tensile strength test was conducted with the structure shown in FIG. That is, as shown in FIG. 3, the case 6 was bonded and fixed to the upper surface of the
[0018]
In the above embodiment, the
[0019]
Furthermore, in the said Example, although applied to the structure which attaches the
[0020]
As described above, if wire bonding is performed in a state where the adhesive 7 that adheres the
[0021]
First, in the second embodiment, as shown in FIG. 4, a holding
[0022]
The configuration of the second embodiment other than that described above is the same as that of the first embodiment. Therefore, also in the second embodiment, it is possible to obtain the same effects as those in the first embodiment.
[0023]
Next, in the third embodiment, as shown in FIG. 5, a pressing
[Brief description of the drawings]
FIG. 1 is a view showing a manufacturing process according to a first embodiment of the present invention, and FIG. 2 is a view showing a tensile strength test result of wire bonding. FIG. 3 is a view showing a tensile strength test. FIG. 4 is a longitudinal side view showing a second embodiment of the present invention. FIG. 5 is a diagram corresponding to FIG. 4 showing a third embodiment of the present invention.
1 is a wiring board, 2 is a conductor pattern, 2a is a bonding land, 3 is a semiconductor chip, 6 is a case (substrate support member), 7 is an adhesive, 8 is an aluminum wire, 9 is a conductor pattern, 9a is a bonding land, 13 Indicates a pressing member, 15 indicates a wire bonder, and 17 indicates a pressing member.
Claims (3)
前記基板を前記基板支持部材に接着剤を介して接着する接着工程と、
この接着工程を実行した後、前記接着剤を硬化させる前に、前記基板と前記基板支持部材との間をワイヤボンディングするボンディング工程と、
このボンディング工程を実行した後、前記接着剤を硬化させる硬化工程とを備え、更に、
前記ボンディング工程を実行するときに、前記基板が位置ずれしないように前記基板を押さえ付ける押さえ部材を、前記基板支持部材を載置固定する治具に設けたことを特徴とする半導体装置の製造方法。A method of manufacturing a semiconductor device, comprising: a substrate made of a wiring substrate, a semiconductor substrate, and the like; and a substrate support member for placing and supporting the substrate, and bonding the substrates to the substrate support member while wire bonding them together. In
An adhesion step of adhering the substrate to the substrate support member via an adhesive;
After performing this bonding step, before curing the adhesive, a bonding step of wire bonding between the substrate and the substrate support member,
And after performing this bonding step, a curing step of curing the adhesive,
A method of manufacturing a semiconductor device, wherein a pressing member for pressing the substrate so that the substrate is not displaced when the bonding step is performed is provided in a jig for mounting and fixing the substrate support member. .
前記基板支持部材を、前記配線基板を収容するケースにより構成したことを特徴とする請求項1記載の半導体装置の製造方法。The substrate is constituted by a wiring substrate,
The method of manufacturing a semiconductor device according to claim 1, wherein the substrate support member is configured by a case that accommodates the wiring substrate.
前記基板を前記基板支持部材に接着剤を介して接着する接着工程と、
この接着工程を実行した後、前記接着剤を硬化させる前に、前記基板と前記基板支持部材との間をワイヤボンディングするボンディング工程と、
このボンディング工程を実行した後、前記接着剤を硬化させる硬化工程とを備え、更に、
前記ボンディング工程を実行するときに、前記基板が位置ずれしないように前記基板を押さえ付ける押さえ部材を、ワイヤボンダーのヘッド部に設けたことを特徴とする半導体装置の製造方法。A method of manufacturing a semiconductor device, comprising: a substrate made of a wiring substrate, a semiconductor substrate, and the like; and a substrate support member for placing and supporting the substrate, and bonding the substrates to the substrate support member while wire bonding them together. In
An adhesion step of adhering the substrate to the substrate support member via an adhesive;
After performing this bonding step, before curing the adhesive, a bonding step of wire bonding between the substrate and the substrate support member,
And after performing this bonding step, a curing step of curing the adhesive,
A method of manufacturing a semiconductor device, comprising: a wire bonder head portion provided with a pressing member for pressing the substrate so that the substrate is not displaced when the bonding step is performed.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17292898A JP3726498B2 (en) | 1998-06-19 | 1998-06-19 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17292898A JP3726498B2 (en) | 1998-06-19 | 1998-06-19 | Manufacturing method of semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2000012594A JP2000012594A (en) | 2000-01-14 |
JP3726498B2 true JP3726498B2 (en) | 2005-12-14 |
Family
ID=15950959
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17292898A Expired - Fee Related JP3726498B2 (en) | 1998-06-19 | 1998-06-19 | Manufacturing method of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3726498B2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104392943A (en) * | 2014-12-05 | 2015-03-04 | 常州瑞华电力电子器件有限公司 | Preparation method of low-stress high-weldability nickel-plated electrode |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003039728A (en) * | 2001-07-31 | 2003-02-13 | Sanyo Electric Co Ltd | Circuit unit and optical printing head with the same |
JP2008227361A (en) * | 2007-03-15 | 2008-09-25 | Nec Corp | Electronic equipment |
-
1998
- 1998-06-19 JP JP17292898A patent/JP3726498B2/en not_active Expired - Fee Related
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN104392943A (en) * | 2014-12-05 | 2015-03-04 | 常州瑞华电力电子器件有限公司 | Preparation method of low-stress high-weldability nickel-plated electrode |
Also Published As
Publication number | Publication date |
---|---|
JP2000012594A (en) | 2000-01-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5161732B2 (en) | Manufacturing method of semiconductor device | |
JPH1022645A (en) | Manufacture of printed wiring board with cavity | |
JP2000082723A (en) | Functional emenet and board for mounting functional element as well as their connection method | |
JP3726498B2 (en) | Manufacturing method of semiconductor device | |
JP3531580B2 (en) | Bonding method | |
JP3649129B2 (en) | Semiconductor device manufacturing method and semiconductor device | |
JP3994327B2 (en) | Electronic component mounting method and anti-contamination chip used therefor | |
JPH06112239A (en) | Method and apparatus for insertion of chip into housing at inside of board by intermediate film | |
JPH11111756A (en) | Semiconductor device and its manufacture | |
JP2944589B2 (en) | COB mounting board and method of mounting IC chip on the board | |
JP2001223232A (en) | Manufacturing method of semiconductor device | |
JP3072602U (en) | Flexible PCB connection structure | |
JP4639473B2 (en) | Method for manufacturing printed wiring board | |
JP3001483B2 (en) | Lead frame, semiconductor device and method of manufacturing the same | |
JPH09181491A (en) | Method and structure for mounting semiconductor device | |
JP2812304B2 (en) | Repair method for flip-chip type semiconductor device | |
JP2002134641A (en) | Semiconductor device, manufacturing method of the semiconductor device and mounting method of the semiconductor device | |
KR100400762B1 (en) | Die bonding method of semiconductor wafer | |
JPH06260520A (en) | Wire bonding method | |
JP2006032470A (en) | Electronic device | |
JPH07201894A (en) | Manufacture of electronic parts mounting device | |
JPH0442547A (en) | Method of mounting components on printed board | |
JP2002141439A (en) | Semiconductor device and manufacturing method thereof | |
JPH01278032A (en) | Wire bonding process | |
JP3315057B2 (en) | Method for manufacturing semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20040713 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20050413 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20050419 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20050608 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20050705 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20050812 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20050906 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20050919 |
|
R150 | Certificate of patent or registration of utility model |
Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20081007 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20091007 Year of fee payment: 4 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101007 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20101007 Year of fee payment: 5 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20111007 Year of fee payment: 6 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121007 Year of fee payment: 7 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20121007 Year of fee payment: 7 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20131007 Year of fee payment: 8 |
|
LAPS | Cancellation because of no payment of annual fees |