JPH09181491A - Method and structure for mounting semiconductor device - Google Patents

Method and structure for mounting semiconductor device

Info

Publication number
JPH09181491A
JPH09181491A JP7339789A JP33978995A JPH09181491A JP H09181491 A JPH09181491 A JP H09181491A JP 7339789 A JP7339789 A JP 7339789A JP 33978995 A JP33978995 A JP 33978995A JP H09181491 A JPH09181491 A JP H09181491A
Authority
JP
Japan
Prior art keywords
semiconductor device
conductive film
anisotropic conductive
predetermined surface
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7339789A
Other languages
Japanese (ja)
Inventor
Minoru Takizawa
稔 滝澤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP7339789A priority Critical patent/JPH09181491A/en
Publication of JPH09181491A publication Critical patent/JPH09181491A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives

Landscapes

  • Supply And Installment Of Electrical Components (AREA)

Abstract

PROBLEM TO BE SOLVED: To reduce the man-hours for mounting a semiconductor device, in which an anisotropic conductive film with the same area as that of the semiconductor device is provided without using an insulating resin for sealing the outside of the semiconductor device. SOLUTION: In a first step, a given face 61 of a semiconductor device 60 is joined by thermal pressure to an anisotropic conductive film 70 having an area a little larger than that of the face 61. In this way, the anisotropic conductive film 70 is bonded to the given face 61 of the semiconductor device 60. In a second step the other face 75 than the bonded face 61 in the semiconductor device 60 is bonded by thermocompression to the part mounting face 51 of the board.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は半導体装置を異方性
導電膜を用いて基板に実装する半導体装置の実装方法及
び実装構造に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device mounting method and structure for mounting a semiconductor device on a substrate using an anisotropic conductive film.

【0002】[0002]

【従来の技術】半導体装置を基板に実装する方法の一つ
として、異方性導電膜を用いて行うフリップチップ実装
方法がある。この実装方法の従来技術を図8及び図9を
用いて説明する。
2. Description of the Related Art As one of methods for mounting a semiconductor device on a substrate, there is a flip chip mounting method using an anisotropic conductive film. A conventional technique of this mounting method will be described with reference to FIGS.

【0003】半導体装置であるところのベアICチップ
10が実装される基板20の部品実装面21には複数の
配線パターン22が導電材料にて形成されており、各配
線パターン22の先端の表面には金メッキがなされて電
極23が形成されている。また、各配線パターン22に
は、電極23の部分を除いてソルダーレジスト24で覆
われている。
A plurality of wiring patterns 22 are formed of a conductive material on a component mounting surface 21 of a substrate 20 on which a bare IC chip 10 which is a semiconductor device is mounted, and each wiring pattern 22 has a tip end surface. Is plated with gold to form an electrode 23. Further, each wiring pattern 22 is covered with a solder resist 24 except for the electrode 23.

【0004】ベアICチップ10は、所定の面11にA
l等の導電材料で形成された複数の電極12が基板20
の電極23に対応させて配置され、各電極12の表面に
は夫々バンプ13が形成されている。バンプ13はAu
又はSn−Pb合金等の金属材料で形成されている。
The bare IC chip 10 has an A on the predetermined surface 11.
a plurality of electrodes 12 formed of a conductive material such as
Bumps 13 are formed on the surface of each electrode 12, respectively. Bump 13 is Au
Alternatively, it is made of a metal material such as Sn—Pb alloy.

【0005】ベアICチップ10の実装のために用いら
れる異方性導電膜30は絶縁性樹脂31に導電粒子32
を混在させて形成されている。この異方性導電膜30は
ベアICチップ10の所定の面11の幅よりも大きな幅
を有するテープ状に形成され、一方の面が保護用テー
プ、他方の面が剥離テープで覆われた状態でリール(図
示せず)に巻回されている。
The anisotropic conductive film 30 used for mounting the bare IC chip 10 has an insulating resin 31 and conductive particles 32.
Are formed in a mixed manner. The anisotropic conductive film 30 is formed in a tape shape having a width larger than the width of the predetermined surface 11 of the bare IC chip 10, and one surface is covered with a protective tape and the other surface is covered with a peeling tape. It is wound around a reel (not shown).

【0006】ベアICチップ10の実装に際しては、ま
ず、リールに巻回された異方性導電膜30から保護用テ
ープを剥がして異方性導電膜30の一方の面を露出さ
せ、所望の長さに切断すると共に露出した一方の面側を
基板20に向けて異方性導電膜30を基板20の部品実
装面21に載置し、異方性導電膜30を剥離テープ側か
ら加圧、加熱(80度C、2秒程度)して異方性導電膜
30の仮接着を行う。この場合に、異方性導電膜30は
基板20の配線パターン22や電極23を覆うようにし
てベアICチップ10実装箇所に接着されるが、基板2
0に対する異方性導電膜30の位置ずれ等を考慮し、異
方性導電膜30の面積はベアICチップ10の所定の面
11の面積の2倍程度とされる。
When the bare IC chip 10 is mounted, first, the protective tape is peeled off from the anisotropic conductive film 30 wound on the reel to expose one surface of the anisotropic conductive film 30 to a desired length. Then, the anisotropic conductive film 30 is placed on the component mounting surface 21 of the substrate 20 with the exposed one surface side facing the substrate 20, and the anisotropic conductive film 30 is pressed from the release tape side, The anisotropic conductive film 30 is temporarily bonded by heating (80 ° C., about 2 seconds). In this case, the anisotropic conductive film 30 is adhered to the place where the bare IC chip 10 is mounted so as to cover the wiring pattern 22 and the electrodes 23 of the substrate 20.
Considering the positional deviation of the anisotropic conductive film 30 with respect to 0, the area of the anisotropic conductive film 30 is set to be about twice the area of the predetermined surface 11 of the bare IC chip 10.

【0007】次に、基板20に接着された異方性導電膜
30の剥離テープを剥がし、ベアICチップ10の所定
の面11が異方性導電膜30の他方の面に向くように設
定して異方性導電膜30上にベアICチップ10を載置
し、異方性導電膜30を加圧、加熱(180度C、20
秒程度)してベアICチップ10の本接着を行う。これ
で、基板20の部品実装面21とベアICチップ10の
所定の面11側とは異方性導電膜30の絶縁性樹脂31
を介して接合される。また、異方性導電膜30の導電粒
子32はバンプ13により基板20の電極23に押圧さ
れるので基板20とベアICチップ10とは電気的にも
接続される。
Next, the release tape of the anisotropic conductive film 30 adhered to the substrate 20 is peeled off, and the predetermined surface 11 of the bare IC chip 10 is set to face the other surface of the anisotropic conductive film 30. The bare IC chip 10 is placed on the anisotropic conductive film 30, and the anisotropic conductive film 30 is pressed and heated (180 ° C., 20 ° C.).
After about 2 seconds), the bare IC chip 10 is permanently bonded. Thus, the component mounting surface 21 of the substrate 20 and the predetermined surface 11 side of the bare IC chip 10 are separated from each other by the insulating resin 31 of the anisotropic conductive film 30.
Are joined through. Further, since the conductive particles 32 of the anisotropic conductive film 30 are pressed against the electrodes 23 of the substrate 20 by the bumps 13, the substrate 20 and the bare IC chip 10 are also electrically connected.

【0008】次に、ベアICチップ10を保護するべ
く、ベアICチップ10の周囲を囲むようにして異方性
導電膜30上に絶縁性樹脂40が封止される。しかしな
がら、この従来の実装方法では、所望の長さに切断した
異方性導電膜30を基板20の部品実装面21に載置し
て熱圧着による仮接着を行い、さらに、剥離テープを剥
がした後に、異方性導電膜30上にベアICチップ10
を載置して熱圧着による本接着を行う必要があり、ま
た、異方性導電膜30を基板20に仮接着するための熱
圧着用の専用ツールとベアICチップ10を異方性導電
膜30に本接着するための熱圧着用の専用ツールとの2
種類の専用ツールが必要であるので、ベアICチップ1
0の実装のための作業工数は非常に多くなっていた。ま
た、ベアICチップ10の実装を自動機を用いて行おう
とすると大変大掛かりな装置が必要であった。
Next, in order to protect the bare IC chip 10, an insulating resin 40 is sealed on the anisotropic conductive film 30 so as to surround the bare IC chip 10. However, in this conventional mounting method, the anisotropic conductive film 30 cut to a desired length is placed on the component mounting surface 21 of the substrate 20 to perform temporary adhesion by thermocompression bonding, and then the release tape is peeled off. After that, the bare IC chip 10 is formed on the anisotropic conductive film 30.
It is necessary to carry out the main bonding by placing the substrate and thermocompression bonding, and the dedicated tool for thermocompression bonding for temporarily bonding the anisotropic conductive film 30 to the substrate 20 and the bare IC chip 10 are anisotropic conductive film. 2 with a dedicated tool for thermocompression bonding for full adhesion to 30
Bare IC chip 1
The number of man-hours required for mounting 0 was very large. In addition, an attempt to mount the bare IC chip 10 using an automatic machine requires a very large-scale device.

【0009】また、基板20に対して熱圧着により接着
されている異方性導電膜30に対してベアICチップ1
0の熱圧着を行う構成であるので、ベアICチップ10
と異方性導電膜30との接合が不十分であり、従って、
ベアICチップ10の周囲を囲むようにして異方性導電
膜30上に絶縁性樹脂40を封止せねばならないという
不都合もあった。
Further, the bare IC chip 1 is attached to the anisotropic conductive film 30 adhered to the substrate 20 by thermocompression bonding.
The bare IC chip 10 has a structure for performing thermocompression bonding of 0.
Is insufficiently bonded to the anisotropic conductive film 30, and
There is also a disadvantage that the insulating resin 40 must be sealed on the anisotropic conductive film 30 so as to surround the bare IC chip 10.

【0010】さらにまた、異方性導電膜30の面積はベ
アICチップ10の所定の面11の面積の2倍程度の広
さを有し、又、異方性導電膜30は絶縁性樹脂40で覆
われているので、ベアICチップ10の周囲には他の電
子部品を実装することが困難であり、従って、基板の電
子部品実装効率が低下していた。
Furthermore, the area of the anisotropic conductive film 30 is about twice as large as the area of the predetermined surface 11 of the bare IC chip 10, and the anisotropic conductive film 30 is made of the insulating resin 40. Since it is covered with, it is difficult to mount other electronic components around the bare IC chip 10, and therefore, the electronic component mounting efficiency of the substrate is reduced.

【0011】[0011]

【発明が解決しようとする課題】上述のごとく、上記半
導体装置の実装方法では、半導体装置の実装のための作
業工数が非常に多くなり、半導体装置の実装を自動機を
用いて行おうとすると大変大掛かりな装置が必要であっ
た。
As described above, in the method of mounting a semiconductor device described above, the number of man-hours required for mounting the semiconductor device becomes very large, and it is difficult to mount the semiconductor device using an automatic machine. A large-scale device was needed.

【0012】また、半導体装置と異方性導電膜との接合
が不十分であり、従って、半導体装置の周囲を囲むよう
にして異方性導電膜上に絶縁性樹脂を封止せねばならな
いという不都合もあった。
In addition, there is a problem that the semiconductor device and the anisotropic conductive film are not sufficiently bonded to each other, and therefore the insulating resin must be sealed on the anisotropic conductive film so as to surround the semiconductor device. It was

【0013】また、異方性導電膜の面積は半導体装置の
面積より各段と広く、又、異方性導電膜は絶縁性樹脂で
覆われているので、半導体装置の周囲には他の電子部品
を実装することが困難であり、従って、基板の電子部品
実装効率が低下するという問題もあった。
Further, the area of the anisotropic conductive film is wider than the area of the semiconductor device, and since the anisotropic conductive film is covered with the insulating resin, other electrons are provided around the semiconductor device. There is also a problem that it is difficult to mount components, and thus the efficiency of mounting electronic components on the board is reduced.

【0014】本発明はこのような従来の欠点を解決する
べくなされたものであり、半導体装置の実装のための作
業工数の削減を図れ、半導体装置の実装を自動機を用い
て容易に行え、また、異方性導電膜の面積を半導体装置
の面積程度にすることが可能であり、半導体装置の周囲
を絶縁性樹脂で覆う必要もない半導体装置の実装方法を
提供する事を目的とする。
The present invention has been made to solve the above-mentioned conventional drawbacks, and it is possible to reduce the number of work steps for mounting a semiconductor device, and to easily mount the semiconductor device by using an automatic machine. Another object of the present invention is to provide a method of mounting a semiconductor device, in which the area of the anisotropic conductive film can be set to be about the area of the semiconductor device and it is not necessary to cover the periphery of the semiconductor device with an insulating resin.

【0015】[0015]

【課題を解決するための手段】請求項1に係る発明は、
絶縁性樹脂に導電粒子が混在してなる異方性導電膜を介
在させた状態で半導体装置の所定の面を基板の部品実装
面に加熱下で圧着することにより、前記半導体装置の所
定の面と前記基板の部品実装面とを前記絶縁性樹脂で接
合すると共に前記半導体装置の所定の面に形成されたバ
ンプとこのバンプに対向する前記基板の部品実装面に形
成の電極とを前記導電粒子を介して電気的に接続する半
導体装置の実装方法において、第1工程で、前記半導体
装置の所定の面よりも若干大きな面積とされた異方性導
電膜の一方の面に前記半導体装置の所定の面側を熱圧着
して前記半導体装置の所定の面及び前記所定の面側の周
側面に前記異方性導電膜を接着し、第2工程で、前記半
導体装置に接着された前記異方性導電膜の他方の面側を
前記基板の部品実装面に熱圧着することを特徴とする。
The invention according to claim 1 is
A predetermined surface of the semiconductor device is bonded by heating the predetermined surface of the semiconductor device to the component mounting surface of the substrate with the anisotropic conductive film in which conductive particles are mixed in the insulating resin interposed. And the component mounting surface of the substrate with the insulating resin, the bump formed on the predetermined surface of the semiconductor device and the electrode formed on the component mounting surface of the substrate facing the bump, the conductive particles. In a method of mounting a semiconductor device electrically connected via a semiconductor device, in a first step, a predetermined surface of the semiconductor device is formed on one surface of an anisotropic conductive film having an area slightly larger than a predetermined surface of the semiconductor device. Of the anisotropic conductive film bonded to the semiconductor device in a second step by thermocompression bonding the surface side of the semiconductor device to the predetermined surface of the semiconductor device and the peripheral side surface of the predetermined surface side. The other surface side of the conductive film is the component part of the board. Wherein the thermocompression bonding to the surface.

【0016】請求項1に係る発明によれば、基板に熱圧
着されてない状態の柔軟性に富んだ異方性導電膜に半導
体装置が最初に熱圧着されるので、異方性導電膜を半導
体装置の所定の面及び所定の面側の周側面に確実に密着
させることができる。また、異方性導電膜自体を所定の
位置に位置決めして半導体装置を熱圧着できるので、半
導体装置を異方性導電膜の所定位置に正確に位置付ける
ことができる。また、第一工程で、半導体装置を異方性
導電膜に熱圧着し、第2工程で、異方性導電膜が接着さ
れた状態の半導体装置を基板に熱圧着すれば良いので、
作業工数が少なくなり、又、これらの作業を半導体装置
の専用ツールのみで行える。
According to the first aspect of the invention, since the semiconductor device is first thermocompression-bonded to the flexible anisotropic conductive film which is not thermocompression-bonded to the substrate, the anisotropic conductive film is formed. The semiconductor device can be reliably brought into close contact with the predetermined surface and the peripheral side surface on the predetermined surface side. Moreover, since the semiconductor device can be thermocompression bonded by positioning the anisotropic conductive film itself at a predetermined position, the semiconductor device can be accurately positioned at a predetermined position of the anisotropic conductive film. Further, in the first step, the semiconductor device may be thermocompression bonded to the anisotropic conductive film, and in the second step, the semiconductor device having the anisotropic conductive film bonded thereto may be thermocompression bonded to the substrate.
The number of man-hours is reduced, and these works can be performed only by the dedicated tool of the semiconductor device.

【0017】請求項2に係る発明は、請求項1に係る発
明において、前記異方性導電膜は前記半導体装置の所定
の面よりも若干大きな面積ごとに切り込みが形成されて
なる複数の領域を有し、この複数の領域のうちの1つの
領域部分が前記半導体装置の所定の面に接着されること
を特徴とする。
According to a second aspect of the present invention, in the first aspect of the present invention, the anisotropic conductive film has a plurality of regions each having a notch formed in an area slightly larger than a predetermined surface of the semiconductor device. One of the plurality of regions is bonded to a predetermined surface of the semiconductor device.

【0018】従って、半導体装置の所定の面を異方性導
電膜の所望の領域内に位置付けて異方性導電膜に熱圧着
することにより、異方性導電膜の所望の領域部分を半導
体装置の所定の面及び所定の面側の周側面にに密着させ
ることができる。
Therefore, by positioning a predetermined surface of the semiconductor device in a desired region of the anisotropic conductive film and thermocompressing the anisotropic conductive film, the desired region portion of the anisotropic conductive film is formed. Can be closely attached to the predetermined surface and the peripheral side surface on the predetermined surface side.

【0019】請求項3に係る発明は、請求項2に係る発
明において、前記異方性導電膜は剥離シート上に形成さ
れていることを特徴とする。従って、半導体装置の所定
の面を異方性導電膜の所望の領域内に位置付けて異方性
導電膜に熱圧着した場合に、当該異方性導電膜の所望の
領域部分のみが剥離シートから剥離して半導体装置の所
定の面及び所定の面側の周側面にに密着する。
The invention according to claim 3 is the invention according to claim 2, characterized in that the anisotropic conductive film is formed on a release sheet. Therefore, when the predetermined surface of the semiconductor device is positioned in a desired region of the anisotropic conductive film and thermocompression-bonded to the anisotropic conductive film, only the desired region portion of the anisotropic conductive film is removed from the release sheet. It is peeled off and adheres to a predetermined surface of the semiconductor device and a peripheral side surface on the predetermined surface side.

【0020】請求項4に係る半導体装置の実装構造は、
絶縁性樹脂に導電粒子が混在してなる異方性導電膜の一
方の面に半導体装置の所定の面及びこの所定の面側の周
側面が接着され、前記異方性導電膜の他方の面側が基板
の部品実装面に接着されていることを特徴とする。
A mounting structure of a semiconductor device according to claim 4 is
The predetermined surface of the semiconductor device and the peripheral side surface on the predetermined surface side are adhered to one surface of the anisotropic conductive film in which conductive particles are mixed in the insulating resin, and the other surface of the anisotropic conductive film The side is adhered to the component mounting surface of the substrate.

【0021】請求項4に係る発明によれば、半導体装置
の所定の面及びこの所定の面側の周側面に異方性導電膜
が接着されているので、半導体装置の周囲を絶縁性樹脂
で覆う必要はない。
According to the invention of claim 4, since the anisotropic conductive film is adhered to the predetermined surface of the semiconductor device and the peripheral side surface on the predetermined surface side, the periphery of the semiconductor device is made of the insulating resin. No need to cover.

【0022】[0022]

【発明の実施の形態】以下、本発明の実施の形態を図1
乃至図7を参照して詳述する。ここに、図1は半導体装
置に接着された状態の異方性導電膜を基板に熱圧着する
状態を示す図、図2は半導体装置を異方性導電膜に熱圧
着する状態を示す図、図3は異方性導電膜が接着された
状態の半導体装置を示す図、図4は異方性導電膜を介し
て接着された半導体装置及び基板を示す図、図5は切り
込みの形成された異方性導電膜の平面図、図6は図5の
異方性導電膜の側面図、図7は半導体装置の実装工程図
である。
FIG. 1 is a block diagram showing an embodiment of the present invention.
It will be described in detail with reference to FIGS. 1 is a diagram showing a state in which an anisotropic conductive film bonded to a semiconductor device is thermocompression bonded to a substrate, and FIG. 2 is a diagram showing a state in which a semiconductor device is thermocompression bonded to an anisotropic conductive film. FIG. 3 is a diagram showing a semiconductor device in which an anisotropic conductive film is bonded, FIG. 4 is a diagram showing a semiconductor device and a substrate bonded via an anisotropic conductive film, and FIG. 5 is a cut. 6 is a plan view of the anisotropic conductive film, FIG. 6 is a side view of the anisotropic conductive film of FIG. 5, and FIG. 7 is a mounting process diagram of the semiconductor device.

【0023】本発明の実施の形態に係る基板50はガラ
スエポキシ樹脂等にて形成され、図1に示すように、半
導体装置であるところのベアICチップ60が実装され
る部品実装面51には複数の配線パターン52が導電材
料にて形成されている。また、各配線パターン52の先
端の表面には金メッキがなされて電極53が形成され、
かつ、各配線パターン52は、電極53の部分を除いて
ソルダーレジスト54で覆われている。
The substrate 50 according to the embodiment of the present invention is formed of glass epoxy resin or the like, and as shown in FIG. 1, the component mounting surface 51 on which the bare IC chip 60, which is a semiconductor device, is mounted is mounted. The plurality of wiring patterns 52 are formed of a conductive material. Further, the surface of the tip of each wiring pattern 52 is plated with gold to form an electrode 53,
Moreover, each wiring pattern 52 is covered with a solder resist 54 except for the electrode 53.

【0024】ベアICチップ60は、所定の面61にA
l等の導電材料で形成された複数の電極62が基板50
の電極53に対応させて配置され、各電極62の表面に
は夫々バンプ63が形成されている。バンプ63はAu
又はSn−Pb合金等の金属材料で形成されている。
The bare IC chip 60 has a predetermined surface 61
a plurality of electrodes 62 formed of a conductive material such as
Bumps 63 are formed on the surface of each electrode 62. Bump 63 is Au
Alternatively, it is made of a metal material such as Sn—Pb alloy.

【0025】ベアICチップ60の実装のために用いら
れる異方性導電膜70は、絶縁性樹脂71に導電粒子7
2を混在させて形成されている。この異方性導電膜70
は、図5及び図6に示す用に、面積の広いシート形状を
しており、剥離シート73に貼付されている。また、こ
の異方性導電膜70には上面(一方の面)74から下面
(他方の面)75に至るように切り込み76が形成さ
れ、切り込み76で囲まれた異方性導電膜70の部分7
01はベアICチップ60の所定の面61と同様の形状
とされ、その面積は所定の面61の面積よりも若干大き
く(本実施の形態では、1.05倍程度)されている。
The anisotropic conductive film 70 used for mounting the bare IC chip 60 includes an insulating resin 71, conductive particles 7 and the like.
It is formed by mixing two. This anisotropic conductive film 70
As shown in FIGS. 5 and 6, has a sheet shape with a large area and is attached to the release sheet 73. Further, a cut 76 is formed in the anisotropic conductive film 70 from the upper surface (one surface) 74 to the lower surface (the other surface) 75, and the portion of the anisotropic conductive film 70 surrounded by the cut 76. 7
01 has the same shape as the predetermined surface 61 of the bare IC chip 60, and its area is slightly larger than the area of the predetermined surface 61 (about 1.05 times in this embodiment).

【0026】次に、ベアICチップ60の実装工程を図
7を参照しながら説明する。第1工程においては、バン
プ63が形成されているベアICチップ60の所定の面
61側に異方性導電膜70を転写する。この工程では、
図2に示すように、ベアICチップ60の上面64側を
ベアICチップ60に対応する形状とされた専用のヒー
タチップ81で吸着すると共にベアICチップ60を加
熱し、所定の位置に位置付けられた異方性導電膜70の
うちの転写をする部分701上にベアICチップ60を
保持したヒータチップ81を位置付ける。そして、この
ヒータチップ81を下降させベアICチップ60の所定
の面61側を異方性導電膜70の一方の面74に押しつ
けて異方性導電膜70を加圧、加熱(80度C、2秒程
度)し、ベアICチップ60に異方性導電膜70の部分
701を転写する。
Next, the mounting process of the bare IC chip 60 will be described with reference to FIG. In the first step, the anisotropic conductive film 70 is transferred to the side of the bare IC chip 60 on which the bumps 63 are formed on the predetermined surface 61. In this step,
As shown in FIG. 2, the upper surface 64 side of the bare IC chip 60 is adsorbed by a dedicated heater chip 81 having a shape corresponding to the bare IC chip 60, the bare IC chip 60 is heated, and the bare IC chip 60 is positioned at a predetermined position. The heater chip 81 holding the bare IC chip 60 is positioned on the transfer portion 701 of the anisotropic conductive film 70. Then, the heater chip 81 is lowered to press the predetermined surface 61 side of the bare IC chip 60 against one surface 74 of the anisotropic conductive film 70 to pressurize and heat the anisotropic conductive film 70 (80 ° C., Then, the portion 701 of the anisotropic conductive film 70 is transferred to the bare IC chip 60.

【0027】この場合に、異方性導電膜70の部分70
1の面積はベアICチップ60の所定の面61の面積よ
りもわずかに大きくされているにすぎないが、異方性導
電膜70は所定の位置に正確に位置付けられているの
で、異方性導電膜70の部分701からベアICチップ
60がはみ出すことはない。また、基板50に熱圧着さ
れてない状態の柔軟性に富んだ異方性導電膜70にベア
ICチップ60が最初に熱圧着されるので、図3に示す
ように、異方性導電膜70はベアICチップ60の所定
の面61及び所定の面61側の周側面65に確実に密着
する。尚、ヒータチップ81を上昇させることにより、
異方性導電膜70のうちのベアICチップ60に接着し
た部分701は剥離シート73から剥離する。
In this case, the portion 70 of the anisotropic conductive film 70 is formed.
The area of 1 is only slightly larger than the area of the predetermined surface 61 of the bare IC chip 60, but the anisotropic conductive film 70 is accurately positioned at the predetermined position. The bare IC chip 60 does not protrude from the portion 701 of the conductive film 70. Further, since the bare IC chip 60 is first thermocompression-bonded to the highly flexible anisotropic conductive film 70 which is not thermocompression-bonded to the substrate 50, as shown in FIG. Securely adheres to the predetermined surface 61 of the bare IC chip 60 and the peripheral side surface 65 on the side of the predetermined surface 61. By raising the heater chip 81,
A portion 701 of the anisotropic conductive film 70 adhered to the bare IC chip 60 is peeled off from the peeling sheet 73.

【0028】第2工程においては、ベアICチップ60
に接着している異方性導電膜70の他方の面75を基板
50に接着する。この工程においては、図1に示すよう
に、基板50はヒータステージ82上にセットされ加熱
される。そして、ベアICチップ60を保持したヒータ
チップ81を基板50上の所定位置に位置付け、このヒ
ータチップ81を下降させ、ベアICチップ60に接着
されている異方性導電膜70の他方の面75を基板50
に押しつけて異方性導電膜70を加圧、加熱(180度
C、20秒程度)する。
In the second step, the bare IC chip 60 is used.
The other surface 75 of the anisotropic conductive film 70 adhered to the substrate 50 is adhered to the substrate 50. In this step, as shown in FIG. 1, the substrate 50 is set on the heater stage 82 and heated. Then, the heater chip 81 holding the bare IC chip 60 is positioned at a predetermined position on the substrate 50, the heater chip 81 is lowered, and the other surface 75 of the anisotropic conductive film 70 bonded to the bare IC chip 60 is placed. The board 50
Then, the anisotropic conductive film 70 is pressed and heated (180 ° C., about 20 seconds).

【0029】これで、図4に示すように、基板50の部
品実装面51側とベアICチップ60の所定の面61側
とは異方性導電膜70の絶縁性樹脂71を介して接合さ
れる。また、異方性導電膜70の導電粒子72はバンプ
63により基板50の電極53に押圧されるので基板5
0とベアICチップ60とは電気的にも接続される。こ
の場合に、前述したように、異方性導電膜70はベアI
Cチップ60の所定の面61及び所定の面61側の周側
面65に確実に密着している。従って、ベアICチップ
60の周囲を絶縁性樹脂で封止する必要はない。また、
本実施の形態に係る実装方法では、剥離シート73上の
異方性導電膜70の部分701にベアICチップ60を
熱圧着し、異方性導電膜70が接着されたベアICチッ
プ60を基板50に熱圧着するという単純、かつ、少な
い作業工数でベアICチップ60を基板50に実装でき
るので、この作業工程の自動化を容易に行える。
Then, as shown in FIG. 4, the component mounting surface 51 side of the substrate 50 and the predetermined surface 61 side of the bare IC chip 60 are bonded together via the insulating resin 71 of the anisotropic conductive film 70. It Further, since the conductive particles 72 of the anisotropic conductive film 70 are pressed against the electrodes 53 of the substrate 50 by the bumps 63, the substrate 5
0 and the bare IC chip 60 are also electrically connected. In this case, as described above, the anisotropic conductive film 70 is bare I.
The C chip 60 is firmly attached to the predetermined surface 61 and the peripheral side surface 65 on the side of the predetermined surface 61. Therefore, it is not necessary to seal the periphery of the bare IC chip 60 with an insulating resin. Also,
In the mounting method according to the present embodiment, the bare IC chip 60 is thermocompression-bonded to the portion 701 of the anisotropic conductive film 70 on the release sheet 73, and the bare IC chip 60 to which the anisotropic conductive film 70 is bonded is formed on the substrate. Since the bare IC chip 60 can be mounted on the substrate 50 with a simple operation of thermocompression bonding to the substrate 50 and with a small number of working steps, automation of this working process can be easily performed.

【0030】[0030]

【発明の効果】以上説明したように、請求項1に係る半
導体装置の実装方法によれば、第1工程で、半導体装置
を異方性導電膜に熱圧着し、第2工程で、異方性導電膜
が接着された状態の半導体装置を基板に熱圧着するだけ
で良く、又、これらの作業を半導体装置の専用ツールの
みで行えるので、半導体装置実装の作業工数の削減を図
れ、又、半導体装置の実装を自動機を用いて容易に行え
る。また、半導体装置を異方性導電膜に正確に位置づけ
られるで、異方性導電膜の面積を半導体装置の面積程度
にまで小さくすることが可能であり、従って、半導体装
置を実装したことによって基板の電子部品実装効率が低
下することもない。また、異方性導電膜は半導体装置の
所定の面及び所定の面側の周側面に確実に密着するの
で、半導体装置の周囲を別の絶縁性樹脂で覆う必要もな
い。
As described above, according to the semiconductor device mounting method of the first aspect, the semiconductor device is thermocompression-bonded to the anisotropic conductive film in the first step, and anisotropic in the second step. It suffices to thermocompress the semiconductor device with the conductive conductive film adhered to the substrate, and since these operations can be performed only with the dedicated tool for the semiconductor device, it is possible to reduce the man-hours for mounting the semiconductor device. The semiconductor device can be easily mounted using an automatic machine. Further, since the semiconductor device can be accurately positioned on the anisotropic conductive film, the area of the anisotropic conductive film can be reduced to about the area of the semiconductor device. Therefore, by mounting the semiconductor device on the substrate, The electronic component mounting efficiency of does not decrease. Further, since the anisotropic conductive film surely adheres to the predetermined surface of the semiconductor device and the peripheral side surface on the predetermined surface side, it is not necessary to cover the periphery of the semiconductor device with another insulating resin.

【0031】また、請求項2に係る発明は、請求項1に
係る発明において、異方性導電膜は半導体装置の所定の
面よりも若干大きな面積ごとに切り込みが形成されてな
る複数の領域を有しており、半導体装置の所定の面を異
方性導電膜の所望の領域内に位置付けて異方性導電膜に
熱圧着するだけで、異方性導電膜の所望の領域部分を半
導体装置の所定の面及び所定の面側の周側面にに密着さ
せることができるので、第1工程の作業性は向上する。
According to a second aspect of the invention, in the invention according to the first aspect, the anisotropic conductive film has a plurality of regions each having a notch formed in an area slightly larger than a predetermined surface of the semiconductor device. The semiconductor device has a desired area portion of the anisotropic conductive film only by positioning a predetermined surface of the semiconductor device in a desired area of the anisotropic conductive film and thermocompressing the anisotropic conductive film. Since it can be closely attached to the predetermined surface and the peripheral side surface on the predetermined surface side, the workability of the first step is improved.

【0032】また、請求項3に係る発明は、請求項2に
係る発明において、異方性導電膜は剥離シート上に形成
されており、半導体装置の所定の面を異方性導電膜の所
望の領域内に位置付けて異方性導電膜に熱圧着すると、
当該異方性導電膜の所望の領域部分のみが剥離シートか
ら剥離して半導体装置の所定の面及び所定の面側の周側
面にに密着するので、第1工程の作業性はさらに向上す
る。
According to a third aspect of the invention, in the invention according to the second aspect, the anisotropic conductive film is formed on a release sheet, and a predetermined surface of the semiconductor device is provided with the anisotropic conductive film. When positioned in the area of and thermocompression bonded to the anisotropic conductive film,
Since only the desired region of the anisotropic conductive film is peeled off from the release sheet and adheres to the predetermined surface of the semiconductor device and the peripheral side surface of the predetermined surface side, the workability of the first step is further improved.

【0033】請求項4に係る発明によれば、半導体装置
の所定の面及びこの所定の面側の周側面に異方性導電膜
が接着されているので、半導体装置の周囲を絶縁性樹脂
で覆う必要はない。
According to the invention of claim 4, since the anisotropic conductive film is adhered to the predetermined surface of the semiconductor device and the peripheral side surface of the predetermined surface side, the periphery of the semiconductor device is made of the insulating resin. No need to cover.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態に係る図であり、半導体装
置に接着された状態の異方性導電膜を基板に熱圧着する
状態を示す図。
FIG. 1 is a diagram according to an embodiment of the present invention, showing a state in which an anisotropic conductive film bonded to a semiconductor device is thermocompression bonded to a substrate.

【図2】本発明の実施の形態に係る図であり、半導体装
置を異方性導電膜に熱圧着する状態を示す図。
FIG. 2 is a diagram according to an embodiment of the present invention, showing a state in which a semiconductor device is thermocompression bonded to an anisotropic conductive film.

【図3】本発明の実施の形態に係る図であり、異方性導
電膜が接着された状態の半導体装置を示す図。
FIG. 3 is a diagram according to an embodiment of the present invention, showing a semiconductor device with an anisotropic conductive film bonded thereto.

【図4】本発明の実施の形態に係る図であり、異方性導
電膜を介して接着された半導体装置及び基板を示す図。
FIG. 4 is a diagram according to an embodiment of the present invention, showing a semiconductor device and a substrate bonded to each other through an anisotropic conductive film.

【図5】本発明の実施の形態に係る図であり、切り込み
の形成された異方性導電膜の平面図。
FIG. 5 is a view according to the embodiment of the present invention, which is a plan view of an anisotropic conductive film in which a notch is formed.

【図6】図5の異方性導電膜の側面図。6 is a side view of the anisotropic conductive film of FIG.

【図7】本発明の実施の形態に係る半導体装置の実装工
程図。
FIG. 7 is a mounting process diagram of the semiconductor device according to the embodiment of the present invention.

【図8】異方性導電膜を介して接着された半導体装置及
び基板の従来例を示す図。
FIG. 8 is a view showing a conventional example of a semiconductor device and a substrate bonded via an anisotropic conductive film.

【図9】従来の半導体装置の実装工程図。FIG. 9 is a mounting process diagram of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

50 基板 51 部品実装面 53 電極 60 半導体装置(ベアICチップ) 61 所定の面 63 バンプ 65 周側面 70 異方性導電膜 71 絶縁性樹脂 72 導電粒子 50 substrate 51 component mounting surface 53 electrode 60 semiconductor device (bare IC chip) 61 predetermined surface 63 bump 65 peripheral side surface 70 anisotropic conductive film 71 insulating resin 72 conductive particles

Claims (4)

【特許請求の範囲】[Claims] 【請求項1】 絶縁性樹脂に導電粒子が混在してなる異
方性導電膜を介在させた状態で半導体装置の所定の面を
基板の部品実装面に加熱下で圧着することにより、前記
半導体装置の所定の面と前記基板の部品実装面とを前記
絶縁性樹脂で接合すると共に前記半導体装置の所定の面
に形成されたバンプとこのバンプに対向する前記基板の
部品実装面に形成の電極とを前記導電粒子を介して電気
的に接続する半導体装置の実装方法において、第1工程
で、前記半導体装置の所定の面よりも若干大きな面積と
された異方性導電膜の一方の面に前記半導体装置の所定
の面側を熱圧着して前記半導体装置の所定の面及び前記
所定の面側の周側面に前記異方性導電膜を接着し、第2
工程で、前記半導体装置に接着された前記異方性導電膜
の他方の面側を前記基板の部品実装面に熱圧着すること
を特徴とする半導体装置の実装方法。
1. The semiconductor according to claim 1, wherein a predetermined surface of a semiconductor device is pressure-bonded to a component mounting surface of a substrate under heating with an anisotropic conductive film in which conductive particles are mixed in an insulating resin. A predetermined surface of the device and a component mounting surface of the substrate are joined with the insulating resin, and a bump formed on the predetermined surface of the semiconductor device and an electrode formed on the component mounting surface of the substrate facing the bump. In the method for mounting a semiconductor device, wherein is electrically connected to each other via the conductive particles, in the first step, one surface of the anisotropic conductive film having an area slightly larger than a predetermined surface of the semiconductor device is attached. The predetermined surface side of the semiconductor device is thermocompression bonded to bond the anisotropic conductive film to the predetermined surface of the semiconductor device and the peripheral side surface of the predetermined surface side, and
In the step, the other surface side of the anisotropic conductive film adhered to the semiconductor device is thermocompression-bonded to the component mounting surface of the substrate.
【請求項2】 前記異方性導電膜は前記半導体装置の所
定の面よりも若干大きな面積ごとに切り込みが形成され
てなる複数の領域を有し、この複数の領域のうちの1つ
の領域部分が前記半導体装置の所定の面に接着されるこ
とを特徴とする請求項1に記載の半導体装置の実装方
法。
2. The anisotropic conductive film has a plurality of regions each having a notch formed in an area slightly larger than a predetermined surface of the semiconductor device, and one region portion of the plurality of regions is formed. The method for mounting a semiconductor device according to claim 1, wherein is bonded to a predetermined surface of the semiconductor device.
【請求項3】 前記異方性導電膜は剥離シート上に形成
されていることを特徴とする請求項2に記載の半導体装
置の実装方法。
3. The method for mounting a semiconductor device according to claim 2, wherein the anisotropic conductive film is formed on a release sheet.
【請求項4】 絶縁性樹脂に導電粒子が混在してなる異
方性導電膜の一方の面に半導体装置の所定の面及びこの
所定の面側の周側面が接着され、前記異方性導電膜の他
方の面側が基板の部品実装面に接着されていることを特
徴とする半導体装置の実装構造。
4. A predetermined surface of a semiconductor device and a peripheral side surface on the predetermined surface side are adhered to one surface of an anisotropic conductive film in which conductive particles are mixed in an insulating resin, and the anisotropic conductive film is formed. A mounting structure of a semiconductor device, wherein the other surface side of the film is adhered to a component mounting surface of a substrate.
JP7339789A 1995-12-27 1995-12-27 Method and structure for mounting semiconductor device Pending JPH09181491A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7339789A JPH09181491A (en) 1995-12-27 1995-12-27 Method and structure for mounting semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7339789A JPH09181491A (en) 1995-12-27 1995-12-27 Method and structure for mounting semiconductor device

Publications (1)

Publication Number Publication Date
JPH09181491A true JPH09181491A (en) 1997-07-11

Family

ID=18330826

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7339789A Pending JPH09181491A (en) 1995-12-27 1995-12-27 Method and structure for mounting semiconductor device

Country Status (1)

Country Link
JP (1) JPH09181491A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002503836A (en) * 1998-02-17 2002-02-05 サーノフ コーポレイション Large area display structure seal
US7354803B2 (en) * 2003-10-06 2008-04-08 Seiko Epson Corporation Method for manufacturing substrate conjugate, substrate conjugate, method for manufacturing electro-optical apparatus, and electro optical apparatus
JP2009208285A (en) * 2008-03-03 2009-09-17 Seiko Epson Corp Thermal head and thermal printer
WO2018008066A1 (en) * 2016-07-04 2018-01-11 株式会社鈴木 Transfer method and mounting method

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002503836A (en) * 1998-02-17 2002-02-05 サーノフ コーポレイション Large area display structure seal
JP2009288810A (en) * 1998-02-17 2009-12-10 Transpacific Infinity Llc Sealing of large area display structure
US7354803B2 (en) * 2003-10-06 2008-04-08 Seiko Epson Corporation Method for manufacturing substrate conjugate, substrate conjugate, method for manufacturing electro-optical apparatus, and electro optical apparatus
JP2009208285A (en) * 2008-03-03 2009-09-17 Seiko Epson Corp Thermal head and thermal printer
WO2018008066A1 (en) * 2016-07-04 2018-01-11 株式会社鈴木 Transfer method and mounting method
KR20190024869A (en) * 2016-07-04 2019-03-08 가부시키가이샤 스즈키 Transfer method and mounting method
TWI710294B (en) * 2016-07-04 2020-11-11 日商鈴木股份有限公司 installation method

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