JP2002141439A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof

Info

Publication number
JP2002141439A
JP2002141439A JP2000335492A JP2000335492A JP2002141439A JP 2002141439 A JP2002141439 A JP 2002141439A JP 2000335492 A JP2000335492 A JP 2000335492A JP 2000335492 A JP2000335492 A JP 2000335492A JP 2002141439 A JP2002141439 A JP 2002141439A
Authority
JP
Japan
Prior art keywords
semiconductor device
semiconductor
semiconductor element
bumper
reinforcing member
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2000335492A
Other languages
Japanese (ja)
Other versions
JP3580244B2 (en
Inventor
Tadahiko Sakai
忠彦 境
Mitsuru Osono
満 大園
Ken Maeda
憲 前田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2000335492A priority Critical patent/JP3580244B2/en
Priority to TW090125113A priority patent/TW522531B/en
Priority to US09/977,220 priority patent/US6797544B2/en
Priority to KR1020010064018A priority patent/KR100762208B1/en
Priority to CNB01135819XA priority patent/CN1221028C/en
Publication of JP2002141439A publication Critical patent/JP2002141439A/en
Application granted granted Critical
Publication of JP3580244B2 publication Critical patent/JP3580244B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/6834Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544Marks applied to semiconductor devices or parts
    • H01L2223/54473Marks applied to semiconductor devices or parts for use after dicing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27Manufacturing methods
    • H01L2224/274Manufacturing methods by blanket deposition of the material of the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161Cap
    • H01L2924/1615Shape
    • H01L2924/16152Cap comprising a cavity for hosting the device, e.g. U-shaped cap
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a manufacturing method thereof which is easy to handle a thinned semiconductor element. SOLUTION: The semiconductor device 7 has a bumper 4' being a reinforcing member bonded with adhesives 5 to the backside of a semiconductor element 1' to its electrode forming surface. The element 1' is bonded to the bumper 4' deformably with the low-elastic modulus adhesives 5 easily expandable/ shrinkable after bonding. This facilitates handling the semiconductor device 7 and allows the element 1' to be deformed according to the deformation of a substrate 11 after mounting, thereby effectively relaxing thermal stresses in a heat cycle.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体素子の電極
形成面の裏面に接着材により補強部材を接合して成る半
導体装置および半導体装置の製造方法に関するものであ
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a reinforcing member is bonded to the back surface of an electrode forming surface of a semiconductor element with an adhesive, and a method of manufacturing the semiconductor device.

【0002】[0002]

【従来の技術】電子機器の基板などに実装される半導体
装置は、ウェハ状態で回路パターン形成が行われた半導
体素子にリードフレームのピンや金属バンプなどを接続
するとともに樹脂などで封止するパッケージング工程を
経て製造されている。最近の電子機器の小型化に伴って
半導体装置の小型化も進み、中でも半導体素子を薄くす
る取り組みが活発に行われている。
2. Description of the Related Art A semiconductor device mounted on a substrate or the like of an electronic device is a package in which a semiconductor element having a circuit pattern formed in a wafer state is connected with a lead frame pin or a metal bump and sealed with a resin or the like. It is manufactured through a aging process. With the recent miniaturization of electronic devices, miniaturization of semiconductor devices has progressed, and in particular, efforts have been actively made to make semiconductor elements thinner.

【0003】薄化された半導体素子は外力に対する強度
が弱くハンドリング時のダメージを受けやすいことか
ら、従来より薄化された半導体素子を用いた半導体装置
は、半導体素子を補強のための樹脂層で封止する構造が
一般的である。
Since a thinned semiconductor element has low strength against external force and is easily damaged during handling, a semiconductor device using a thinned semiconductor element in the related art has a resin layer for reinforcing the semiconductor element. A structure for sealing is common.

【0004】[0004]

【発明が解決しようとする課題】しかしながら、薄い半
導体素子の表面に樹脂層を形成する工程においては、樹
脂層形成時の硬化収縮による半導体素子の反りや割れな
どの不具合が発生しやすいものであった。この問題は半
導体素子が薄化するほど顕著となり、100μm以下の
極薄の半導体素子では樹脂封止することすら困難な状況
となる。
However, in the process of forming a resin layer on the surface of a thin semiconductor element, defects such as warping and cracking of the semiconductor element due to curing shrinkage during the formation of the resin layer are likely to occur. Was. This problem becomes more conspicuous as the semiconductor element becomes thinner, and it becomes difficult to seal the semiconductor element even with a very thin semiconductor element having a thickness of 100 μm or less.

【0005】そこで本発明は、薄化された半導体素子の
取り扱いが簡単な半導体装置および半導体装置の製造方
法を提供することを目的とする。
Accordingly, an object of the present invention is to provide a semiconductor device in which a thinned semiconductor element can be easily handled and a method of manufacturing the semiconductor device.

【0006】[0006]

【課題を解決するための手段】請求項1記載の半導体装
置は、外部接続用の電極が形成された電極形成面を有す
る半導体素子と、前記電極形成面の裏面に低弾性係数の
樹脂接着材を介して接合された補強部材とを備えた。
According to a first aspect of the present invention, there is provided a semiconductor device having a semiconductor element having an electrode forming surface on which electrodes for external connection are formed, and a resin adhesive having a low elastic coefficient on a back surface of the electrode forming surface. And a reinforcing member joined through the reinforcing member.

【0007】請求項2記載の半導体装置は、請求項1記
載の半導体装置であって、前記補強部材の曲げ剛性は、
半導体素子の曲げ剛性よりも大きい。
According to a second aspect of the present invention, in the semiconductor device according to the first aspect, the bending rigidity of the reinforcing member is:
It is larger than the bending rigidity of the semiconductor element.

【0008】請求項3記載の半導体装置は、請求項1記
載の半導体装置であって、前記樹脂接着材は、半導体素
子の変形を許容する状態でこの半導体素子を補強部材に
接合している。
A semiconductor device according to a third aspect is the semiconductor device according to the first aspect, wherein the resin adhesive joins the semiconductor element to a reinforcing member in a state where the semiconductor element is allowed to deform.

【0009】請求項4記載の半導体装置の製造方法は、
半導体素子の外部接続用の電極が形成された電極形成面
の裏面に低弾性係数の樹脂接着材を介して補強部材を接
合して成る半導体装置を製造する半導体装置の製造方法
であって、複数の半導体素子が形成された半導体ウェハ
の電極形成面の裏面を削る薄化工程と、薄化工程後の前
記半導体素子の裏面に低弾性係数の樹脂接着材を介して
補強部材を接合する接合工程とを含む。
According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
A method of manufacturing a semiconductor device for manufacturing a semiconductor device in which a reinforcing member is joined to a back surface of an electrode forming surface on which an electrode for external connection of a semiconductor element is formed via a resin adhesive having a low elastic modulus, Thinning step of shaving the back surface of the electrode forming surface of the semiconductor wafer on which the semiconductor element is formed, and a joining step of joining a reinforcing member to the back surface of the semiconductor element after the thinning step via a resin adhesive having a low elastic modulus. And

【0010】請求項5記載の半導体装置の製造方法は、
請求項4記載の半導体装置の製造方法であって、前記接
合工程において、半導体ウェハ状態の複数の半導体素子
を一括して補強部材に接合する。
According to a fifth aspect of the present invention, there is provided a method of manufacturing a semiconductor device.
5. The method of manufacturing a semiconductor device according to claim 4, wherein in the bonding step, a plurality of semiconductor elements in a semiconductor wafer state are bonded together to a reinforcing member.

【0011】本発明によれば、半導体装置を半導体素子
の電極形成面の裏面に低弾性係数の樹脂接着材を介して
補強部材を接合した構成とすることにより、薄化された
半導体素子の取り扱いが容易で実装後の信頼性が高い半
導体装置を実現することができる。
According to the present invention, the semiconductor device has a structure in which a reinforcing member is bonded to the back surface of the electrode forming surface of the semiconductor element via a resin adhesive having a low elastic modulus, thereby handling the thinned semiconductor element. And a semiconductor device having high reliability after mounting can be realized.

【0012】[0012]

【発明の実施の形態】(実施の形態1)図1、図2は本
発明の実施の形態1の半導体装置の製造方法の工程説明
図、図3は本発明の実施の形態1の半導体装置の斜視
図、図4は本発明の実施の形態1の半導体装置の実装方
法の説明図である。なお、図1、図2は半導体装置の製
造方法を工程順に示している。
(Embodiment 1) FIGS. 1 and 2 are process explanatory views of a method for manufacturing a semiconductor device according to Embodiment 1 of the present invention, and FIG. 3 is a semiconductor device according to Embodiment 1 of the present invention. FIG. 4 is an explanatory view of a method of mounting the semiconductor device according to the first embodiment of the present invention. 1 and 2 show a method of manufacturing a semiconductor device in the order of steps.

【0013】図1(a)において、1は複数の半導体素
子が形成された半導体ウェハである。半導体ウェハ1の
上面には、外部接続用の電極であるバンプ2が形成され
ている。図1(b)に示すように、半導体ウェハ1の上
面のバンプ形成面(電極形成面)にはシート3が貼着さ
れ、シート3によって補強された状態で電極形成面の裏
面の薄化加工が行われる。薄化加工手段としては、砥石
を用いた研磨装置や、ドライエッチング装置によるエッ
チング、さらには薬液の化学反応を利用してエッチング
を行うものがある。これにより、半導体ウェハ1は約5
0μmの厚さまで薄化される。
In FIG. 1A, reference numeral 1 denotes a semiconductor wafer on which a plurality of semiconductor elements are formed. On the upper surface of the semiconductor wafer 1, bumps 2 as electrodes for external connection are formed. As shown in FIG. 1B, a sheet 3 is adhered to the bump forming surface (electrode forming surface) on the upper surface of the semiconductor wafer 1, and the back surface of the electrode forming surface is thinned while being reinforced by the sheet 3. Is performed. As the thinning means, there is a polishing apparatus using a grindstone, an etching using a dry etching apparatus, and an etching using a chemical reaction of a chemical solution. As a result, the semiconductor wafer 1 has about 5
It is thinned to a thickness of 0 μm.

【0014】次に、薄化された半導体ウェハ1の下面へ
のバンパ板4の貼着が行われる。図1(c)に示すよう
に、樹脂やセラミックあるいは金属などの材質を板状に
形成したバンパ板4の上面には接着材5が塗布される。
ここで、接着材5は低弾性係数の樹脂接着材であり、エ
ラストマーなど接合状態における弾性係数が小さく、小
さな外力で容易に伸縮する材質が用いられる。
Next, the bumper plate 4 is attached to the lower surface of the thinned semiconductor wafer 1. As shown in FIG. 1C, an adhesive 5 is applied to the upper surface of the bumper plate 4 formed of a material such as resin, ceramic, or metal in a plate shape.
Here, the adhesive 5 is a resin adhesive having a low elastic coefficient, and is made of a material such as an elastomer having a small elastic coefficient in a joined state and easily expanding and contracting with a small external force.

【0015】次にこの接着材5の塗布面に対して、薄化
された半導体ウェハ1を貼着する。このバンパ板4は、
各半導体素子毎に切り分けられて半導体装置を形成した
状態で、半導体装置のハンドリング用の保持部として機
能すると共に、半導体素子を外力や衝撃から保護する補
強部材としての役割をも有するものである。このためバ
ンパ板4は、半導体素子の曲げ剛性よりも大きな曲げ剛
性を有する充分な厚さとなっている。この後、図1
(d)に示すように、半導体ウェハ1貼着後のバンパ板
4の下面には、ダイシング工程における保持用のシート
6が貼着され、シート3が電極形成面から剥離される。
Next, the thinned semiconductor wafer 1 is attached to the surface to which the adhesive 5 is applied. This bumper plate 4
In a state where a semiconductor device is formed by being divided for each semiconductor element, the semiconductor device functions as a holding portion for handling the semiconductor device and also has a role as a reinforcing member for protecting the semiconductor element from external force and impact. For this reason, the bumper plate 4 has a sufficient thickness to have a bending rigidity larger than the bending rigidity of the semiconductor element. After this, FIG.
As shown in (d), the holding sheet 6 in the dicing step is adhered to the lower surface of the bumper plate 4 after the semiconductor wafer 1 is adhered, and the sheet 3 is separated from the electrode forming surface.

【0016】次いで、シート6によって保持されたバン
パ板4および半導体ウェハ1はダイシング工程に送られ
る。ここでは、図2(a)に示すようにバンパ板4と半
導体ウェハ1とを異なるダイシング幅で切り分ける2段
ダイシングが行われる。すなわち半導体ウェハ1はダイ
シング幅b1で切り分けられて個片の半導体素子1’に
分割され、バンパ板4はb1よりも狭いダイシング幅b
2で切り分けられて個片のバンパ部材4’となる。
Next, the bumper plate 4 and the semiconductor wafer 1 held by the sheet 6 are sent to a dicing process. Here, as shown in FIG. 2A, two-stage dicing is performed in which the bumper plate 4 and the semiconductor wafer 1 are cut at different dicing widths. That is, the semiconductor wafer 1 is cut at a dicing width b1 and divided into individual semiconductor elements 1 ', and the bumper plate 4 has a dicing width b smaller than b1.
2, the individual bumper members 4 'are obtained.

【0017】そして、接着材5によって半導体素子1’
と接着されたバンパ部材4’をシート6から剥離するこ
とにより、図2(b)に示すように個片の半導体装置7
が完成する。この半導体装置7は、外部接続用の電極で
あるバンプ2が形成された半導体素子1’と、この半導
体素子1’の電極形成面の裏面に接着材5により接合さ
れた補強部材としてのバンパ部材4’とを備えた構成と
なっており、バンパ部材4’のサイズB2は半導体素子
1’のサイズB1よりも大きく、その外周端は、半導体
素子1’の外周端よりも外側に突出している。バンパ部
材4’は半導体素子1’と接着材5によって接合された
構造となっている。接着材5は低弾性係数の樹脂接着材
であるので、半導体素子1’の変形を許容する状態で、
この半導体素子1’をバンパ部材4’に接合している。
Then, the semiconductor element 1 ′ is bonded by the adhesive 5.
By peeling the bumper member 4 ′ bonded to the sheet 6 from the sheet 6, as shown in FIG.
Is completed. The semiconductor device 7 includes a semiconductor element 1 ′ on which a bump 2 serving as an electrode for external connection is formed, and a bumper member as a reinforcing member bonded to the back surface of the electrode forming surface of the semiconductor element 1 ′ by an adhesive 5. 4 ', the size B2 of the bumper member 4' is larger than the size B1 of the semiconductor element 1 ', and the outer peripheral end of the bumper member 4' projects outward from the outer peripheral end of the semiconductor element 1 '. . The bumper member 4 ′ has a structure in which the semiconductor element 1 ′ and the adhesive 5 are joined. Since the adhesive 5 is a resin adhesive having a low modulus of elasticity, the semiconductor element 1 ′ is allowed to be deformed.
This semiconductor element 1 'is joined to a bumper member 4'.

【0018】図3に示すように、バンパ部材4’の上面
には、従来の樹脂封止型の電子部品の上面と同様に、識
別情報としての部品コード8が印字されており、コーナ
部には実装時の方向を特定する極性マーク9が形成され
ている。すなわち、バンパ部材4’の半導体素子1’と
の接合面の裏面は、識別情報の印加面となっている。こ
の後、個片の半導体装置7を上下反転してバンパ部材
4’を上面側にし、電子部品供給用のテープに収容する
テーピング処理を行う。これにより、半導体装置7は、
電子部品実装装置による実装が可能な状態となる。
As shown in FIG. 3, a component code 8 as identification information is printed on the upper surface of the bumper member 4 'similarly to the upper surface of the conventional resin-encapsulated electronic component. Is formed with a polarity mark 9 for specifying a mounting direction. That is, the back surface of the bonding surface of the bumper member 4 'with the semiconductor element 1' is a surface to which the identification information is applied. Thereafter, a taping process is performed in which the individual semiconductor devices 7 are turned upside down so that the bumper member 4 ′ is placed on the upper surface side and housed in a tape for supplying electronic components. As a result, the semiconductor device 7
The electronic component mounting apparatus is ready for mounting.

【0019】本発明者らは、半導体素子1’の代わり
に、厚さ50μmのシリコンの板を用いて半導体装置の
ダミーを製作し、高さ1mの所からの落下試験を行っ
た。その結果、シリコンの板には割れ等の損傷は全く発
生しなかった。これにより、本発明の半導体装置は、通
常の電子部品と同等に取り扱っても全く問題がないこと
が確認された。さらに、半導体素子1’に接着材5を介
してバンパ部材4’を取り付けただけの簡単な構造なの
で、従来の樹脂封止では取り扱いが困難な極薄の半導体
素子を使用することができる。
The present inventors manufactured a dummy of a semiconductor device using a silicon plate having a thickness of 50 μm in place of the semiconductor element 1 ′, and conducted a drop test from a height of 1 m. As a result, no damage such as cracks occurred in the silicon plate. As a result, it has been confirmed that the semiconductor device of the present invention has no problem even if it is handled in the same manner as a normal electronic component. Furthermore, since it has a simple structure in which the bumper member 4 'is simply attached to the semiconductor element 1' via the adhesive 5, an extremely thin semiconductor element which is difficult to handle with conventional resin sealing can be used.

【0020】この半導体装置7の実装について図4を参
照して説明する。図4(a)に示すように、半導体装置
7はバンパ部材4’の上面を実装ヘッド10によって吸
着して保持され、実装ヘッド10を移動させることによ
り、基板11の上方に位置する。そして半導体装置7の
バンプ2を基板11の電極12に位置合わせした状態
で、実装ヘッド10を下降させて半導体素子1’のバン
プ2を基板11の電極12に上に着地させる。
The mounting of the semiconductor device 7 will be described with reference to FIG. As shown in FIG. 4A, the upper surface of the bumper member 4 'is sucked and held by the mounting head 10, and the semiconductor device 7 is located above the substrate 11 by moving the mounting head 10. Then, with the bumps 2 of the semiconductor device 7 aligned with the electrodes 12 of the substrate 11, the mounting head 10 is lowered to land the bumps 2 of the semiconductor element 1 ′ on the electrodes 12 of the substrate 11.

【0021】その後基板11を加熱することにより、バ
ンプ2を電極12に半田接合する。すなわち、半導体装
置7を基板11へ搭載する際のハンドリングにおいて、
実装ヘッド10によって、保持部であるバンパ部材4’
を保持する。なおバンプ2の電極12との接合に、導電
性樹脂接着材による接合方法を用いてもよい。
After that, the bumps 2 are soldered to the electrodes 12 by heating the substrate 11. That is, in handling when the semiconductor device 7 is mounted on the substrate 11,
The mounting head 10 allows the bumper member 4 ′ as a holding unit to be held.
Hold. Note that the bumps 2 may be bonded to the electrodes 12 by a bonding method using a conductive resin adhesive.

【0022】この半導体装置7を基板11に実装して成
る実装構造は、半導体装置7の電極であるバンプ2をワ
ークである基板11の電極12に接合することにより半
導体装置7が基板11に固定される形態となっている。
図4(c)に示すように、実装後に基板11に何らかの
外力により、撓み変形が発生した場合には、半導体素子
1’は薄くて撓みやすくしかも接着材5は低弾性係数の
変形しやすい材質を用いていることから、基板11の撓
み変形に対して半導体素子1’と接着材5の接着層のみ
が追従して変形する。
The mounting structure in which the semiconductor device 7 is mounted on the substrate 11 has a structure in which the semiconductor device 7 is fixed to the substrate 11 by bonding the bumps 2 serving as the electrodes of the semiconductor device 7 to the electrodes 12 of the substrate 11 serving as the work. It is a form to be done.
As shown in FIG. 4 (c), when the substrate 11 undergoes bending deformation due to some external force after mounting, the semiconductor element 1 'is thin and easily bent, and the adhesive 5 has a low elastic coefficient and is easily deformed. Is used, only the adhesive layer of the semiconductor element 1 ′ and the adhesive 5 follows the bending deformation of the substrate 11 and deforms.

【0023】さらに本発明の半導体装置において100
μm以下の極薄の半導体素子を用いることにより、半導
体素子1’と基板11との熱膨張率の差に起因してバン
プ2に発生する応力を小さくできる。従来のバンプ付電
子部品(半導体装置)では、厚い半導体素子を使用して
いたので、バンプ2に発生する応力が過大となり断線す
る可能性があった。このため、バンプ付電子部品と基板
との間にアンダーフィル樹脂等の補強を必要としてい
た。半導体素子1’を極薄とすることにより、実装後に
アンダーフィル樹脂を充填するなどの補強処理を必要と
することなく接合部の応力が緩和され、単に半導体素子
1’とバンパ部材4’とを接着材5により接合するとい
う簡易な形態のパッケージ構造で、実装後の信頼性の確
保が実現される。
Further, in the semiconductor device of the present invention, 100
By using an ultra-thin semiconductor element of μm or less, the stress generated in the bump 2 due to the difference in the coefficient of thermal expansion between the semiconductor element 1 ′ and the substrate 11 can be reduced. In a conventional electronic component with a bump (semiconductor device), since a thick semiconductor element is used, the stress generated in the bump 2 becomes excessive, and there is a possibility of disconnection. For this reason, reinforcement such as an underfill resin is required between the electronic component with bumps and the substrate. By making the semiconductor element 1 'extremely thin, the stress at the joint is reduced without the need for reinforcement processing such as filling an underfill resin after mounting, and the semiconductor element 1' and the bumper member 4 'are simply separated. With a simple package structure of joining with the adhesive 5, reliability after mounting is ensured.

【0024】(実施の形態2)図5、図6は本発明の実
施の形態2の半導体装置の製造方法の工程説明図であ
る。なお、図5、図6は半導体装置の製造方法を工程順
に示している。
(Embodiment 2) FIGS. 5 and 6 are process explanatory views of a method for manufacturing a semiconductor device according to Embodiment 2 of the present invention. 5 and 6 show a method of manufacturing a semiconductor device in the order of steps.

【0025】図5(a)において、1は実施の形態1に
示す半導体ウェハと同様に、複数の半導体素子が形成さ
れた半導体ウェハであり、上面には外部接続用のバンプ
2が形成されている。半導体ウェハ1の下面にはシート
6が貼着され、図5(b)に示すようにシート6で保持
された状態で、半導体ウェハ1のダイシングが行われ、
各半導体素子1’の境界にはダイシング溝1aが形成さ
れる。次いでこの状態で各導体素子1’のバンプ形成面
には、薄化工程での補強用のシート3が貼着される。そ
してシート3によって補強された状態で、各半導体素子
1’のバンプ形成面の裏面の薄化が一括して行われる。
これにより、半導体素子1’は約50μmの厚さまで薄
化されるとともに、ダイシング溝1aによって個別に分
離される。
In FIG. 5A, reference numeral 1 denotes a semiconductor wafer on which a plurality of semiconductor elements are formed, similarly to the semiconductor wafer shown in the first embodiment, and bumps 2 for external connection are formed on the upper surface. I have. A sheet 6 is adhered to the lower surface of the semiconductor wafer 1, and the semiconductor wafer 1 is diced while being held by the sheet 6 as shown in FIG.
Dicing grooves 1a are formed at boundaries between the semiconductor elements 1 '. Next, in this state, a sheet 3 for reinforcement in the thinning step is adhered to the bump formation surface of each conductor element 1 '. Then, with the sheet 3 reinforced, the back surface of the bump forming surface of each semiconductor element 1 ′ is thinned at once.
As a result, the semiconductor elements 1 ′ are thinned to a thickness of about 50 μm and are individually separated by the dicing grooves 1a.

【0026】次に、図5(d)に示すように半導体素子
1’とバンパ板4との貼着が一括して行われる。すなわ
ち、実施の形態1に示すものと同様のバンパ板4の上面
に接着材5が塗布される。ここで、接着材5の材質は実
施の形態1に示すものと同様である。そしてこの接着材
5の塗布面に対して薄化された半導体素子1’を貼着す
る。
Next, as shown in FIG. 5D, the bonding of the semiconductor element 1 'and the bumper plate 4 is performed at one time. That is, the adhesive 5 is applied to the upper surface of the bumper plate 4 similar to that shown in the first embodiment. Here, the material of the adhesive 5 is the same as that shown in the first embodiment. Then, the thinned semiconductor element 1 ′ is adhered to the application surface of the adhesive 5.

【0027】次に図6(a)に示すように、半導体素子
貼着後のバンパ板4の下面には、ダイシング工程におけ
る保持用のシート6が貼着され、シート6によって保持
されたバンパ板4に対してダイシングが行われる。ここ
では半導体素子1’のバンプ形成面のシート3を除去し
た後、図6(b)に示すようにバンパ板4を半導体素子
1’のダイシング幅b1よりも狭いダイシング幅b2で
切り分け、個片のバンパ部材4’とする。そして、接着
材5によって半導体素子1’と接着されたバンパ部材
4’をシート6から1個づつ剥離することにより、図6
(c)に示すように実施の形態1に示すものと同様の個
片の半導体装置7が完成する。この半導体装置7は、実
施の形態1と同様にテーピング処理が行われる。
Next, as shown in FIG. 6A, a sheet 6 for holding in the dicing step is stuck on the lower surface of the bumper plate 4 after the semiconductor element is stuck, and the bumper plate held by the sheet 6 is held. 4 is diced. Here, after removing the sheet 3 on the bump forming surface of the semiconductor element 1 ′, the bumper plate 4 is cut at a dicing width b 2 smaller than the dicing width b 1 of the semiconductor element 1 ′ as shown in FIG. Bumper member 4 ′. Then, the bumper members 4 ′ adhered to the semiconductor element 1 ′ by the adhesive 5 are peeled off from the sheet 6 one by one, whereby FIG.
As shown in (c), a semiconductor device 7 of the same size as that of the first embodiment is completed. This semiconductor device 7 is subjected to a taping process as in the first embodiment.

【0028】(実施の形態3)図7、図8は本発明の実
施の形態3の半導体装置の製造方法の工程説明図、図9
は本発明の実施の形態3の半導体装置の実装方法の説明
図である。なお、図7、図8は半導体装置の製造方法を
工程順に示している。
(Embodiment 3) FIGS. 7 and 8 are process explanatory views of a method of manufacturing a semiconductor device according to Embodiment 3 of the present invention, and FIGS.
FIG. 9 is an explanatory diagram of a method for mounting a semiconductor device according to a third embodiment of the present invention. 7 and 8 show a method of manufacturing a semiconductor device in the order of steps.

【0029】図7(a)において、1は実施の形態1,
2と同様の半導体ウェハであり、上面に外部接続用のバ
ンプ2が形成されている。次に図7(b)に示すよう
に、半導体ウェハ1の上面の電極形成面にはシート3が
貼着され、シート3によって補強された状態で半導体素
子下面の薄化加工が行われる。これにより、半導体ウェ
ハ1は約50μmの厚さまで薄化される。
In FIG. 7A, reference numeral 1 denotes the first embodiment,
2 is a semiconductor wafer similar to that of FIG. 2, and has bumps 2 for external connection formed on the upper surface. Next, as shown in FIG. 7B, a sheet 3 is adhered to the electrode forming surface on the upper surface of the semiconductor wafer 1, and the lower surface of the semiconductor element is thinned while being reinforced by the sheet 3. Thereby, the semiconductor wafer 1 is thinned to a thickness of about 50 μm.

【0030】この後、半導体ウェハ1の下面には、ダイ
シング工程における保持用のシート6が貼着され、薄化
時の補強用のシート3が除去される。次いで、シート6
によって保持された半導体ウェハ1はダイシング工程に
送られ、ここで図7(c)に示すようにダイシング溝1
aが加工され、半導体ウェハ1は各半導体素子1’毎に
切り分けられる。そして切り分けられた半導体素子1’
は、シート6から剥離されて図8(a)に示すように個
片毎に取り出される。
Thereafter, a sheet 6 for holding in the dicing step is adhered to the lower surface of the semiconductor wafer 1, and the sheet 3 for reinforcement at the time of thinning is removed. Then, sheet 6
The semiconductor wafer 1 held by the semiconductor wafer 1 is sent to the dicing step, where the dicing groove 1 is formed as shown in FIG.
a is processed, and the semiconductor wafer 1 is cut for each semiconductor element 1 ′. And the separated semiconductor element 1 '
Is peeled off from the sheet 6 and taken out individually as shown in FIG.

【0031】次に、半導体素子1’のバンパケース14
への貼着が行われる。本実施の形態3で用いられる補強
部材は、図8(b)に示すように、周囲に突部14aが
設けられ半導体素子1’が接合される部分に凹部14b
が形成された形状のバンパケース14である。凹部14
b内には半導体素子1’の範囲に対応した部分に、実施
の形態に示すものと同様の材質の接着材5が塗布され
る。そして図8(c)に示すように、凹部14b内に半
導体素子1’が搭載され、接着材5によってバンパケー
ス14と半導体素子1’が接合される。これにより、半
導体装置15が完成する。ここで、半導体素子1’との
接着状態において、バンパケース14の突部14aの端
部は、半導体素子1’のバンプ2の下端から突出しない
ように寸法設定がなされている。
Next, the bumper case 14 of the semiconductor element 1 '
Is applied. As shown in FIG. 8B, the reinforcing member used in the third embodiment has a protrusion 14a around its periphery and a concave portion 14b at a portion where the semiconductor element 1 'is joined.
Are formed in the bumper case 14. Recess 14
In b, an adhesive 5 made of the same material as that shown in the embodiment is applied to a portion corresponding to the range of the semiconductor element 1 '. Then, as shown in FIG. 8C, the semiconductor element 1 ′ is mounted in the recess 14 b, and the bumper case 14 and the semiconductor element 1 ′ are joined by the adhesive 5. Thus, the semiconductor device 15 is completed. Here, in the bonded state with the semiconductor element 1 ′, the dimension of the end of the protrusion 14 a of the bumper case 14 is set so as not to protrude from the lower end of the bump 2 of the semiconductor element 1 ′.

【0032】このバンパケース14は、実施の形態1,
2と同様に、半導体装置15のハンドリング用の保持部
として機能すると共に、半導体素子1’を外力や衝撃か
ら保護する補強部材としての役割をも有するものであ
る。本実施の形態3では、半導体素子1’の側方をも保
護する形状となっていることから、半導体装置15の信
頼性が更に向上している。この後、図8(d)に示すよ
うに半導体装置15は上下反転され、同様にテーピング
処理される。これにより、電子部品実装装置による半導
体装置15の実装が可能な状態となる。
The bumper case 14 is used in the first and second embodiments.
Similarly to 2, it functions as a holding portion for handling the semiconductor device 15 and also has a role as a reinforcing member for protecting the semiconductor element 1 ′ from external force and impact. In the third embodiment, the semiconductor device 1 ′ has a shape that also protects the lateral sides, so that the reliability of the semiconductor device 15 is further improved. Thereafter, the semiconductor device 15 is turned upside down as shown in FIG. As a result, the semiconductor device 15 can be mounted by the electronic component mounting apparatus.

【0033】この半導体装置15の実装について図9を
参照して説明する。図9(a)に示すように、半導体装
置15はバンパケース14の上面を実装ヘッド10によ
って吸着して保持され、実装ヘッド10を移動させるこ
とにより、基板11の上方に位置する。本実施の形態3
では、基板11上面の電極12の周囲(バンパケース1
4の突部14aに対応する位置)に予め接着材16が塗
布されている。そして半導体装置15のバンプ2を基板
11の電極12に位置合わせした状態で、実装ヘッド1
0を下降させて半導体素子1’のバンプ2を基板11の
電極12に上に着地させる。
The mounting of the semiconductor device 15 will be described with reference to FIG. As shown in FIG. 9A, the upper surface of the bumper case 14 is sucked and held by the mounting head 10, and the semiconductor device 15 is located above the substrate 11 by moving the mounting head 10. Embodiment 3
Then, the periphery of the electrode 12 on the upper surface of the substrate 11 (bumper case 1)
The adhesive 16 is applied in advance to the position corresponding to the protrusions 14a of No. 4). Then, with the bumps 2 of the semiconductor device 15 aligned with the electrodes 12 of the substrate 11, the mounting head 1
0 is lowered so that the bumps 2 of the semiconductor element 1 ′ land on the electrodes 12 of the substrate 11.

【0034】これにより、バンパケース14の突部14
aが基板11上面の接着材16に接触する。この後基板
11を加熱することにより、図9(b)に示すようにバ
ンプ2を電極12に半田接合するとともに、バンパケー
ス14が接着材16により基板11に固着される。すな
わち、実施の形態3における実装動作も、半導体装置1
5のハンドリングにおいて保持部であるバンパケース1
4を実装ヘッド10によって保持する形態となってい
る。
Thus, the projection 14 of the bumper case 14
a contacts the adhesive 16 on the upper surface of the substrate 11. Thereafter, by heating the substrate 11, the bumps 2 are soldered to the electrodes 12 as shown in FIG. 9B, and the bumper case 14 is fixed to the substrate 11 by the adhesive 16. That is, the mounting operation in the third embodiment is also
Bumper case 1 which is a holding part in the handling of 5
4 is held by the mounting head 10.

【0035】この半導体装置15を基板11に実装して
成る実装構造は、半導体装置15の電極であるバンプ2
をワークである基板11の電極12に接合するととも
に、バンパケース14の周囲が基板11に接合されるこ
とにより、半導体装置15が基板11に固定される形態
となっている。この実装構造においても、半導体素子
1’の変形が許容される構造となっており、実施の形態
1,2に示す半導体素子1’と同様の効果を得る。
The mounting structure formed by mounting the semiconductor device 15 on the substrate 11 is the same as that of the bump 2 serving as an electrode of the semiconductor device 15.
Is bonded to the electrode 12 of the substrate 11 as a work, and the periphery of the bumper case 14 is bonded to the substrate 11, so that the semiconductor device 15 is fixed to the substrate 11. Also in this mounting structure, the semiconductor element 1 'is allowed to deform, and the same effects as those of the semiconductor element 1' shown in the first and second embodiments are obtained.

【0036】さらに、図9(b)に示すように、本実施
の形態3においては、実装後に半導体装置15の半導体
素子1’の部分は、上面及び周囲を完全に密閉された構
造となるため、基板11の電極12との接合部への水分
や異物の混入が防止され、実装後の信頼性を向上させる
ことができる。
Further, as shown in FIG. 9B, in the third embodiment, the semiconductor element 1 'of the semiconductor device 15 has a structure in which the upper surface and the periphery are completely sealed after mounting. In addition, it is possible to prevent moisture and foreign substances from being mixed into the joint portion between the substrate 11 and the electrode 12, thereby improving the reliability after mounting.

【0037】[0037]

【発明の効果】本発明によれば、半導体装置を半導体素
子の電極形成面の裏面に低弾性係数の樹脂接着材を介し
て補強部材を接合した構成とすることにより、薄化され
た半導体素子の取り扱いが容易で実装後の信頼性が高い
半導体装置を実現することができる。
According to the present invention, a semiconductor device having a thinned semiconductor device is constructed by joining a reinforcing member to a back surface of an electrode forming surface of a semiconductor device via a resin adhesive having a low elastic modulus. And a semiconductor device with high reliability after mounting can be realized.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態1の半導体装置の製造方法
の工程説明図
FIG. 1 is a process explanatory view of a method for manufacturing a semiconductor device according to a first embodiment of the present invention;

【図2】本発明の実施の形態1の半導体装置の製造方法
の工程説明図
FIG. 2 is a process explanatory view of the method for manufacturing the semiconductor device according to the first embodiment of the present invention;

【図3】本発明の実施の形態1の半導体装置の斜視図FIG. 3 is a perspective view of the semiconductor device according to the first embodiment of the present invention;

【図4】本発明の実施の形態1の半導体装置の実装方法
の説明図
FIG. 4 is a diagram illustrating a method for mounting the semiconductor device according to the first embodiment of the present invention;

【図5】本発明の実施の形態2の半導体装置の製造方法
の工程説明図
FIG. 5 is a process explanatory view of a method for manufacturing a semiconductor device according to a second embodiment of the present invention;

【図6】本発明の実施の形態2の半導体装置の製造方法
の工程説明図
FIG. 6 is a process explanatory view of the method for manufacturing the semiconductor device according to the second embodiment of the present invention;

【図7】本発明の実施の形態3の半導体装置の製造方法
の工程説明図
FIG. 7 is a process explanatory view of a method for manufacturing a semiconductor device according to a third embodiment of the present invention;

【図8】本発明の実施の形態3の半導体装置の製造方法
の工程説明図
FIG. 8 is a process explanatory view of the method for manufacturing the semiconductor device according to the third embodiment of the present invention;

【図9】本発明の実施の形態3の半導体装置の実装方法
の説明図
FIG. 9 is a diagram illustrating a method for mounting a semiconductor device according to a third embodiment of the present invention;

【符号の説明】[Explanation of symbols]

1 半導体ウェハ 1’ 半導体素子 2 バンプ 3 シート 4 バンパ板 4’ バンパ部材 5 接着材 6 シート 7、15 半導体装置 14 バンパケース DESCRIPTION OF SYMBOLS 1 Semiconductor wafer 1 'Semiconductor element 2 Bump 3 sheet 4 Bumper plate 4' Bumper member 5 Adhesive material 6 Sheet 7, 15 Semiconductor device 14 Bumper case

───────────────────────────────────────────────────── フロントページの続き (72)発明者 前田 憲 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Fターム(参考) 5F044 QQ00  ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Ken Maeda 1006 Kazuma Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. F-term (reference) 5F044 QQ00

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】外部接続用の電極が形成された電極形成面
を有する半導体素子と、前記電極形成面の裏面に低弾性
係数の樹脂接着材を介して接合された補強部材とを備え
たことを特徴とする半導体装置。
1. A semiconductor device having an electrode forming surface on which an electrode for external connection is formed, and a reinforcing member joined to a back surface of the electrode forming surface via a resin adhesive having a low elastic coefficient. A semiconductor device characterized by the above-mentioned.
【請求項2】前記補強部材の曲げ剛性は、半導体素子の
曲げ剛性よりも大きいことを特徴とする請求項1記載の
半導体装置。
2. The semiconductor device according to claim 1, wherein the bending rigidity of the reinforcing member is larger than the bending rigidity of the semiconductor element.
【請求項3】前記樹脂接着材は、半導体素子の変形を許
容する状態でこの半導体素子を補強部材に接合している
ことを特徴とする請求項1記載の半導体装置。
3. The semiconductor device according to claim 1, wherein the resin adhesive bonds the semiconductor element to a reinforcing member in a state where the semiconductor element is allowed to deform.
【請求項4】半導体素子の外部接続用の電極が形成され
た電極形成面の裏面に低弾性係数の樹脂接着材を介して
補強部材を接合して成る半導体装置を製造する半導体装
置の製造方法であって、複数の半導体素子が形成された
半導体ウェハの電極形成面の裏面を削る薄化工程と、薄
化工程後の前記半導体素子の裏面に低弾性係数の樹脂接
着材を介して補強部材を接合する接合工程とを含むこと
を特徴とする半導体装置の製造方法。
4. A semiconductor device manufacturing method for manufacturing a semiconductor device in which a reinforcing member is joined to a back surface of an electrode forming surface on which an electrode for external connection of a semiconductor element is formed via a resin adhesive having a low elastic modulus. A thinning step of shaving the back surface of the electrode forming surface of the semiconductor wafer on which a plurality of semiconductor elements are formed, and a reinforcing member on the back surface of the semiconductor element after the thinning step via a resin adhesive having a low elastic modulus. And a bonding step of bonding the semiconductor devices.
【請求項5】前記接合工程において、半導体ウェハ状態
の複数の半導体素子を一括して補強部材に接合すること
を特徴とする請求項4記載の半導体装置の製造方法。
5. The method according to claim 4, wherein in the bonding step, a plurality of semiconductor elements in a semiconductor wafer state are bonded together to a reinforcing member.
JP2000335492A 2000-10-20 2000-11-02 Semiconductor device and method of manufacturing semiconductor device Expired - Fee Related JP3580244B2 (en)

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JP2000335492A JP3580244B2 (en) 2000-11-02 2000-11-02 Semiconductor device and method of manufacturing semiconductor device
TW090125113A TW522531B (en) 2000-10-20 2001-10-11 Semiconductor device, method of manufacturing the device and mehtod of mounting the device
US09/977,220 US6797544B2 (en) 2000-10-20 2001-10-16 Semiconductor device, method of manufacturing the device and method of mounting the device
KR1020010064018A KR100762208B1 (en) 2000-10-20 2001-10-17 Semiconductor device and its manufacturing method and mounting method of semiconductor device
CNB01135819XA CN1221028C (en) 2000-10-20 2001-10-19 Semiconductor devices and their method of production, and mounting method thereof

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7071577B2 (en) 2002-10-25 2006-07-04 Matshushita Electric Industrial Co., Ltd. Semiconductor device and resin binder for assembling semiconductor device
US7446423B2 (en) 2002-04-17 2008-11-04 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for assembling the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7446423B2 (en) 2002-04-17 2008-11-04 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for assembling the same
US7071577B2 (en) 2002-10-25 2006-07-04 Matshushita Electric Industrial Co., Ltd. Semiconductor device and resin binder for assembling semiconductor device

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