JP2002217527A - Semiconductor device, its manufacturing method and method for disposing anisotropic conducting film - Google Patents

Semiconductor device, its manufacturing method and method for disposing anisotropic conducting film

Info

Publication number
JP2002217527A
JP2002217527A JP2001014161A JP2001014161A JP2002217527A JP 2002217527 A JP2002217527 A JP 2002217527A JP 2001014161 A JP2001014161 A JP 2001014161A JP 2001014161 A JP2001014161 A JP 2001014161A JP 2002217527 A JP2002217527 A JP 2002217527A
Authority
JP
Japan
Prior art keywords
substrate
anisotropic conductive
conductive film
semiconductor device
conducting film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001014161A
Other languages
Japanese (ja)
Inventor
Shiyunei Nobusada
俊英 信定
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP2001014161A priority Critical patent/JP2002217527A/en
Publication of JP2002217527A publication Critical patent/JP2002217527A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

PROBLEM TO BE SOLVED: To prevent peeling of an anisotropic conducting film which is to be generated, simultaneously with peeling of a protective film of the anisotropic conducting film, in flip-chip mounting using the anisotropic conducting film. SOLUTION: Bonding strength is increased by forming a pattern 4 for bonding in a belt type on a peripheral part in a region on which the anisotropic conducting film 3 is stuck. The same material as that of electrode patterns 2, which are wired in a region on which a bare IC is to be mounted, is used as material of the pattern 4, so that the height of the pattern 4 is made identical to that of the electrode patterns 2, contact area between a substrate 1 and the anisotropic conducting film 3 is enlarged, and bonding strength is increased.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、半導体装置および
その製造方法、および異方性導電膜の装着方法に関する
ものであり、特に、ベアーICをフリップチップ実装す
る半導体実装基板に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, a method of manufacturing the same, and a method of mounting an anisotropic conductive film, and more particularly to a semiconductor mounting substrate on which a bare IC is flip-chip mounted.

【0002】[0002]

【従来の技術】ベアーICをフリップチップ実装する工
法のひとつに、異方性導電膜を使ってベアーICを基板
に固定する方法がある。
2. Description of the Related Art One method of flip-chip mounting a bare IC is a method of fixing the bare IC to a substrate using an anisotropic conductive film.

【0003】図3は、従来の半導体装置の製造方法を説
明するための図であり、ベースとなる基板1の上に電極
パターン2が形成されている半導体装置の平面図であ
る。この基板1を用いたフリップチップ実装の工程を図
4に示す。
FIG. 3 is a view for explaining a conventional method of manufacturing a semiconductor device, and is a plan view of a semiconductor device in which an electrode pattern 2 is formed on a substrate 1 serving as a base. FIG. 4 shows a flip-chip mounting process using the substrate 1.

【0004】まず、図4(a)に示すように、保護フィル
ム5上に密着形成されている異方性導電膜3を基板1に
装着し、圧着ヘッド6により所定の温度と圧力を全面に
加えると、異方性導電膜3は粘着性を持っているため
に、基板1と異方性導電膜3が密着される。
[0004] First, as shown in FIG. 4 (a), an anisotropic conductive film 3 formed in close contact with a protective film 5 is mounted on a substrate 1, and a predetermined temperature and pressure are applied to the entire surface by a pressure bonding head 6. In addition, since the anisotropic conductive film 3 has adhesiveness, the substrate 1 and the anisotropic conductive film 3 are adhered to each other.

【0005】次に、図4(b)に示すように、表面の保護
フィルム5を周辺部分から剥離すると異方性導電膜3が
基板1に残される。
[0005] Next, as shown in FIG. 4 (b), when the protective film 5 on the surface is peeled off from the peripheral portion, the anisotropic conductive film 3 is left on the substrate 1.

【0006】次に、図4(c)に示すように、バンプ8が
あらかじめ形成されているベアーIC7を位置決め装置
で基板1に装着する。異方性導電膜3の粘着性によりベ
アーIC7は位置決めされた状態で異方性導電膜3上に
密着する。このときはバンプ8と電極パターン2は異方
性導電膜3を介した状態となる。
Next, as shown in FIG. 4C, a bare IC 7 on which bumps 8 are formed in advance is mounted on the substrate 1 by a positioning device. Due to the adhesiveness of the anisotropic conductive film 3, the bare IC 7 comes into close contact with the anisotropic conductive film 3 in a positioned state. At this time, the bump 8 and the electrode pattern 2 are in a state via the anisotropic conductive film 3.

【0007】その後、図4(d)に示すように、ベアーI
C7に熱を加えながら基板1側に加圧することにより、
基板1上の電極パターン2とベアーIC7のバンプ8と
が接近し最終的には両者が接続状態になる。同時に異方
性導電膜3が硬化することにより電極パターン2とバン
プ8が電気的に接続されたままの状態で機械的強度が保
持される。
[0007] Thereafter, as shown in FIG.
By applying pressure to the substrate 1 while applying heat to C7,
The electrode pattern 2 on the substrate 1 and the bump 8 of the bare IC 7 come close to each other, and finally the two are connected. At the same time, the anisotropic conductive film 3 is cured, so that the mechanical strength is maintained while the electrode pattern 2 and the bump 8 remain electrically connected.

【0008】[0008]

【発明が解決しようとする課題】しかしながら、基板1
は電極パターン2の存在する部分と存在しない部分とで
は高さが異なるために、異方性導電膜3を基板1に接着
する際に全面にわたって均一な圧力では接着されない。
基板1上に形成されている電極パターン2は電極材料が
ある厚みを持っているために電極パターン2のないとこ
ろに比べてある高さを持つことになる。図4(b)に示
した仮圧着工程で基板1に対して平行度を持った圧着ヘ
ッド6で加圧すると異方性導電膜3は基板1に密着する
が、電極パターン2のある領域では高さが高いために局
部的に強い圧力が加わり接着強度が強くなる。逆に、そ
の他の領域では電極パターン2の存在する領域に比べて
接着強度が弱くなる。保護フィルム5の周辺部分は電極
パターン2がないために接着強度が弱く、保護フィルム
5を周辺部分から剥離する際に異方性導電膜3が同時に
周辺から剥がれてしまうという問題が生じる。異方性導
電膜3の剥離がベアーIC7の装着される電極パターン
2の領域に至ると接続不良が発生し歩留の低下を招く。
However, the substrate 1
Since the height is different between the portion where the electrode pattern 2 exists and the portion where the electrode pattern 2 does not exist, when the anisotropic conductive film 3 is bonded to the substrate 1, it is not bonded with a uniform pressure over the entire surface.
The electrode pattern 2 formed on the substrate 1 has a certain height as compared with the area without the electrode pattern 2 because the electrode material has a certain thickness. When pressure is applied to the substrate 1 by a pressure bonding head 6 having a parallelism to the substrate 1 in the temporary pressure bonding step shown in FIG. Since the height is high, a strong pressure is locally applied to increase the bonding strength. Conversely, the adhesive strength is weaker in other areas than in the area where the electrode pattern 2 exists. Since the peripheral portion of the protective film 5 does not have the electrode pattern 2, the adhesive strength is weak, and there is a problem that the anisotropic conductive film 3 is simultaneously peeled off from the periphery when the protective film 5 is peeled off from the peripheral portion. When the peeling of the anisotropic conductive film 3 reaches the region of the electrode pattern 2 on which the bare IC 7 is mounted, a connection failure occurs and the yield is reduced.

【0009】本発明は、保護フィルム5を剥離する際に
も異方性導電膜3が剥がれてしまわない半導体実装基板
を提供することを目的とする。
An object of the present invention is to provide a semiconductor mounting substrate in which the anisotropic conductive film 3 does not peel off even when the protective film 5 is peeled off.

【0010】[0010]

【課題を解決するための手段】本発明の半導体装置は、
基板と、前記基板上に形成された電極と、前記基板上に
形成された壇部と、前記基板上に形成された異方性導電
膜と、前記異方性導電膜上に形成された半導体素子とを
有し、前記壇部は、前記異方性導電膜の周縁部近傍に形
成されているものである。本発明により、異方性導電膜
と壇部との接着強度が強くなる。
According to the present invention, there is provided a semiconductor device comprising:
A substrate, an electrode formed on the substrate, a platform formed on the substrate, an anisotropic conductive film formed on the substrate, and a semiconductor formed on the anisotropic conductive film An element, wherein the platform is formed near the periphery of the anisotropic conductive film. According to the present invention, the adhesive strength between the anisotropic conductive film and the platform is increased.

【0011】本発明の他の半導体装置は、異方性導電膜
を介してベアーICをフリップチップ実装する基板にお
いて、バンプと接続される電極パターンとは別に前記異
方性導電膜を接着するための接着用パターンが前記電極
パターンの周囲を囲んで形成されており、前記電極パタ
ーンと前記接着用パターンの高さが同じ高さであること
を特徴とする。このような構成により異方性導電膜の周
辺部分は接着用ダミーパターンに接着するため、保護シ
ートを剥離する際に剥がれることはない。
According to another aspect of the present invention, there is provided a semiconductor device, on which a bare IC is flip-chip mounted via an anisotropic conductive film, for bonding the anisotropic conductive film separately from an electrode pattern connected to a bump. Is formed so as to surround the periphery of the electrode pattern, and the electrode pattern and the bonding pattern have the same height. With such a configuration, the peripheral portion of the anisotropic conductive film is bonded to the bonding dummy pattern, and thus does not peel off when the protective sheet is peeled off.

【0012】また本発明は、接着用パターンと電極パタ
ーンが同じ工程で形成されていること特徴とする。この
ようにして接着用パターンを形成することにより新たな
工程を追加することなく接着用パターンと電極パターン
を同じ高さで形成することができる。
Further, the present invention is characterized in that the bonding pattern and the electrode pattern are formed in the same step. By forming the bonding pattern in this way, the bonding pattern and the electrode pattern can be formed at the same height without adding a new process.

【0013】[0013]

【発明の実施形態】以下、本発明の実施形態について、
図面を参照しながら詳細に説明する。
Hereinafter, embodiments of the present invention will be described.
This will be described in detail with reference to the drawings.

【0014】図1は、本発明の実施の形態における半導
体装置に用いるための基板1を示す平面図である。図1
において、基板1上には、複数の電極パターン2が形成
され、複数の電極パターン2を取り囲むように壇部であ
る接着用パターン4が形成されている。電極パターン2
と接着用パターン4は同じ高さになるように、1回のパ
ターンニングにより同時に形成されている。
FIG. 1 is a plan view showing a substrate 1 used for a semiconductor device according to an embodiment of the present invention. Figure 1
In FIG. 1, a plurality of electrode patterns 2 are formed on a substrate 1, and a bonding pattern 4 as a platform is formed so as to surround the plurality of electrode patterns 2. Electrode pattern 2
And the bonding pattern 4 are simultaneously formed by one patterning so as to have the same height.

【0015】図2は、このような電極パターン2と接着
用パターン4とを有する基板1を用いたフリップチップ
実装による半導体装置の製造方法を示す工程断面図であ
る。
FIG. 2 is a process sectional view showing a method of manufacturing a semiconductor device by flip-chip mounting using the substrate 1 having such an electrode pattern 2 and the bonding pattern 4.

【0016】まず、図2(a)に示すように、保護フィル
ム5上に密着形成されている異方性導電膜3を基板1に
装着し、圧着ヘッド6により所定の温度と圧力を全面に
加えると、異方性導電膜3は粘着性を持っているため
に、基板1と異方性導電膜3が密着される。
First, as shown in FIG. 2A, an anisotropic conductive film 3 formed in close contact with a protective film 5 is mounted on a substrate 1, and a predetermined temperature and pressure are applied to the entire surface by a pressure bonding head 6. In addition, since the anisotropic conductive film 3 has adhesiveness, the substrate 1 and the anisotropic conductive film 3 are adhered to each other.

【0017】次に、図2(b)に示すように、表面の保護
フィルム5を周辺部分から剥離すると異方性導電膜3が
基板1に残される。
Next, as shown in FIG. 2B, when the protective film 5 on the surface is peeled off from the peripheral portion, the anisotropic conductive film 3 is left on the substrate 1.

【0018】次に、図2(c)に示すように、バンプ8が
あらかじめ形成されているベアーIC7を位置決め装置
で基板1に装着する。異方性導電膜3の粘着性によりベ
アーIC7は位置決めされた状態で異方性導電膜3上に
密着する。このときはバンプ8と電極パターン2は異方
性導電膜3を介した状態となる。
Next, as shown in FIG. 2C, a bare IC 7 on which bumps 8 are formed in advance is mounted on the substrate 1 by a positioning device. Due to the adhesiveness of the anisotropic conductive film 3, the bare IC 7 comes into close contact with the anisotropic conductive film 3 in a positioned state. At this time, the bump 8 and the electrode pattern 2 are in a state via the anisotropic conductive film 3.

【0019】その後、図2(d)に示すように、ベアーI
C7に熱を加えながら基板1側に加圧することにより、
基板1上の電極パターン2とベアーIC7のバンプ8と
が接近し最終的には両者が接続状態になる。同時に異方
性導電膜3が硬化することにより電極パターン2とバン
プ8が電気的に接続されたままの状態で機械的強度が保
持される。最後に、ベアーIC7ごとに基板1を切り出
すことにより半導体装置が完成する。
Thereafter, as shown in FIG.
By applying pressure to the substrate 1 while applying heat to C7,
The electrode pattern 2 on the substrate 1 and the bump 8 of the bare IC 7 come close to each other, and finally the two are connected. At the same time, the anisotropic conductive film 3 is cured, so that the mechanical strength is maintained while the electrode pattern 2 and the bump 8 remain electrically connected. Finally, the semiconductor device is completed by cutting out the substrate 1 for each bear IC 7.

【0020】本発明の実施の形態における半導体装置で
は、異方性導電膜3の周辺部分に対応して接着用パター
ン4が設けられているので、圧着ヘッド6を基板1側に
加圧すると、保護フィルム5の周辺部と接着用パターン
4との間に挟まれた異方性導電膜3が強く押さえられ
る。そのため、接着用パターン4が形成された領域は異
方性導電膜3との接着強度がその他の領域に比べて強く
なる。したがって、図2(b)に示した保護フィルム5
を周辺部分から剥離する工程において問題となっていた
接着力の不足で発生する異方性導電膜3の周辺部分の剥
離を防止できる。
In the semiconductor device according to the embodiment of the present invention, since the bonding pattern 4 is provided corresponding to the peripheral portion of the anisotropic conductive film 3, when the pressure bonding head 6 is pressed against the substrate 1, The anisotropic conductive film 3 sandwiched between the peripheral portion of the protective film 5 and the bonding pattern 4 is strongly suppressed. Therefore, the region where the bonding pattern 4 is formed has a higher bonding strength with the anisotropic conductive film 3 than other regions. Therefore, the protective film 5 shown in FIG.
Can be prevented from peeling off the peripheral portion of the anisotropic conductive film 3 which occurs due to insufficient adhesive force, which has been a problem in the step of peeling off from the peripheral portion.

【0021】なお、ここで説明した壇部である接着用パ
ターン4は、電極パターン2と同一の工程で形成されて
いるので、従来の半導体装置の製造工程と比較しても、
工程数を増やす必要がない。
Since the bonding pattern 4, which is the platform described here, is formed in the same process as the electrode pattern 2, it can be compared with the conventional semiconductor device manufacturing process.
There is no need to increase the number of processes.

【0022】[0022]

【発明の効果】以上説明したように、本発明の半導体装
置によれば、保護フィルムを剥離する際に異方性導電膜
の周辺部分が剥がれることなく、これが原因で発生する
接続不良を低減することができる。
As described above, according to the semiconductor device of the present invention, the peripheral portion of the anisotropic conductive film does not peel off when the protective film is peeled off, thereby reducing the connection failure caused by this. be able to.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の実施の形態における半導体装置に用い
る基板の平面図
FIG. 1 is a plan view of a substrate used for a semiconductor device according to an embodiment of the present invention.

【図2】本発明の実施の形態における半導体装置の製造
方法を示す工程断面図
FIG. 2 is a process sectional view illustrating the method for manufacturing the semiconductor device in the embodiment of the present invention.

【図3】従来の半導体装置に用いる基板の平面図FIG. 3 is a plan view of a substrate used in a conventional semiconductor device.

【図4】従来の半導体装置の製造方法を示す工程断面図FIG. 4 is a process sectional view showing a conventional method for manufacturing a semiconductor device.

【符号の説明】[Explanation of symbols]

1 基板 2 電極パターン 3 異方性導電膜 4 接着用パターン 5 保護フィルム 6 圧着ヘッド 7 ベアーIC 8 バンプ DESCRIPTION OF SYMBOLS 1 Substrate 2 Electrode pattern 3 Anisotropic conductive film 4 Adhesion pattern 5 Protective film 6 Pressure bonding head 7 Bear IC 8 Bump

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】 基板と、前記基板上に形成された電極
と、前記基板上に形成された壇部と、前記基板上に形成
された異方性導電膜と、前記異方性導電膜上に形成され
た半導体素子とを有し、前記壇部は、前記異方性導電膜
の周縁部近傍に形成されていることを特徴とする半導体
装置。
A substrate, an electrode formed on the substrate, a platform formed on the substrate, an anisotropic conductive film formed on the substrate, and an anisotropic conductive film formed on the substrate. A semiconductor element formed in the semiconductor device, wherein the platform is formed near the periphery of the anisotropic conductive film.
【請求項2】 前記壇部が、前記電極と同一の材料で構
成され、前記電極と同一の厚さを有することを特徴とす
る請求項1記載の半導体装置。
2. The semiconductor device according to claim 1, wherein the platform is made of the same material as the electrode and has the same thickness as the electrode.
【請求項3】 基板上に電極および壇部を形成する工程
と、保護膜を有する異方性導電膜を前記基板に貼り合わ
せる工程と、前記保護膜を除去する工程と、半導体素子
を、前記異方性導電膜を介して前記基板上にフリップチ
ップ実装する工程とを有することを特徴とする半導体装
置の製造方法。
A step of forming an electrode and a step on the substrate; a step of bonding an anisotropic conductive film having a protective film to the substrate; a step of removing the protective film; Flip-chip mounting on the substrate via an anisotropic conductive film.
【請求項4】 前記壇部を、前記電極と同一の材料で構
成し、前記電極および前記壇部を同一工程で形成するこ
とを特徴とする請求項3記載の半導体装置の製造方法。
4. The method of manufacturing a semiconductor device according to claim 3, wherein the platform is made of the same material as the electrode, and the electrode and the platform are formed in the same step.
【請求項5】 基板上に電極および壇部を形成する工程
と、保護膜を有する異方性導電膜を前記基板に貼り合わ
せる工程と、前記保護膜を除去する工程とを有すること
を特徴とする異方性導電膜の装着方法。
5. A method comprising: forming an electrode and a step on a substrate; bonding an anisotropic conductive film having a protective film to the substrate; and removing the protective film. Mounting method of the anisotropic conductive film.
JP2001014161A 2001-01-23 2001-01-23 Semiconductor device, its manufacturing method and method for disposing anisotropic conducting film Pending JP2002217527A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2001014161A JP2002217527A (en) 2001-01-23 2001-01-23 Semiconductor device, its manufacturing method and method for disposing anisotropic conducting film

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001014161A JP2002217527A (en) 2001-01-23 2001-01-23 Semiconductor device, its manufacturing method and method for disposing anisotropic conducting film

Publications (1)

Publication Number Publication Date
JP2002217527A true JP2002217527A (en) 2002-08-02

Family

ID=18880896

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001014161A Pending JP2002217527A (en) 2001-01-23 2001-01-23 Semiconductor device, its manufacturing method and method for disposing anisotropic conducting film

Country Status (1)

Country Link
JP (1) JP2002217527A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100643169B1 (en) 2005-04-28 2006-11-10 (주)유비엠디 Film substrate for semiconductor package and semiconductor package having the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100643169B1 (en) 2005-04-28 2006-11-10 (주)유비엠디 Film substrate for semiconductor package and semiconductor package having the same

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