JP3694803B2 - Method for forming titanium film of semiconductor device - Google Patents

Method for forming titanium film of semiconductor device Download PDF

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JP3694803B2
JP3694803B2 JP17934199A JP17934199A JP3694803B2 JP 3694803 B2 JP3694803 B2 JP 3694803B2 JP 17934199 A JP17934199 A JP 17934199A JP 17934199 A JP17934199 A JP 17934199A JP 3694803 B2 JP3694803 B2 JP 3694803B2
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film
semiconductor device
titanium film
titanium
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JP2000031094A (en
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憲 度 金
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SK Hynix Inc
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Hynix Semiconductor Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
    • H01L21/76846—Layer combinations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/2855—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by physical means, e.g. sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28568—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising transition metals

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physical Vapour Deposition (AREA)

Description

【０００１】
【発明の属する技術分野】
本発明は半導体技術に関し、特に半導体装置のチタニウム(Ti)膜の形成方法に関するものである。
【０００２】
【従来の技術】
半導体素子が益々高集積化されていくにことよって、金属コンタクトホールの大きさも徐々に縮小化する傾向にあり、これに伴い金属配線形成が益々難しくなっている。金属配線工程時に一般的に適用される拡散防止膜(diffusion barrier)として主として物理蒸着(PVD)法によるTi/TiN膜を使用してきた。しかし、広く知られているように、物理蒸着法はその蒸着原理により優れた段差被覆性(step coverage)を得るのが根本的に難しい。
【０００３】
すなわち、物理蒸着(PVD)法を使用してTi/TiN膜を蒸着する場合、段差比(aspect ratio)が２以上の高段差コンタクトホールではコンタクトホールの下部と側壁での被覆性が劣悪になる。
【０００４】
このような物理蒸着法の劣悪な被覆性を改善するためにコリメーター(collimator)またはイオン化(ionized)方式の物理蒸着(PVD)法などが研究されているが、未だ充分な被覆性を確保しにくいだけでなく、このような研究の大部分がTiN膜に関し、Ti膜に関する研究はほとんどなされない実情である。
【０００５】
実質的に、TiN膜はバリアー(barrier)の役割だけを正しく遂行すれば素子の特性には大きい影響を及ぼさないが、Ti膜の場合、シリコン基板と接触し、また後続工程時に半導体基板との反応により素子の特性に非常に大きい影響を及ぼすようになる。
【０００６】
詳述した工程等の問題点を解決するために、高周波(RF)電源を印加してスパッタリングチャンバ(sputtering chamber)内に高密度プラズマを形成し、ウエハーにバイアス電源を印加してスパッタされた原子らがウエハーに垂直方向に入射されるようにしてコンタクトホール(contact hole)の下部の被覆性を増大させる工程が提案された。
【０００７】
しかし、この場合、被覆性は増加する反面、高密度のプラズマと半導体基板に印加したバイアスによりシリコン基板の損傷を誘発して素子の特性を劣化させるようになるという問題があった。
【０００８】
【発明が解決しようとする課題】
本発明はスパッタ法によるチタニウム膜の蒸着時に基板の損傷なしに被覆性を向上させることができる半導体装置のチタニウム膜の形成方法を提供するのにその目的がある。
【０００９】
【課題を解決するための手段】
上記目的を達成するために本発明から提供されている特徴的な半導体装置のチタニウム膜形成方法は、スパッタ法を使用した半導体装置のチタニウム膜形成方法において、コンタクトホールが形成されたウエハーの上部に、1010/cm3を越えない密度のプラズマを利用してスパッタ法により第１チタニウム膜を蒸着する段階と、上記第１チタニウム膜上に、バイアスを印加した状態で少なくとも1011/cm3以上の密度のプラズマを使用して第２チタニウム膜を蒸着する段階とを含んでなる。
【００１０】
本発明はスパッタ法によるTi膜の蒸着時に高周波電源及びバイアス電源の調節により基板の損傷なしに優れた被覆性を確保することができるようにする。
【００１１】
すなわち、Ti膜の蒸着初期には低い密度のプラズマを利用して非常に低い工程圧力下で一定厚さを蒸着し、残り厚さのTi膜は中間密度以上のプラズマを利用してバイアスを印加して蒸着する技術である。
【００１２】
【発明の実施の形態】
以下、本発明の容易な実施のために本発明の望ましい実施例を説明する。
【００１３】
添付された図１〜図４は本発明の一実施例に係る半導体装置の金属配線形成工程を示す断面図であり、以下これを参照してその工程を詳細に説明する。
【００１４】
まず、図１に図示された通り所定の下部層工程を終えたシリコン基板10の上部に層間絶縁膜11を蒸着し、これを選択的にエッチングして金属コンタクトホールを形成してから高真空に維持されたスパッタリング装置内で全体構造の上部に第１Ti膜12を蒸着する。
【００１５】
この時、第１Ti膜12は、450〜650℃の温度下で、1010/cm3以下の低いプラズマ密度と2.0mTorr以下の低い工程圧力を使用して蒸着し、その厚さは予定されたTi膜の厚さの1/2を越えないようにする。
【００１６】
このように蒸着された第１Ti膜12は、図示された通り、コンタクトホール側壁部分の被覆は高密度プラズマを使用する時より優れており、コンタクトホール下部では高密度プラズマを使用する時より劣るが、コンタクトホール下部に露出していたシリコン基板10の損傷を防止できる。
【００１７】
次いで、図２に示すように、第１Ti膜12上に第2Ti膜13を蒸着する。この時、第２Ti膜13は、４５０〜６５０℃の温度下で、スパッタリングチャンバのプラズマ密度を1011/cm3以上に増加させ、工程圧力を15mTorr以上に増加させた状態で予定された厚さとなるまで蒸着し、バイアスを印加してスパッタリングされたTi粒子に直進性を与えることによってコンタクトホール下部の被覆性を良化させる。
【００１８】
続けて、図３に示すように、チャンバの移動なしに第２Ti膜13上にTiN膜14を蒸着する。TiN膜14の蒸着は第２Ti膜13の蒸着時とほとんど同じ雰囲気で蒸着する。
【００１９】
次に、図４に示すように、TiN膜14上にタングステン膜15を蒸着してコンタクトホールを埋める。例えば、前述した一実施形態では金属配線工程を一例として説明したが、本発明は金属ビットライン工程にも適用できる。
【００２０】
以上で説明した本発明は前述した実施例及び添付された図面により限定されることがなく、本発明の技術的思想を逸脱しない範囲内で種々の置換、変形及び変更が可能だということは、本発明が属する技術分野における通常の知識を有する者にとって明白なことである。
【００２１】
【発明の効果】
以上のように本発明によれば、Ti膜の被覆性を改善して金属配線形成工程を安定化することによって半導体装置の信頼度及び歩留まりを向上させる効果がある。
【図面の簡単な説明】
【図１】本発明の一実施例に係る半導体装置の金属配線形成工程を示す断面図である。
【図２】本発明の一実施例に係る半導体装置の金属配線形成工程を示す断面図である。
【図３】本発明の一実施例に係る半導体装置の金属配線形成工程を示す断面図である。
【図４】本発明の一実施例に係る半導体装置の金属配線形成工程を示す断面図である。
【符号の説明】
10 シリコン基板
11 層間絶縁膜
12 第１チタニウム膜
13 第２チタニウム膜
14 TiN膜
15 タングステン膜[0001]
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor technology, and more particularly to a method for forming a titanium (Ti) film of a semiconductor device.
[0002]
[Prior art]
As semiconductor elements become more highly integrated, the size of metal contact holes tends to be gradually reduced, and accordingly, formation of metal wiring becomes more difficult. Ti / TiN films mainly by physical vapor deposition (PVD) have been used as diffusion barriers generally applied during metal wiring processes. However, as is widely known, physical vapor deposition is fundamentally difficult to obtain excellent step coverage due to its vapor deposition principle.
[0003]
That is, when depositing a Ti / TiN film using the physical vapor deposition (PVD) method, the coverage on the lower and side walls of the contact hole is poor in a high step contact hole with an aspect ratio of 2 or more. .
[0004]
Collimator or ionized physical vapor deposition (PVD) methods have been studied to improve the poor coverage of physical vapor deposition, but sufficient coverage is still ensured. Not only is it difficult, but most of such research is related to TiN films, and research on Ti films is rarely done.
[0005]
In effect, the TiN film does not have a significant effect on the device characteristics if it only performs the role of a barrier, but in the case of the Ti film, it contacts the silicon substrate. The reaction greatly affects the characteristics of the device.
[0006]
In order to solve the problems such as the process described in detail, a high frequency (RF) power is applied to form a high density plasma in the sputtering chamber, and a bias power is applied to the wafer to sputter the atoms. Have proposed a process for increasing the coverage of the lower part of the contact hole so that they are vertically incident on the wafer.
[0007]
However, in this case, the coverage is increased, but there is a problem that the characteristics of the device are deteriorated by inducing damage to the silicon substrate by the high-density plasma and the bias applied to the semiconductor substrate.
[0008]
[Problems to be solved by the invention]
An object of the present invention is to provide a method for forming a titanium film of a semiconductor device that can improve the coverage without damaging the substrate when depositing the titanium film by sputtering.
[0009]
[Means for Solving the Problems]
Titanium film forming method of the characteristic semiconductor device that is provided by the present invention in order to attain the above objects, the titanium film formation method of a semiconductor device using a sputtering method, the upper portion of the wafer where the contact hole is formed to 10 10 / the steps of cm 3 by using the density of the plasma which does not exceed depositing a first titanium layer by sputtering, on said first titanium layer, at least 10 11 while applying a bus ear scan / depositing a second titanium film using a plasma having a density of cm 3 or more.
[0010]
The present invention makes it possible to ensure excellent coverage without damaging the substrate by adjusting the high-frequency power source and the bias power source when depositing the Ti film by sputtering.
[0011]
That is, at the initial stage of Ti film deposition, a low-density plasma is used to deposit a constant thickness under a very low process pressure, and the remaining thickness of the Ti film is biased using a medium-density plasma or higher. This is a technique for vapor deposition.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described for easy implementation of the present invention.
[0013]
1 to 4 attached hereto are sectional views showing a metal wiring forming process of a semiconductor device according to one embodiment of the present invention, and the process will be described in detail below with reference to this.
[0014]
First, as shown in FIG. 1, an interlayer insulating film 11 is deposited on an upper part of a silicon substrate 10 after a predetermined lower layer process is completed, and this is selectively etched to form a metal contact hole, and then a high vacuum is applied. A first Ti film 12 is deposited on top of the entire structure in the maintained sputtering apparatus.
[0015]
At this time, the first Ti film 12 was deposited at a temperature of 450 to 650 ° C. using a low plasma density of 10 10 / cm 3 or less and a low process pressure of 2.0 mTorr or less. Do not exceed 1/2 of the thickness of the Ti film.
[0016]
As shown in the figure, the first Ti film 12 deposited in this way is better in covering the contact hole side wall than when using high-density plasma, but inferior to using high-density plasma below the contact hole. The damage to the silicon substrate 10 exposed under the contact hole can be prevented.
[0017]
Next, as shown in FIG. 2, a second Ti film 13 is deposited on the first Ti film 12. At this time, the second Ti film 13 has a predetermined thickness with a plasma pressure in the sputtering chamber increased to 10 11 / cm 3 or more at a temperature of 450 to 650 ° C. and a process pressure increased to 15 mTorr or more. Vapor deposition is performed and a bias is applied to impart straightness to the sputtered Ti particles, thereby improving the coverage of the lower part of the contact hole.
[0018]
Subsequently, as shown in FIG. 3, a TiN film 14 is deposited on the second Ti film 13 without moving the chamber. The TiN film 14 is deposited in almost the same atmosphere as the second Ti film 13 is deposited.
[0019]
Next, as shown in FIG. 4, a tungsten film 15 is deposited on the TiN film 14 to fill the contact holes. For example, in the above-described embodiment, the metal wiring process has been described as an example, but the present invention can also be applied to a metal bit line process.
[0020]
The present invention described above is not limited by the above-described embodiments and attached drawings, and various substitutions, modifications, and changes can be made without departing from the technical idea of the present invention. It will be clear to those skilled in the art to which the present invention belongs.
[0021]
【The invention's effect】
As described above, according to the present invention, there is an effect of improving the reliability and yield of the semiconductor device by improving the coverage of the Ti film and stabilizing the metal wiring forming process.
[Brief description of the drawings]
FIG. 1 is a cross-sectional view showing a metal wiring forming process of a semiconductor device according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view showing a metal wiring forming process of a semiconductor device according to an embodiment of the present invention.
FIG. 3 is a cross-sectional view showing a metal wiring forming process of a semiconductor device according to an embodiment of the present invention.
FIG. 4 is a cross-sectional view showing a metal wiring forming process of a semiconductor device according to an embodiment of the present invention.
[Explanation of symbols]
10 Silicon substrate
11 Interlayer insulation film
12 First titanium film
13 Second titanium film
14 TiN film
15 Tungsten film

Claims (6)

コンタクトホールを有する半導体装置において、
コンタクトホールが形成されたウエハーの上部に、1010/cm3を越えない密度のプラズマを利用してスパッタ法により第1チタニウム膜を蒸着する段階と、
上記第１チタニウム膜上に、バイアスを印加した状態で少なくとも1011/cm3以上の密度のプラズマを使用して第２チタニウム膜を蒸着する段階とを含んでなることを特徴とする半導体装置のチタニウム膜の形成方法。In a semiconductor device having a contact hole,
The upper portion of the wafer where the contact hole is formed, and depositing a first titanium layer by sputtering using a plasma density not exceeding 10 10 / cm 3,
On said first titanium layer, a semiconductor, characterized in that it comprises a step of depositing a second titanium layer using a plasma of at least 10 11 / cm 3 or more density while applying a bus ear scan A method of forming a titanium film of an apparatus. 上記第１チタニウム膜が2.0mTorrを越えない工程圧力下で蒸着されることを特徴とする請求項1記載の半導体装置のチタニウム膜の形成方法。2. The method of forming a titanium film in a semiconductor device according to claim 1, wherein the first titanium film is deposited under a process pressure not exceeding 2.0 mTorr. 上記第１チタニウム膜が450〜650℃の温度下で蒸着されることを特徴とする請求項２記載の半導体装置のチタニウム膜の形成方法。3. The method of forming a titanium film in a semiconductor device according to claim 2, wherein the first titanium film is deposited at a temperature of 450 to 650.degree. 上記第２チタニウム膜が少なくとも15mTorrの工程圧力下で蒸着されることを特徴とする請求項１記載の半導体装置のチタニウム膜の形成方法。2. The method of forming a titanium film in a semiconductor device according to claim 1, wherein the second titanium film is deposited under a process pressure of at least 15 mTorr. 上記第２チタニウム膜が450〜650℃の温度下で蒸着されることを特徴とする請求項４記載の半導体装置のチタニウム膜の形成方法。5. The method of forming a titanium film in a semiconductor device according to claim 4, wherein the second titanium film is deposited at a temperature of 450 to 650.degree. 上記第１及び第２チタニウム膜が同一チャンバ内で蒸着されることを特徴とする請求項１記載の半導体装置のチタニウム膜の形成方法。2. The method of forming a titanium film in a semiconductor device according to claim 1, wherein the first and second titanium films are deposited in the same chamber.
JP17934199A 1998-06-27 1999-06-25 Method for forming titanium film of semiconductor device Expired - Fee Related JP3694803B2 (en)

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KR10-1998-0024584A KR100484253B1 (en) 1998-06-27 1998-06-27 Titanium film formation method of semiconductor device
KR1998-24584 1998-06-27

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JPH02291124A (en) 1989-04-28 1990-11-30 Fujitsu Ltd Manufacture of semiconductor device
JP2660359B2 (en) * 1991-01-30 1997-10-08 三菱電機株式会社 Semiconductor device
KR0126457B1 (en) * 1992-01-08 1997-12-26 기타오카 다카시 Large scale integrated circuit device and thin film forming method and apparatus for the same
US6197686B1 (en) * 1992-03-03 2001-03-06 Sony Corporation Aluminum metallization by a barrier metal process
US5397962A (en) * 1992-06-29 1995-03-14 Texas Instruments Incorporated Source and method for generating high-density plasma with inductive power coupling
JPH06120176A (en) 1992-06-30 1994-04-28 Ashida:Kk Method and apparatus of etching
EP0608409B1 (en) 1992-08-14 1997-05-07 Hughes Aircraft Company Surface preparation and deposition method for titanium nitride onto cast iron
US5350629A (en) * 1993-03-01 1994-09-27 Storage Technology Corporation Magnetoresistive device and barrier formation process
JPH06268083A (en) 1993-03-11 1994-09-22 Sony Corp Wiring of semiconductor device
US5512164A (en) 1993-06-03 1996-04-30 The United States Of America As Represented By The United States Department Of Energy Method for sputtering with low frequency alternating current
US5455197A (en) 1993-07-16 1995-10-03 Materials Research Corporation Control of the crystal orientation dependent properties of a film deposited on a semiconductor wafer
KR0124489B1 (en) * 1993-11-23 1997-12-10 김주용 Forming method of titanium nitride film for semiconductor device
JPH07263444A (en) 1994-03-17 1995-10-13 Matsushita Electron Corp Semiconductor device
JPH07263572A (en) 1994-03-23 1995-10-13 Hitachi Ltd Manufacture of semiconductor memory device and semiconductor memory device and application system using it
JPH07283214A (en) 1994-04-04 1995-10-27 Mitsubishi Electric Corp Manufacture of semiconductor device
US5580823A (en) * 1994-12-15 1996-12-03 Motorola, Inc. Process for fabricating a collimated metal layer and contact structure in a semiconductor device
KR960026167A (en) * 1994-12-20 1996-07-22 김주용 Contact method of semiconductor device
JPH08176823A (en) * 1994-12-26 1996-07-09 Sony Corp Formation of thin film of high melting point metal
JP2616733B2 (en) 1994-12-28 1997-06-04 日本電気株式会社 Method for manufacturing semiconductor device
US5604140A (en) 1995-05-22 1997-02-18 Lg Semicon, Co. Ltd. Method for forming fine titanium nitride film and method for fabricating semiconductor element using the same
US6054382A (en) * 1996-03-28 2000-04-25 Texas Instruments Incorporated Method of improving texture of metal films in semiconductor integrated circuits
JPH1022379A (en) * 1996-06-28 1998-01-23 Fujitsu Ltd Manufacture of semiconductor device
JP2985789B2 (en) * 1996-08-30 1999-12-06 日本電気株式会社 Method for manufacturing semiconductor device
JP3393465B2 (en) * 1996-11-13 2003-04-07 東京エレクトロン株式会社 Method for manufacturing semiconductor device
KR100253311B1 (en) * 1997-09-02 2000-06-01 김영환 Planation method of semiconductor device
US5985759A (en) * 1998-02-24 1999-11-16 Applied Materials, Inc. Oxygen enhancement of ion metal plasma (IMP) sputter deposited barrier layers
US6171717B1 (en) * 1998-10-28 2001-01-09 United Microelectronics Corp. Structure of stacked barrier layer

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