JP3655901B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- JP3655901B2 JP3655901B2 JP2002238032A JP2002238032A JP3655901B2 JP 3655901 B2 JP3655901 B2 JP 3655901B2 JP 2002238032 A JP2002238032 A JP 2002238032A JP 2002238032 A JP2002238032 A JP 2002238032A JP 3655901 B2 JP3655901 B2 JP 3655901B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- temperature
- semiconductor device
- interlayer insulating
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/2856—Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
- G01R31/2858—Measuring of material aspects, e.g. electro-migration [EM], hot carrier injection
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
- G01R31/286—External aspects, e.g. related to chambers, contacting devices or handlers
- G01R31/2868—Complete testing stations; systems; procedures; software aspects
- G01R31/287—Procedures; Software aspects
Landscapes
- Engineering & Computer Science (AREA)
- Environmental & Geological Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Tests Of Electronic Circuits (AREA)
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002238032A JP3655901B2 (ja) | 2002-08-19 | 2002-08-19 | 半導体装置の製造方法 |
| US10/642,222 US7157368B2 (en) | 2002-08-19 | 2003-08-18 | Method of accelerating test of semiconductor device |
| US11/561,293 US7485475B2 (en) | 2002-08-19 | 2006-11-17 | Method of accelerating test of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002238032A JP3655901B2 (ja) | 2002-08-19 | 2002-08-19 | 半導体装置の製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2004077283A JP2004077283A (ja) | 2004-03-11 |
| JP2004077283A5 JP2004077283A5 (https=) | 2005-02-03 |
| JP3655901B2 true JP3655901B2 (ja) | 2005-06-02 |
Family
ID=32021567
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002238032A Expired - Lifetime JP3655901B2 (ja) | 2002-08-19 | 2002-08-19 | 半導体装置の製造方法 |
Country Status (2)
| Country | Link |
|---|---|
| US (2) | US7157368B2 (https=) |
| JP (1) | JP3655901B2 (https=) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070128827A1 (en) * | 2001-09-12 | 2007-06-07 | Faris Sadeg M | Method and system for increasing yield of vertically integrated devices |
| US7397260B2 (en) * | 2005-11-04 | 2008-07-08 | International Business Machines Corporation | Structure and method for monitoring stress-induced degradation of conductive interconnects |
| US11031342B2 (en) | 2017-11-15 | 2021-06-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor package and method |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2612210B2 (ja) | 1990-03-05 | 1997-05-21 | 日本電信電話株式会社 | 半導体集積回路配線の評価方法 |
| JP3847807B2 (ja) * | 1995-01-30 | 2006-11-22 | 財団法人国際科学振興財団 | 半導体装置 |
| JPH1012687A (ja) | 1996-06-20 | 1998-01-16 | Matsushita Electric Works Ltd | 半導体チップの検査方法 |
| US5930587A (en) * | 1997-08-27 | 1999-07-27 | Lucent Technologies | Stress migration evaluation method |
| US6342733B1 (en) * | 1999-07-27 | 2002-01-29 | International Business Machines Corporation | Reduced electromigration and stressed induced migration of Cu wires by surface coating |
| JP2001237348A (ja) * | 2000-02-23 | 2001-08-31 | Hitachi Ltd | 半導体装置およびその製造方法 |
| JP2002057252A (ja) * | 2000-08-07 | 2002-02-22 | Hitachi Ltd | 半導体装置及びその製造方法 |
-
2002
- 2002-08-19 JP JP2002238032A patent/JP3655901B2/ja not_active Expired - Lifetime
-
2003
- 2003-08-18 US US10/642,222 patent/US7157368B2/en not_active Expired - Fee Related
-
2006
- 2006-11-17 US US11/561,293 patent/US7485475B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2004077283A (ja) | 2004-03-11 |
| US20070077762A1 (en) | 2007-04-05 |
| US7485475B2 (en) | 2009-02-03 |
| US7157368B2 (en) | 2007-01-02 |
| US20040106219A1 (en) | 2004-06-03 |
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