JP3647448B2 - 半導体装置及び半導体装置の製造方法 - Google Patents
半導体装置及び半導体装置の製造方法 Download PDFInfo
- Publication number
- JP3647448B2 JP3647448B2 JP2004168845A JP2004168845A JP3647448B2 JP 3647448 B2 JP3647448 B2 JP 3647448B2 JP 2004168845 A JP2004168845 A JP 2004168845A JP 2004168845 A JP2004168845 A JP 2004168845A JP 3647448 B2 JP3647448 B2 JP 3647448B2
- Authority
- JP
- Japan
- Prior art keywords
- die pad
- semiconductor element
- semiconductor device
- resin
- view
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004168845A JP3647448B2 (ja) | 2004-06-07 | 2004-06-07 | 半導体装置及び半導体装置の製造方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2004168845A JP3647448B2 (ja) | 2004-06-07 | 2004-06-07 | 半導体装置及び半導体装置の製造方法 |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP35644699A Division JP3602997B2 (ja) | 1999-12-15 | 1999-12-15 | 半導体装置及び半導体装置の製造方法 |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2005004182A Division JP4418373B2 (ja) | 2005-01-11 | 2005-01-11 | 半導体装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2004260216A JP2004260216A (ja) | 2004-09-16 |
| JP3647448B2 true JP3647448B2 (ja) | 2005-05-11 |
| JP2004260216A5 JP2004260216A5 (enExample) | 2005-06-02 |
Family
ID=33128737
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2004168845A Expired - Fee Related JP3647448B2 (ja) | 2004-06-07 | 2004-06-07 | 半導体装置及び半導体装置の製造方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3647448B2 (enExample) |
-
2004
- 2004-06-07 JP JP2004168845A patent/JP3647448B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2004260216A (ja) | 2004-09-16 |
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