JP3637680B2 - 露光装置 - Google Patents
露光装置 Download PDFInfo
- Publication number
- JP3637680B2 JP3637680B2 JP10621796A JP10621796A JP3637680B2 JP 3637680 B2 JP3637680 B2 JP 3637680B2 JP 10621796 A JP10621796 A JP 10621796A JP 10621796 A JP10621796 A JP 10621796A JP 3637680 B2 JP3637680 B2 JP 3637680B2
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- exposure
- circuit pattern
- coordinate value
- sample circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
- Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10621796A JP3637680B2 (ja) | 1996-04-02 | 1996-04-02 | 露光装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10621796A JP3637680B2 (ja) | 1996-04-02 | 1996-04-02 | 露光装置 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JPH09275066A JPH09275066A (ja) | 1997-10-21 |
| JPH09275066A5 JPH09275066A5 (enExample) | 2004-07-15 |
| JP3637680B2 true JP3637680B2 (ja) | 2005-04-13 |
Family
ID=14427991
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10621796A Expired - Fee Related JP3637680B2 (ja) | 1996-04-02 | 1996-04-02 | 露光装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3637680B2 (enExample) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP1182508B1 (de) * | 2000-08-14 | 2012-12-12 | Vistec Electron Beam GmbH | Verfahren zum Belichten eines aus mehreren Ebenen bestehenden Layouts auf einem Wafer |
| JP4340638B2 (ja) * | 2004-03-02 | 2009-10-07 | エーエスエムエル ネザーランズ ビー.ブイ. | 基板の表側または裏側に結像するためのリソグラフィ装置、基板識別方法、デバイス製造方法、基板、およびコンピュータプログラム |
| US7808613B2 (en) | 2006-08-03 | 2010-10-05 | Asml Netherlands B.V. | Individual wafer history storage for overlay corrections |
| JP7359899B1 (ja) * | 2022-04-27 | 2023-10-11 | 華邦電子股▲ふん▼有限公司 | 半導体製造装置及びその半導体製造方法 |
-
1996
- 1996-04-02 JP JP10621796A patent/JP3637680B2/ja not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH09275066A (ja) | 1997-10-21 |
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