JP3592887B2 - Nonvolatile semiconductor memory device - Google Patents

Description

【００５１】
図６〜図８は、それぞれデ−タの読み出し、書き込み、消去の動作を示す波形図である。本実施例では、読み出しと書き込みにおいて ＢｉｔｌｉｎｅＥを選択、 ＢｉｔｌｉｎｅＯを非選択としている。
【００５２】
初めに、読み出し動作を説明する。選択ビット線は１．５Ｖに充電され、その後フロ−ティングにされる。その後、非選択ワ−ド線ＷＬ２〜８と選択ゲ−ト線ＳＧＳ、ＳＧＤは電源電圧ＶＣＣにされる．選択ワ−ド線は０Ｖである。選択されたメモリセルのデ−タが“０”であるときビット線は０Ｖに放電され、さもなければビット線は１．５Ｖのままである。
【００５３】
ビット線電圧は、信号ＳＢＬ１によって第１の２値センスアンプに読み込まれる。従って、ノ−ドＮ１はデ−タが“０”ならばＬ、“１”又は“２”ならばＨとなる。選択されたワ−ド線はＶＧ１（＝１．８Ｖ）にされる。選択されたメモリセルのデ−タが“１”ならば０Ｖに放電され、“２”ならば１．５Ｖのままとなる。“０”ならばビット線は既に０Ｖである。ビット線電圧は信号ＳＢＬ２によって第２の２値センスアンプに読み込まれる。従って、ノ−ドＮ２はデ−タが“０”又は“１”ならばＬ、“２”ならばＨとなる（表１）。ラッチされたデ−タはシリアルにＩ／Ｏ線に読み出される。
【００５４】
次に、書き込み動作を説明する。電源投入時、チップが正常動作するのに十分な電圧に達するとパワ−オン信号ＰｏｎがＨになる。この信号を利用して３値センスアンプ兼ラッチ回路４のラッチデ−タＮ１、２は共にＬにされる。書き込みデ−タを入力するためのコマンドが入ると、このコマンド信号を使つてラッチデ−タＮ１、２は反転し共にＨとなる。
【００５５】
選択されたビット線には書き込みデ−タ“０〜２”に応じてそれぞれＶＣＣ、ＶＤ３−Ｖｔ（＝１Ｖ）、０Ｖにされる。非選択のビット線には、デ−タ変更しないための電圧ＶＣＣが印加される。選択ゲ−ト線ＳＧＤは、ＶＣＣに、ＳＧＳは０Ｖに、選択ワ−ド線はＶＰＰ（＝２０Ｖ）に、非選択ワ−ド線はＶＭ１０ （＝１０Ｖ）にそれぞれされる。なお、ここでセンスアンプ兼ラッチ回路４からビット線に出力される電圧のうち、０Ｖが書き込み電圧、ＶＣＣが非書き込み電圧に相当する。
【００５６】
ビット線に０Ｖ、１Ｖが印加された選択メモリセルでは、ゲ−ト・チャネル間電圧が高いためトンネル電流が流れてメモリセルのしきい電圧は上昇する。ビット線が０Ｖである方が１Ｖである方よりトンネル電流が多く流れるため、しきい電圧はより高くなる。ＶＣＣが印加された選択メモリセルはゲ−ト・チャネル間電圧が低いためトンネル電流は流れず、“０”を保持する。
【００５７】
最後に、消去動作を説明する。消去コマンドが入力されると、メモリセルアレイ２のウェルはＶＰＰ（＝２０Ｖ）が印加される。選択されたメモリセルのゲ−トは０Ｖにされるため、トンネル電流が書き込み時とは反対方向に流れ、メモリセルのしきい電圧は下降する。一方、非選択のメモリセル及び選択トランジスタのゲ−トはフロ−ティングにされるため、メモリセルアレイ２のウェルと共にＶＰＰ近くまで上昇する。このため、トンネル電流は流れずしきい電圧の変動はない。
【００５８】
＜消去ベリファイリ−ド＞
以下ではタイミング図を用いて消去ベリファイリ−ド動作を説明する。ブロック単位で消去が行われる場合には、１ブロック内のメモリセル（例えばワ−ド線ＷＬ１〜ＷＬ８で選択されるメモリセル）に対して、奇数ペ−ジと偶数ペ−ジの２回に分けてベリファイリ−ドを行う。図９はタイミング図である。図１０は消去ベリファイリ−ドを説明するブロック図である。
【００５９】
ベリファイリ−ドは、まず、偶数ペ−ジ（例えば図２のビット線ＢｉｔｌｉｎｅＥに接続するメモリセル）について行い、第１のラッチ回路に読み出しデ−タを保持する。次に奇数ペ−ジ（例えば図２のビット線ＢｉｔｌｉｎｅＯに接続するメモリセル）について行い第２のラッチ回路に読み出しデ−タを保持する。
【００６０】
まず、ビット線ＢｉｔｌｉｎｅＥを１．５Ｖにプリチャ−ジした後に、時刻ｔ１に選択ゲ−ト線ＳＧＳ、ＳＧＤをＶｃｃ、ワ−ド線ＷＬ１〜ＷＬ８は０Ｖにすると、メモリセルが消去十分の場合には、ビット線は０Ｖになり、消去不十分の場合には１．５Ｖを保つ。時刻ｔ２にＢＬＳＨＦＥが１．５Ｖになり、ビット線の電位がデ−タ回路内に転送され、その後、ＳＢＬ１が“Ｈｉｇｈ”になることにより、デ−タがノ−ドＮ１に転送され、センスされる。このように偶数ペ−ジのデ−タは第１のラッチ回路に保持される。偶数ペ−ジの読み出し中は、ビット線間容量結合ノイズを低減するためにビット線ＢｉｔｌｉｎｅＯは０Ｖに保たれる。
【００６１】
続いて、奇数ペ−ジ（例えば図２のビット線ＢｉｔｌｉｎｅＯに接続するメモリセル）について行う。ビット線ＢｉｔｌｉｎｅＯを１．５Ｖにプリチャ−ジした後に、時刻ｔ４に選択ゲ−ト線ＳＧＳ、ＳＧＤをＶｃｃ、ワ−ド線ＷＬ１〜ＷＬ８は０Ｖにすると、メモリセルが消去十分の場合には、ビット線は０Ｖになり、消去不十分の場合には１．５Ｖを保つ。時刻ｔ５にＢＬＳＨＦＯが１．５Ｖになり、ビット線の電位がデ−タ回路内に転送され、その後、ＳＢＬ２が“Ｈｉｇｈ”になることにより、デ−タがノ−ドＮ２に転送され、センスされる。このように奇数ペ−ジのデ−タは第２のラッチ回路に保持される。奇数ペ−ジの読み出し中は、ビット線間容量結合ノイズを低減するために、ビット線ＢｉｔｌｉｎｅＥは０Ｖに保たれる。
【００６２】
偶数ペ−ジと奇数ペ−ジの読み出しデ−タはそれぞれ第１のラッチ回路及び、第２のラッチ回路に保持される。その後、カラムデコ−ダによって順次カラムを選択する事により、第１および第２のラッチ回路のデ−タをほぼ同時に出力する。これにより、消去が十分に行われたか否かが分かる。
【００６３】
図１０からわかるように従来例では第１のラッチ回路のみを用いてベリファイリ−ドを行うのに対し、本実施例では第１のラッチ回路と第２のラッチ回路を両方用いているので、ベリファイリ−ドを高速化することができる。
【００６４】
上記実施例で、最初に偶数ペ−ジのメモリセルを読み出して第１のラッチ回路に読み出した後に、奇数ペ−ジのメモリセルを読み出す間に第１のラッチ回路に保持した読み出しデ−タをＤＬｉ、ｎＤＬｉを通じて出力しても良い。
【００６５】
同様に、ほぼ同時に消去された第１のブロック及び第２のブロック内のメモリセルに対して、２回の分けてベリファイリ−ドを行ったうえで、読み出しデ−タをそれぞれ第１、第２のラッチ回路に保持させてもよい。このように、複数のブロックをほぼ同時に消去する場合には、図１１のように消去すればよい。つまり、まず第１、第２、・・・第ｎ（ｎは自然数）のブロックの消去をほぼ同時に行い、次に上記で説明した１ブロック単位のベリファイリ−ドを消去を行ったブロック毎に行う。
【００６６】
さらに、デ−タ回路が第１、第２、・・・第ｎのラッチ回路で構成される場合は、各読み出しデ−タをそれぞれ第１、第２、・・・第ｎのラッチ回路に保持させることも無論可能である。
【００６７】
また、図３６のようなセルアレイに対し、１ビット線あたり１つのデ−タ回路を有する場合でも本発明は有効である。デ−タ回路は図２のように２つのラッチ回路を有する場合を例にとる。
【００６８】
図３６の第１のブロックと第２のブロックを同時に消去する場合には、ベリファイリ−ドでは先ず第１のブロックのベリファイリ−ドを行い、第１のラッチ回路に読み出したデ−タを保持する。次に第２のブロックのベリファイリ−ドを行い、第２のラッチ回路に読み出したデ−タを保持する。その後、第１のラッチ回路及び、第２のラッチ回路に保持された第１のブロックのデ−タと第２のブロックのデ−タを、カラムデコ−ダによって順次カラムを選択する事により、第１および第２のラッチ回路からほぼ同時に出力する。これにより、消去が十分に行われたか否かがわかる。
【００６９】
この場合も、従来例では第１のラッチ回路のみを用いてベリファイリ−ドを行うのに対し、本実施例では第１のラッチ回路と第２のラッチ回路を両方用いているので、図３６のメモリセルアレイでもベリファイリ−ドを高速化することができる。
【００７０】
消去終了の検出は、上記のように第１、第２、・・・のラッチ回路のデ−タをＩ／Ｏ線に出力する他に、例えば図２５に示されるような消去終了一括検知トランジスタＱＮＬ９、ＱＮＬ１０、・・・を用いて一括検知してもよい。
【００７１】
上記のように、偶数ペ−ジ及び奇数ペ−ジのデ−タをそれぞれ第１、第２のラッチ回路、又は第１のブロックから第ｎのブロックまでのデ−タを第１、・・・第ｎのラッチ回路に読み出した後に、まずＶＲＴを例えばＶｃｃにプリチャ−ジする。消去が不十分なメモリセルが存在するカラムではノ−ドＮ１、Ｎ２、・・・のうち少なくとも一つは“Ｈｉｇｈ”になり、ｎチャネルＭＯＳトランジスタＱＮＬ９、ＱＮＬ１０、・・・のうち少なくとも一つがオンしＶＲＴはプリチャ−ジ電位から低下する。選択したすべてのメモリセルが十分に消去される場合に限り、すべてのカラムでノ−ドＮ１およびＮ２は“Ｌｏｗ”になる。その結果、全てのデ−タ回路内のｎチャネルＭＯＳトランジスタＱＮＬ９、ＱＮＬ１０、・・・がオフになるので、ＶＲＴは、プリチャ−ジ電位を保ち、消去終了が検知される。
【００７２】
［実施例２］
（１）１ブロック消去の場合
図１２が１ブロックの消去ベリファイリ−ドの動作を説明する概略図、図１３がタイミング図である。
【００７３】
ベリファイリ−ドは、まず、偶数ペ−ジ（例えば図２のビット線ＢｉｔｌｉｎｅＥに接続するメモリセル）について行い第１のラッチ回路に読み出しデ−タを保持する。次に奇数ペ−ジ（例えば図２のビット線ＢｉｔｌｉｎｅＯに接続するメモリセル）について行い第１のラッチ回路に読み出しデ−タを保持する。
【００７４】
ベリファイリ−ドに先立ち、ノ−ドＮ１は“Ｌｏｗ”、ノ−ドＮ３は“Ｈｉｇｈ”にセットされる。まず、ビット線ＢｉｔｌｉｎｅＥを１．５Ｖにプリチャ−ジした後に、時刻ｔ１ｖに選択ゲ−ト線ＳＧＳ、ＳＧＤをＶｃｃ、ワ−ド線ＷＬ１〜ＷＬ８は０Ｖにすると、メモリセルが消去十分の場合には、ビット線は０Ｖになり、消去不十分の場合には１．５Ｖを保つ。時刻ｔ２ｖにＢＬＳＨＦＥが１．５Ｖになり、ビット線の電位がデ−タ回路内に転送される。その後、時刻ｔ３ｖにｎＶＥＲＩＦＹが“Ｌｏｗ”になる。ノ−ドＮ３は“Ｈｉｇｈ”にセットされているのでｐチャネルトランジスタＱｐ３はオフし、ノ−ドＮ４の電位を変化しない。
【００７５】
この１ブロックの消去ベリファイリ−ド動作では、この時刻ｔ３ｖにｎＶＥＲＩＦＹを“Ｌｏｗ”にする動作、および第１のラッチ回路のセット（ノ−ドＮ３を“Ｈｉｇｈ”にする動作）は省略することができる。
【００７６】
その後、ＳＢＬ１が“Ｈｉｇｈ”になることにより、デ−タがノ−ドＮ１に転送され、センスされる。このように偶数ペ−ジのデ−タは第１のラッチ回路に保持される。偶数ペ−ジの読み出し中は、ビット線間容量結合ノイズを低減するためにビット線ＢｉｔｌｉｎｅＯは０Ｖに保たれる。以上のベリファイリ−ドの結果、消去不十分の場合にはノ−ドＮ１は“Ｈｉｇｈ”、消去十分の場合にはノ−ドＮ１は“Ｌｏｗ”になる。
【００７７】
続いて、奇数ペ−ジ（例えば図２のビット線ＢｉｔｌｉｎｅＯに接続するメモリセル）についてベリファイリ−ドを行う。ビット線ＢｉｔｌｉｎｅＯを１．５Ｖにプリチャ−ジした後に、時刻ｔ５ｖに選択ゲ−ト線ＳＧＳ、ＳＧＤをＶｃｃ、ワ−ド線ＷＬ１〜ＷＬ８は０Ｖにすると、メモリセルが消去十分の場合には、ビット線は０Ｖになり、消去不十分の場合には１．５Ｖを保つ。時刻ｔ６ｖにＢＬＳＨＦＯが１．５Ｖになり、ビット線の電位がデ−タ回路内に転送される。その後、時刻ｔ７ｖにｎＶＥＲＩＦＹが“Ｌｏｗ”になる。
【００７８】
偶数ペ−ジを読み出した結果、消去十分の場合は、ノ−ドＮ３は“Ｈｉｇｈ”がラッチされているので、ｐチャネルトランジスタＱｐ３はオフし、ノ−ドＮ４の電位を変化しない。つまり、奇数ペ−ジが消去不十分ならばノ−ドＮ４は“Ｈｉｇｈ”、消去十分ならばノ−ドＮ４は“Ｌｏｗ”になる。
【００７９】
一方、偶数ペ−ジを読み出した結果、消去不十分の場合は、ノ−ドＮ３は“Ｌｏｗ”がラッチされているので、ｐチャネルトランジスタＱｐ３はオンし、ノ−ドＮ４の電位は奇数ペ−ジのデ−タによらず“Ｈｉｇｈ”になる。
【００８０】
その後、ＳＢＬ１が“Ｈｉｇｈ”になることにより、デ−タがノ−ドＮ１に転送され、センスされる。奇数ペ−ジの読み出し中は、ビット線間容量結合ノイズを低減するために、ビット線ＢｉｔｌｉｎｅＥは０Ｖに保たれる。
【００８１】
以上のベリファイリ−ド動作の結果、表２のように偶数ペ−ジと奇数ペ−ジのうち、１つでも消去不十分のセルがあると、Ｎ１は“Ｈｉｇｈ”になる。偶数ぺ−ジと奇数ペ−ジが共に消去十分の場合に限り、Ｎ１は“Ｌｏｗ”になる。
【００８２】
【表２】

【００８３】
このように時刻ｔ７ｖにｎＶＥＲＩＦＹを“Ｌｏｗ゛にすることにより、第１のラッチ回路のみを用いて消去のベリファイリ−ドを行うことができる。
【００８４】
偶数ペ−ジと奇数ペ−ジの読み出しデ−タを第１のラッチ回路に読み出した後に、カラムデコ−ダによって順次カラムを選択する事により、第１のラッチ回路のデ−タを出力する。これにより、消去が十分に行われたか否かがわかる。
【００８５】
（２）複数のブロックをほぼ同時に消去する場合
次に、複数のブロックの消去、及びベリファイリ−ドを図１４、図１３を用いて説明する。まず第１、第２、・・・第ｎ（ｎは自然数）のブロックの消去をほぼ同時に行う。その後、各ブロックの消去ベリファイリ−ドを行う。＜実施例１＞と異なるのは、第１のラッチ回路に読み出したデ−タの出力を、各ブロックのベリファイリ−ドをするたびに行う必要はなく、図１４のように第１、第２、・・・第ｎ（ｎは自然数）のブロックのデ−タを第１のラッチ回路に読み出した後に１回だけ行えば良い。
【００８６】
第１のブロックの消去ベリファイリ−ドは、１ブロック消去のベリファイリ−ドとほぼ同様である。タイミング図は図１３とほぼ同様である。図１３と異なるのは、第２のブロックの消去ベリファイ後には第１のラッチ回路の読み出しデ−タをＤＬｉ、ｎＤＬｉに出力せず、第１から第ｎの消去ベリファイリ−ド終了後に第１のラッチ回路の読み出しデ−タをＤＬｉ、ｎＤＬｉに出力する。
【００８７】
ベリファイリ−ドは、まず、第１のブロックの偶数ペ−ジ（例えば図２のビット線ＢｉｔｌｉｎｅＥに接続するメモリセル）について行い、第１のラッチ回路に読み出しデ−タを保持する。次に、奇数ペ−ジ（例えば図２のビット線ＢｉｔｌｉｎｅＯに接続するメモリセル）について行い、第１のラッチ回路に読み出しデ−タを保持する。
【００８８】
ベリファイリ−ドに先立ち、ノ−ドＮ１は“Ｌｏｗ”、ノ−ドＮ３は“Ｈｉｇｈ”にセットされる。まず、ビット線ＢｉｔｌｉｎｅＥを１．５Ｖにプリチャ−ジした後に、時刻ｔ１ｖに選択ゲ−ト線ＳＧＳ、ＳＧＤをＶｃｃ、ワ−ド線ＷＬ１〜ＷＬ８は０Ｖにすると、メモリセルが消去十分の場合には、ビット線は０Ｖになり、消去不十分の場合には１．５Ｖを保つ。時刻ｔ２ｖにＢＬＳＨＦＥが１．５Ｖになり、ビット線の電位がデ−タ回路内に転送される。その後、時刻ｔ３ｖにｎＶＥＲＩＦＹが“Ｌｏｗ”になる。ノ−ドＮ３は“Ｈｉｇｈ”にセットされているのでｐチャネルトランジスタＱｐ３はオフし、ノ−ドＮ４の電位を変化しない。
【００８９】
この１ブロックの消去ベリファイリ−ド動作では、時刻ｔ３ｖにｎＶＥＲＩＦＹを“Ｌｏｗ”にする動作、および第１のラッチ回路のセット（ノ−ドＮ３を“Ｈｉｇｈ”にする動作）は省略することができる。
【００９０】
その後、ＳＢＬ１が“Ｈｉｇｈ”になることにより、デ−タがノ−ドＮ１に転送され、センスされる。
【００９１】
このように、第１のブロックの偶数ペ−ジのデ−タは第１のラッチ回路に保持される。偶数ペ−ジの読み出し中は、ビット線間容量結合ノイズを低減するためにビット線ＢｉｔｌｉｎｅＯは０Ｖに保たれる。以上のベリファイリ−ドの結果、消去不十分の場合にはノ−ドＮ１は“Ｈｉｇｈ”、消去十分の場合にはノ−ドＮ１は“Ｌｏｗ”になる。
【００９２】
続いて、第１のブロックの奇数ペ−ジ（例えば図２のビット線ＢｉｔｌｉｎｅＯに接続するメモリセル）についてベリファイリ−ドを行う。ビット線ＢｉｔｌｉｎｅＯを１．５Ｖにプリチャ−ジした後に、時刻ｔ５ｖに選択ゲ−ト線ＳＧＳ、ＳＧＤをＶｃｃ、ワ−ド線ＷＬ１〜ＷＬ８は０Ｖにすると、メモリセルが消去十分の場合には、ビット線は０Ｖになり、消去不十分の場合には１．５Ｖを保つ。時刻ｔ６ｖにＢＬＳＨＦＯが１．５Ｖになり、ビット線の電位がデ−タ回路内に転送される。その後、時刻ｔ７ｖにｎＶＥＲＩＦＹが“Ｌｏｗ”になる。
【００９３】
第１のブロックの偶数ペ−ジを読み出した結果、消去十分の場合は、ノ−ドＮ３は“Ｈｉｇｈ”がラッチされているので、ｐチャネルトランジスタＱｐ３はオフし、ノ−ドＮ４の電位を変化しない。つまり、奇数ペ−ジが消去不十分ならばノ−ドＮ４は“Ｈｉｇｈ”、消去十分ならばノ−ドＮ４は“Ｌｏｗ”になる。
【００９４】
一方、偶数ペ−ジを読み出した結果、消去不十分の場合は、ノ−ドＮ３は“Ｌｏｗ”がラッチされているので、ｐチャネルトランジスタＱｐ３はオンし、ノ−ドＮ４の電位は奇数ペ−ジのデ−タによらず“Ｈｉｇｈ”になる。
【００９５】
その後、ＳＢＬ１が“Ｈｉｇｈ”になることにより、デ−タがノ−ドＮ１に転送され、センスされる。奇数ペ−ジの読み出し中は、ビット線間容量結合ノイズを低減するために、ビット線ＢｉｔｌｉｎｅＥは０Ｖに保たれる。
【００９６】
以上のベリファイリ−ド動作の結果、上記表２のように第１のブロックの偶数ぺ−ジと奇数ペ−ジのうち、１つでも消去不十分のセルがあると、Ｎ１は“Ｈｉｇｈ”になる。第１のブロックの偶数ペ−ジと奇数ペ−ジが共に消去十分の場合に限り、Ｎ１は“Ｌｏｗ”になる。
【００９７】
引き続き、第２のブロックの消去ベリファイリ−ドを行う。タイミング図は図１３とほぼ同様である。図１３と異なるのは、第２のブロックの消去ベリファイ後には第１のラッチ回路の読み出しデ−タをＤＬｉ、ｎＤＬｉに出力せず、第１から第ｎの消去ベリファイリ−ド終了後に第１のラッチ回路の読み出しデ−タをＤＬｉ、ｎＤＬｉに出力する。
【００９８】
ベリファイリ−ドはまず第２のブロックの偶数ペ−ジ（例えば図２のビット線ＢｉｔｌｉｎｅＥに接続するメモリセル）について行い第１のラッチ回路に読み出しデ−タを保持する。次に第２のブロックの奇数ペ−ジ（例えば図２のビット線ＢｉｔｌｉｎｅＯに接続するメモリセル）について行い第１のラッチ回路に読み出しデ−タを保持する。
【００９９】
第１のブロックの消去ベリファイリ−ドと異なり第１のラッチ回路のセットは行わず、第１のラッチ回路は第１のブロックの消去ベリファイリ−ドの結果を保持する。つまり、第１のブロックの消去ベリファイリ−ドを行った結果、偶数ペ−ジと奇数ペ−ジのうち、１つでも消去不十分のセルがあると、Ｎ１は“Ｈｉｇｈ”である。
【０１００】
まず、ビット線ＢｉｔｌｉｎｅＥを１．５Ｖにプリチャ−ジした後に、時刻ｔ１ｖに選択ゲ−ト線ＳＧＳ、ＳＧＤをＶｃｃ、ワ−ド線ＷＬ１〜ＷＬ８は０Ｖにすると、メモリセルが消去十分の場合には、ビット線は０Ｖになり、消去不十分の場合には１．５Ｖを保つ。時刻ｔ２ｖにＢＬＳＨＦＥが１．５Ｖになり、ビット線の電位がデ−タ回路内に転送される。その後、時刻ｔ３ｖにｎＶＥＲＩＦＹが“Ｌｏｗ”になる。
【０１０１】
第２のブロックに先だってベリファイリ−ドしたブロック（この場合第１のブロック）内のメモリセルが消去不十分の場合には、ノ−ドＮ３は“Ｌｏｗ”なのでｐチャネルトランジスタＱｐ３はオンし、ビット線の電位にかかわらずノ−ドＮ４の電位はＶｃｃになる。
【０１０２】
一方、第２のブロックに先だってベリファイリ−ドしたブロック（この場合第１のブロック）内のメモリセルがすべて消去十分の場合には、ノ−ドＮ３は“Ｈｉｇｈ”なのでｐチャネルトランジスタＱｐ３はオフし、ノ−ドＮ４の電位は変動しない。
【０１０３】
つまり、第２のブロックの奇数ペ−ジが消去不十分ならば、ノ−ドＮ４は“Ｈｉｇｈ”、消去十分ならばノ−ドＮ４は“Ｌｏｗ”になる。
【０１０４】
その後、ＳＢＬ１が“Ｈｉｇｈ”になることにより、デ−タがノ−ドＮ１に転送され、センスされる。
【０１０５】
このように、偶数ペ−ジのデ−タは第１のラッチ回路に保持される。第２のブロックの偶数ペ−ジの読み出し中は、ビット線間容量結合ノイズを低減するためにビット線ＢｉｔｌｉｎｅＯは０Ｖに保たれる。以上のベリファイリ−ドの結果、消去不十分の場合にはノ−ドＮ１は“Ｈｉｇｈ”、消去十分の場合にはノ一ドＮ１は“Ｌｏｗ”になる。
【０１０６】
続いて、第２のブロックの奇数ペ−ジ（例えば図２のビット線ＢｉｔｌｉｎｅＯに接続するメモリセル）についてベリファイリ−ドを行う。ビット線ＢｉｔｌｉｎｅＯを１．５Ｖにプリチャ−ジした後に、時刻ｔ５ｖに選択ゲ−ト線ＳＧＳ、ＳＧＤをＶｃｃ、ワ−ド線ＷＬ１〜ＷＬ８は０Ｖにすると、メモリセルが消去十分の場合には、ビット線は０Ｖになり、消去不十分の場合には１．５Ｖを保つ。時刻ｔ６ｖにＢＬＳＨＦＯが１．５Ｖになり、ビット線の電位がデ−タ回路内に転送される。その後、時刻ｔ７ｖにｎＶＥＲＩＦＹが“Ｌｏｗ”になる。
【０１０７】
このベリファイリ−ド動作以前のベリファイリ−ドで消去十分のメモリセルが１つでもある場合は、ノ−ドＮ３は“Ｈｉｇｈ”がラッチされているので、ｐチャネルトランジスタＱｐ３はオフし、ノ−ドＮ４の電位を変化しない。つまり、第２のブロックの奇数ペ−ジが消去不十分ならばノ−ドＮ４は“Ｈｉｇｈ”、消去十分ならばノ−ドＮ４は“Ｌｏｗ”になる。
【０１０８】
一方、このベリファイリ−ド動作以前のベリファイリ−ドですべてのメモリセルが十分に消去されている場合は、ノ−ドＮ３は“Ｌｏｗ”がラッチされているので、ｐチャネルトランジスタＱｐ３はオンし、ノ−ドＮ４の電位は第２のブロックの奇数ぺ−ジのデ−タによらず“Ｈｉｇｈ”になる。
【０１０９】
その後、ＳＢＬ１が“Ｈｉｇｈ”になることにより、デ−タがノ−ドＮ１に転送され、センスされる。奇数ペ−ジの読み出し中は、ビット線間容量結合ノイズを低減するために、ビット線ＢｉｔｌｉｎｅＥは０Ｖに保たれる。
【０１１０】
第ｉ（ｉは２以上ｎ以下の整数）のブロックの消去ベリファイリ−ドは上記第２の消去ベリファイリ−ドとほぼ同様に行えばよい。
【０１１１】
第１から第ｎの消去ベリファイリ−ドを行った結果、１つでも消去不十分のブロックがある場合は、ノ−ドＮ１は“Ｈｉｇｈ”になる。全てのメモリセルが消去十分の場合に限りノ−ドＮ１は“Ｌｏｗ”になる。
【０１１２】
この後、カラムデコ−ダによって順次カラムを選択する事により、第１のラッチ回路のデ−タをＤＬｉ、ｎＤＬｉに出力する。これにより、ほぼ同時に消去を行ったすべてのブロックで消去が十分に行われたか否かがわかる。
【０１１３】
消去終了の検出は上記のように第１のラッチ回路のデ−タをＤＬｉ、ｎＤＬｉに出力する他に、例えば図１５のように消去終了一括検知トランジスタＱ ＮＬ９を用いて一括検知してもよい。
【０１１４】
上記のように、第１のブロックから第ｎのブロックまでのデ−タを第１のラッチ回路に読み出した後に、まず、ＶＲＴを例えばＶｃｃにプリチャ−ジする。消去が不十分なメモリセルが存在するカラムではノ−ドＮ１は“Ｈｉｇｈ”になり、ｎチャネルＭＯＳトランジスタＱ ＮＬ９がオンしＶＲＴはプリチャ−ジ電位から低下する。選択したすべてのメモリセルが十分に消去される場合に限り、すべてのカラムでノ−ドＮ１は“Ｌｏｗ”になる。その結果、全てのデ−タ回路内のｎチャネルＭＯＳトランジスタＱ ＮＬ９がオフになるので、ＶＲＴはプリチャ−ジ電位を保ち、消去終了が検知される。
【０１１５】
以上で説明したように本発明では複数のブロックを同時に消去する場合には、消去ベリファイリ−ド時に図１４のように読み出しデ−タを次々に第１のラッチ回路に読み出す。すべてのブロックのデ−タを第１のラッチ回路に読み出した後に１回だけデ−タをＤＬｉ、ｎＤＬｉに出力する或いは、一括検知すればよいので、消去ベリファイリ−ドを高速に行うことができる。
【０１１６】
［実施例３］
（１） 電気的に書き換え可能な所定数のメモリセルから構成され、消去に際してほぼ同時に選択されるメモリセルグル−プを含むメモリセルアレイと、
前記メモリセルとデ−タの授受を行うビット線と、
前記ビット線と電気的に接続可能な信号線（ノ−ド）と、
前記信号線の電位をセンスすることでメモリセルの消去後の状態を読み出し、その情報を保持するデ−タ回路と、
複数のメモリセルグル−プをほぼ同時に消去した後、消去が十分に行われたかを調べるベリファイリ−ドの際に、
第１のメモリセルグル−プのベリファイリ−ドによって、信号線に読み出されデ−タ回路に保持された第１のデ−タと、第２のメモリセルグル−プのベリファイリ−ド時に、前記信号線に読み出された第２デ−タとの論理をとって、
第１のデ−タと第２のデ−タのうち少なくとも１つ消去不十分の場合には、前記信号線の電位を消去不十分レベルに、
第１のデ−タと第２のデ−タが共に消去十分の場合には、前記信号線の電位を消去十分レベルに自動設定する消去電位設定手段とを図２６，図２７のように備えたことを特徴とする。第１のメモリセルグル−プと第２のメモリセルグル−プは図２６のようにワ−ド線を共有し、異なるビット線に接続しても良い。あるいは図２７のように第１のメモリセルグル−プと第２のメモリセルグル−プは異なるワ−ド線に選択され、同じビット線に接続しても良い。また信号線とビット線の間にスイッチ回路を有しても良いし、なくても良い。
【０１１７】
（２） 電気的に書き換え可能な所定数のメモリセルから構成され、消去に際してほぼ同時に選択されるメモリセルグル−プを含むメモリセルアレイと、
前記メモリセルとデ−タの授受を行うビット線と、
メモリセルの消去後の状態をセンスしその情報を保持するデ−タ回路と、
前記ビット線と電気的に接続可能な信号線（ノ−ド）と
を備える不揮発性半導体記憶装置であり、
前記デ−タ回路は前記信号線の電位をセンスすることでメモリセルの状態を読み出し、
複数のメモリセルグル−プをほぼ同時に消去した後、消去が十分に行われたかを調べるベリファイリ−ドの際に、
第１のメモリセルグル−プのベリファイリ−ドを行い、信号線に読み出された第１のデ−タをデ−タ回路に保持し、
第２のメモリセルグル−プのべリファイリ−ドを行う際、前記信号線の電位を、デ−タ回路に保持する第１のデ−タに基づいて調節することを特徴とする。従って、図２０（ａ）のようにビット線がスイッチ回路を介して信号線に接続しても良い。また図２０（ｂ）でも良い。図２０（ｂ）ではビット線が信号線を兼ねるので、第２のメモリセルグル−プのベリファイリ−ドを行う際、前記信号線の電位を、デ−タ回路に保持する第１のデ−タに基づいて調節する際に、ビット線の電位も調整されることになる。もちろん、図２０（ａ）の場合でも、第２のメモリセルグル−プのベリファイリ−ドを行う際、前記信号線の電位を、デ−タ回路に保持する第１のデ−タに基づいて調節する際に、スイッチ回路をオンすることによりビット線の電位も調整してもよい。
【０１１８】
（３） 電気的に書き換え可能な所定数のメモリセルから構成され、消去に際してほぼ同時に選択されるメモリセルグル−プを含むメモリセルアレイと、
前記メモリセルとデ−タの授受を行うビット線と、
メモリセルの消去後の状態をセンスしその情報を保持するデ−タ回路と、
前記ビット線と電気的に接続可能な信号線（ノ−ド）と
を備える不揮発性半導体記憶装置において、
前記デ−タ回路は前記信号線の電位をセンスすることでメモリセルの状態を読み出し、
複数のメモリセルグル−プをほぼ同時に消去した後、消去が十分に行われたかを調べるベリファイリ−ドの際に、
第１のメモリセルグル−プのベリファイリ−ドを行い、信号線に読み出された第１のデ−タをデ−タ回路に保持し、
第２のメモリセルグル−プのベリファイリ−ドを行う際、前記信号線の電位を、デ−タ回路に保持する第１のデ−タに基づいて調節し、
かつ前記複数のメモリセルグル−プ中には、他のメモリセルグル−プ中のメモリセルと互いにワ−ド線を共有し、かつ異なるビット線に接続するメモリセルを含むことを特徴とする。
【０１１９】
従って、例えば図２１のようであればよい。もちろん図２１でスイッチ回路がなくてもよい。また例えば、図１５のＢｉｔｌｉｎｅＥに接続する第１のブロックのベリファイリ−ドを行い、読み出された第１のデ−タを図１５の第１のラッチ回路に保持する。その後、ＢｉｔｌｉｎｅＯに接続し第１のブロックとワ−ド線を共有する、第２のブロックのベリファイリ−ドを行い、読み出された第２のデ−タを図１５のノ−ドＮ４に転送する。そして第１のラッチ回路に保持した第１のデ−タに基づいて、ノ−ドＮ４の第２のデ−タを調整した後に、ノ−ドＮ４のデ−タを第１のラッチ回路に保持する。
【０１２０】
（４） 電気的に書き換え可能な所定数のメモリセルから構成され、消去に際してほぼ同時に選択されるメモリセルグル−プを含むメモリセルアレイと、
前記メモリセルとデ−タの授受を行うビット線と、
メモリセルの消去後の状態をセンスしその情報を保持するデ−タ回路と、
前記ビット線と電気的に接続可能な信号線（ノ−ド）と
を備える不揮発性半導体記憶装置において、
前記デ−タ回路は前記信号線の電位をセンスすることでメモリセルの状態を読み出し、
複数のメモリセルグル−プをほぼ同時に消去した後、消去が十分に行われたかを調べるベリファイリ−ドの際に、
第１のメモリセルグル−プのベリファイリ−ドを行い、信号線に読み出された第１のデ−タをデ−タ回路に保持し、
第２のメモリセルグル−プのベリファイリ−ドを行う際、前記信号線の電位を、デ−タ回路に保持する第１のデ−タに基づいて調節し、
かつ前記複数のメモリセルグル−プ中には、他のメモリセルグル−プ中のメモリセルと互いにワ−ド線が異なり、かつ同じビット線に接続するメモリセルを含むことを特徴とする。
【０１２１】
従って、例えば図２２のようであればよい。もちろん図２２でスイッチ回路 （ｎチャネルトランジスタのトランスファゲ−ト）がなくてもよい。また例えば、図１５のＢｉｔｌｉｎｅＥに接続する第１のブロックのベリファイリ−ドを行い、読み出された第１のデ−タを図１５の第１のラッチ回路に保持する。
【０１２２】
その後、ＢｉｔｌｉｎｅＥに接続し第１のブロックと異なるワ−ド線に接続する、第２のブロックのベリファイリ−ドを行い、読み出された第２のデ−タを図１５のノ−ドＮ４に転送する。そして第１のラッチ回路に保持した第１のデ−タに基づいて、ノ−ドＮ４の第２のデ−タを調整した後に、ノ−ドＮ４のデ−タを第１のラッチ回路に保持する。
【０１２３】
（５） 電気的に書き換え可能な所定数のメモリセルから構成され、消去に際してほぼ同時に選択されるメモリセルグル−プを含むメモリセルアレイと、
前記メモリセルとデ−タの授受を行うビット線と、
メモリセルの消去後の状態をセンスしその情報を保持するデ−タ回路と、
前記ビット線と電気的に接続可能な信号線（ノ−ド）と
を備える不揮発性半導体記憶装置において、
前記デ−タ回路は前記信号線の電位をセンスすることでメモリセルの状態を読み出し、
複数のメモリセルグル−プをほぼ同時に消去した後、消去が十分に行われたかを調べるベリファイリ−ドの際に、
第１のメモリセルグル−プのベリファイリ−ドを行い、信号線に読み出された第１のデ−タをデ−タ回路に保持し、
第２のメモリセルグル−プのベリファイリ−ドを行う際、前記信号線の電位を、デ−タ回路に保持する第１のデ−タに基づいて、第１のデ−タと第２のデ−タのうち少なくとも１つでも消去不十分の場合には消去不十分レベルに、第１のデ−タと第２のデ−タが共に消去十分の場合には消去十分レベルに調整することを特徴とする。
【０１２４】
例えば、図１５のＢｉｔｌｉｎｅＥに接続する第１のブロックのベリファイリ−ドを行い、読み出された第１のデ−タを図１５の第１のラッチ回路に保持する。その後、ＢｉｔｌｉｎｅＯに接続し第１のブロックとワ−ド線を共有する、第２のブロックのベリファイリ−ドを行い、読み出された第２のデ−タを図１５のノ−ドＮ４に転送する。
【０１２５】
そして、第１のラッチ回路に保持した第１のデ−タに基づいて、第１のデ−タと第２のデ−タのうち少なくとも１つでも消去不十分の場合にはノ−ドＮ４を消去不十分レベルに、第１のデ−タと第２のデ−タが共に消去十分の場合にはノ−ドＮ４を消去十分レベルに調整する。その後、ノ−ドＮ４のデ−タを第１のラッチ回路に保持する。
【０１２６】
また、次のような場合でもよい。例えば、図１５のＢｉｔｌｉｎｅＥに接続する第１のブロックのベリファイリ−ドを行い、読み出された第１のデ−タを図１５の第１のラッチ回路に保持する。その後、ＢｉｔｌｉｎｅＥに接続し第１のブロックと異なるワ−ド線に接続する、第２のブロックのベリファイリ−ドを行い、読み出された第２のデ−タを図１５のノ−ドＮ４に転送する。
【０１２７】
そして、第１のラッチ回路に保持した第１のデ−タに基づいて、第１のデ−タと第２のデ−タのうち少なくとも１つでも消去不十分の場合にはノ−ドＮ４を消去不十分レベルに、第１のデ−タと第２のデ−タが共に消去十分の場合にはノ−ドＮ４を消去十分レベルに調整する。その後、ノ−ドＮ４のデ−タを第１のラッチ回路に保持する。
【０１２８】
（６） 電気的に書き換え可能な所定数のメモリセルから構成され、消去に際してほぼ同時に選択されるメモリセルグル−プを含むメモリセルアレイと、
前記メモリセルとデ−タの授受を行うビット線と、
メモリセルの消去後の状態をセンスしその情報を保持するデ−タ回路と、
前記ビット線と電気的に接続可能な信号線（ノ−ド）と
を備える不揮発性半導体記憶装置において、
前記デ−タ回路は前記信号線の電位をセンスすることでメモリセルの状態を読み出し、
複数のメモリセルグル−プをほぼ同時に消去した後、消去が十分に行われたかを調べるベリファイリ−ドの際に、
第１のメモリセルグル−プのベリファイリ−ドを行い、信号線に読み出された第１のデ−タをデ−タ回路に保持し、
第２のメモリセルグル−プのベリファイリ−ドを行う際、前記信号線の電位を、デ−タ回路に保持する第１のデ−タに基づいて、第１のデ−タと第２のデ−タのうち少なくとも１つでも消去不十分の場合には消去不十分レベルに、第１のデ−タと第２のデ−タが共に消去十分の場合には消去十分レベルに調整し、
第ｍ（ｍは２以上ｎ以下の自然数）のメモリセルグル−プのベリファイリ−ドを行う際、信号線の電位を、デ−タ回路に保持するデ−タに基づいて、第１のデ−タ、第２のデ−タ、・・・、第ｍのデ−タのうち少なくとも１つでも消去不十分の場合には消去不十分レベルに、第１のデ−タ、第２のデ−タ、・・・、第ｍのデ−タがすべて消去十分の場合には消去十分レベルに調整し、
第ｎのメモリセルグル−プのベリファイリ−ドを行う際、前記信号線の電位を、デ−タ回路に保持するデ−タに基づいて、第１のデ−タ、第２のデ−タ、・・・、第ｎのデ−タのうち少なくとも１つでも消去（或いは書き込み）不十分の場合には消去不十分レベルに、第１のデ−タ、第２のデ−タ、・・・、第ｎのデ−タがすべて消去十分の場合には消去十分レベルに調整することを特徴とする。
【０１２９】
例えば、図１５のＢｉｔｌｉｎｅＥに接続する第１のブロックのベリファイリ−ドを行い、読み出された第１のデ−タを図１５の第１のラッチ回路に保持する。
【０１３０】
その後、ＢｉｔｌｉｎｅＯに接続し第１のブロックとワ−ド線を共有する、第１のブロックのベリファイリ−ドを行い、読み出された第２のデ−タを図１５のノ−ドＮ４に転送する。そして第１のラッチ回路に保持した第１のデ−タに基づいて、第１のデ−タと第２のデ−タのうち少なくとも１つでも消去不十分の場合にはノ−ドＮ４を消去不十分レベルに、第１のデ−タと第２のデ−タが共に消去十分の場合にはノ−ドＮ４を消去十分レベルに調整する。その後、ノ−ドＮ４のデ−タを第１のラッチ回路に保持する。
【０１３１】
次に、ＢｉｔｌｉｎｅＥに接続し第１のブロックと異なるワ−ド線に接続される、第２のブロックのベリファイリ−ドを行い、読み出された第３のデ−タを図１５のノ−ドＮ４に転送する。そして第１のラッチ回路に保持したデ−タに基づいて、第１のデ−タ、第２のデ−タ、第３のデ−タのうち少なくとも１つでも消去不十分の場合にはノ−ドＮ４を消去不十分レベルに、第１のデ−タ、第２のデ−タ、第３のデ−タが共に消去十分の場合にはノ−ドＮ４を消去十分レベルに調整する。その後、ノ−ドＮ４のデ−タを第１のラッチ回路に保持する。
【０１３２】
更に、ＢｉｔｌｉｎｅＯに接続し第２のブロックとワ−ド線を共有する、第２のブロックのベリファイリ−ドを行い、読み出された第４のデ−タを図１５のノ−ドＮ４に転送する。そして第１のラッチ回路に保持したデ−タに基づいて、第１のデ−タ、第２のデ−タ、第３のデ−タ、第４のデ−タのうち少なくとも１つでも消去不十分の場合にはノ−ドＮ４を消去不十分レベルに、第１のデ−タ、第２のデ−タ、第３のデ−タ、第４のデ−タが共に消去十分の場合にはノ−ドＮ４を消去十分レベルに調整する。その後、ノ−ドＮ４のデ−タを第１のラッチ回路に保持する。
【０１３３】
（７） 電気的に書き換え可能な所定数のメモリセルから構成され、消去に際してほぼ同時に選択されるメモリセルグル−プを含むメモリセルアレイと、
前記メモリセルとデ−タの授受を行うビット線と、
メモリセルの消去後の状態をセンスしその情報を保持するデ−タ回路と、
前記ビット線と電気的に接続可能な信号線（ノ−ド）と
を備える不揮発性半導体記憶装置において、
デ−タ回路は複数のラッチ回路を含み、
前記デ−タ回路は前記信号線の電位をセンスすることでメモリセルの状態を読み出し、
複数のメモリセルグル−プをほぼ同時に消去した後、消去が十分に行われたかを調べるベリファイリ−ドの際に、
第１のメモリセルグル−プのベリファイリ−ドを行い、信号線に読み出された第１のデ−タをデ−タ回路内の第１のラッチ回路に保持し、
第２のメモリセルグル−プのベリファイリ−ドを行い、第２のデ−タが読み出された信号線の電位を、デ−タ回路内の第２のラッチ回路に保持することを特徴とする。例えば図２３、図２４であればよい。図２３、図２４中、スイッチ回路があってもよいしなくても良い。スイッチ回路がない場合にはビット線と信号線は同電位になる。スイッチ回路がある場合でも、信号線の電位を調整する際にスイッチ回路を導通状態にしてもよい。
【０１３４】
（８） 電気的に書き換え可能な所定数のメモリセルから構成され、消去に際してほぼ同時に選択されるメモリセルグル−プを含むメモリセルアレイと、
前記メモリセルとデ−タの授受を行うビット線と、
メモリセルの消去後の状態をセンスしその情報を保持するデ−タ回路と、
前記ビット線と電気的に接続可能な信号線（ノ−ド）と
を備える不揮発性半導体記憶装置において、
デ−タ回路は複数のラッチ回路を含み、
前記デ−タ回路は前記信号線の電位をセンスすることでメモリセルの状態を読み出し、
複数のメモリセルグル−プをほぼ同時に消去した後、消去が十分に行われたかを調べるベリファイリ−ドの際に、
第１のメモリセルグル−プのベリファイリ−ドを行い、信号線に読み出された第１のデ−タをデ−タ回路内の第１のラッチ回路に保持し、
第２のメモリセルグル−プのベリファイリ−ドを行い、第２のデ−タが読み出された信号線の電位を、デ−タ回路内の第２のラッチ回路に保持し、
かつ前記複数のメモリセルグル−プ中には、他のメモリセルグル−プ中のメモリセルと互いにワ−ド線が異なり、かつ同じビット線に接続するメモリセルを含むことを特徴とする。
【０１３５】
従って、例えば、図２４のようであればよい。もちろん、図２４でスイッチ回路がなくてもよい。また、例えば、図１５のＢｉｔｌｉｎｅＥに接続する第１のブロックのベリファイリ−ドを行い、読み出された第１のデ−タを図１５の第１のラッチ回路に保持する。その後、ＢｉｔｌｉｎｅＥに接続し第１のブロックと異なるワ−ド線に接続する、第２のブロックのベリファイリ−ドを行い、読み出された第２のデ−タを図１５の第２のラッチ回路に保持する。そして第１のラッチ回路に保持した第１のデ−タと、第２のラッチ回路に保持した第２のデ−タをＩＯ線を通じて出力する。
【０１３６】
（９） 電気的に書き換え可能な所定数のメモリセルから構成され、消去に際してほぼ同時に選択されるメモリセルグル−プを含むメモリセルアレイと、
前記メモリセルとデ−タの授受を行うビット線と、
メモリセルの消去後の状態をセンスしその情報を保持するデ−タ回路と、
前記ビット線と電気的に接続可能な信号線（ノ−ド）と
を備える不揮発性半導体記憶装置において、
デ−タ回路は複数のラッチ回路を含み、
前記デ−タ回路は前記信号線の電位をセンスすることでメモリセルの状態を読み出し、
複数のメモリセルグル−プをほぼ同時に消去した後、消去が十分に行われたかを調べるベリファイリ−ドの際に、
第１のメモリセルグル−プのベリファイリ−ドを行い、信号線に読み出された第１のデ−タをデ−タ回路内の第１のラッチ回路に保持し、
第２のメモリセルグル−プのベリファイリ−ドを行い、第２のデ−タが読み出された信号線の電位を、デ−タ回路内の第２のラッチ回路に保持し、
かつ前記複数のメモリセルグル−プ中には、他のメモリセルグル−プ中のメモリセルとワ−ド線を共有し、かつ異なるビット線に接続するメモリセルを含むことを特徴とする。
【０１３７】
従って、例えば、図２３のようであればよい。もちろん、図２３でスイッチ回路がなくてもよい。また例えば、図１５のＢｉｔｌｉｎｅＥに接続する第１のブロックのベリファイリ−ドを行い、読み出された第１のデ−タを図１５の第１のラッチ回路に保持する。その後、ＢｉｔｌｉｎｅＯに接続し第１のブロックとワ−ド線を共有する、第２のブロックのベリファイリ−ドを行い、読み出された第２のデ−タを図１５の第２のラッチ回路に保持する。そして第１のラッチ回路に保持した第１のデ−タと、第２のラッチ回路に保持した第２のデ−タをＩ／Ｏ線を通じて出力する。
【０１３８】
（１０） 電気的に書き換え可能な所定数のメモリセルから構成され、消去に際してほぼ同時に選択されるメモリセルグル−プを含むメモリセルアレイと、
前記メモリセルとデ−タの授受を行うビット線と、
メモリセルの消去後の状態をセンスしその情報を保持するデ−タ回路と、
前記ビット線と電気的に接続可能な信号線（ノ−ド）と
を備える不揮発性半導体記憶装置において、
デ−タ回路は複数のラッチ回路を含み、
前記デ−タ回路は前記信号線の電位をセンスすることでメモリセルの状態を読み出し、
複数のメモリセルグル−プをほぼ同時に消去した後、消去が十分に行われたかを調べるベリファイリ−ドの際に、
第１のメモリセルグル−プのベリファイリ−ドを行い、信号線に読み出された第１のデ−タをデ−タ回路内の第１のラッチ回路に保持し、
第２のメモリセルグル−プのベリファイリ−ドを行い、第２のデ−タが読み出された信号線の電位を、デ−タ回路内の第２のラッチ回路に保持し、
第ｍ（ｍは２以上の自然数）のメモリセルグル−プのベリファイリ−ドを行い、第ｍのデ−タが読み出された信号線の電位を、デ−タ回路内の第ｍのラッチ回路に保持することを特徴とする。
【０１３９】
（１１） それぞれの前記デ−タ回路は、消去したすべてのメモリセルが充分に消去されていることを一括して検知する一括検知回路を有することを特徴とする。この一括検知回路は例えば図１５のトランジスタＱＮＬ９であればよい。
【０１４０】
（１２） また前記メモリセルグル−プは例えば図３６のようなブロック構成であればよい。
【０１４１】
［実施例４］
上記実施例では、多値ＮＡＮＤ型ＥＥＰＲＯＭを例にとって説明を行ったが、本発明が適用できるのはこれに限らない。つまり、２値フラッシュメモリも、多値フラッシュメモリとほぼ同様に消去を行うので、本発明は無論２値フラッシュメモリにも適用できる。
【０１４２】
ここでは、２ビット線を１つのデ−タ回路で共有する図２８のようなオ−プンビット線方式のセルアレイを例にとり説明する。なお、読み出し、書き込み動作の詳細は、公知例 Ｔ．Ｔａｎａｋａ ｅｔ．ａｌ．；ＩＥＥＥ Ｊｏｕｒｎａｌ ｏｆ Ｓｏｌｉｄ−Ｓｔａｔｅ Ｃｉｒｃｕｉｔｓ ｖｏｌ．２９，Ｎｏ．１１，ｐｐ．１３６６−１３７３，Ｎｏｖｅｍｂｅｒ １９９４ に記されている。
【０１４３】
以下では、図２８のＣＧ１からＣＧ８で選択されるブロックが消去された後のベリファイリ−ドを図２９のタイミング図を用いて説明する。
【０１４４】
ベリファイリ−ドは、まず、第１のブロックの偶数ペ−ジ（例えば図２８のビット線ＢＬａｉに接続するメモリセル）について行いラッチ回路に読み出しデ−タを保持する。次に奇数ペ−ジ（例えば図２８のビット線ＢＬａｉ＋１に接続するメモリセル）について行いラッチ回路に読み出しデ−タを保持する。
【０１４５】
まず、ビット線ＢＬａｉを１．８Ｖに、ＢＬｂｉを１．５Ｖにプリチャ−ジした後に、時刻ｔ１ｙに選択ゲ−ト線ＳＧ１、ＳＧ２をＶｃｃ、ワ−ド線ＣＧ１〜ＣＧ８は０Ｖにすると、メモリセルが消去十分の場合には、ビット線はダミ−ビット線電位１．５Ｖよりも低くなり、消去不十分の場合には１．８Ｖを保つ。時刻ｔ２ｙにφ１がＶｃｃになり、ビット線およびダミ−ビット線の電位がデ−タ回路内に転送される。その後、φａが“Ｈｉｇｈ”になることにより、デ−タが転送され、センスされる。このように偶数ペ−ジのデ−タはラッチ回路に保持される。
【０１４６】
偶数ペ−ジの読み出し中は、ビット線間容量結合ノイズを低減するためにビット線ＢＬａｉ＋１、ＢＬｂｉ＋１は０Ｖに保たれる。以上のベリファイリ−ドの結果、消去不十分の場合にはノ−ドＮ１は“Ｈｉｇｈ゛、消去十分の場合にはノ−ドＮ１は“Ｌｏｗ”になる。
【０１４７】
続いて、奇数ペ−ジ（例えば図２８のビット線ＢＬａｉ＋１に接続するメモリセル）についてベリファイリ−ドを行う。ビット線ＢＬａｉ＋１を１．８Ｖに、ダミ−ビット線ＢＬｂｉ＋１を１．５Ｖにプリチャ−ジした後に、時刻ｔ５ｙに選択ゲ−ト線ＳＧ１、ＳＧ２をＶｃｃ、ワ−ド線ＣＧ１〜ＣＧ８は０Ｖにすると、メモリセルが消去十分の場合には、ビット線はダミ−ビット線の電位１．５Ｖ以下になり、消去不十分の場合には１．８Ｖを保つ。時刻ｔ６ｙにφ２がＶｃｃになり、ビット線の電位がデ−タ回路内に転送される。その後、時刻ｔ ７ｙにφＡＶが“Ｈｉｇｈ”になる。
【０１４８】
偶数ペ−ジを読み出した結果、消去十分の場合は、ノ−ドＮ１は“Ｌｏｗ”がラッチされているので、ｎチャネルトランジスタＱＮＳはオフし、ノ−ドＮ４の電位を変化しない。つまり、奇数ペ−ジが消去不十分ならばノ−ドＮ４は“Ｈｉｇｈ”、消去十分ならばノ−ドＮ４は“Ｌｏｗ”になる。
【０１４９】
一方、偶数ペ−ジを読み出した結果、消去不十分の場合は、ノ−ドＮ１は“Ｈｉｇｈ”がラッチされているので、ｎチャネルトランジスタＱＮＳはオンし、ノ−ドＮ４の電位は奇数ペ−ジのデ−タによらず“Ｈｉｇｈ”になる。
【０１５０】
その後、φａ、φｂが“Ｈｉｇｈ”になることにより、デ−タが転送されセンスされる。奇数ペ−ジの読み出し中は、ビット線間容量結合ノイズを低減するために、ビット線Ｂｌａｉ、Ｂｌｂ２は０Ｖに保たれる。
【０１５１】
以上のベリファイリ−ド動作の結果、偶数ペ−ジと奇数ペ−ジのうち、１つでも消去不十分のセルがあると、Ｎ１は“Ｈｉｇｈ”になる。偶数ペ−ジと奇数ペ−ジが共に消去十分の場合に限り、Ｎ１は“Ｌｏｗ”になる。
【０１５２】
消去終了の検出はラッチ回路のデ−タを図２９のようにＩＯＡ、ＩＯＢに出力する他に、例えば図２８のように消去終了一括検知トランジスタＱＮＮを用いて一括検知してもよい。上記のように偶数ペ−ジ及び奇数ペ−ジのデ−タ又は実施例２のように第１のブロックから第ｎのブロックまでのデ−タを第１のラッチ回路に読み出した後に、まず、ＶＲＴを例えばＶｃｃにプリチャ−ジする。
【０１５３】
消去が不十分なメモリセルが存在するカラムでは、ノ−ドＮ１は“Ｈｉｇｈ”になり、ｎチャネルＭＯＳトランジスタＱＮＮがオンしＶＲＴはプリチャ−ジ電位から低下する。選択したすべてのメモリセルが十分に消去される場合に限り、すべてのカラムでノ−ドＮ１は“Ｌｏｗ”になる。その結果、全てのデ−タ回路内のｎチャネルＭＯＳトランジスタＱＮＮがオフになるので、ＶＲＴはプリチャ−ジ電位を保ち、消去終了が検知される。
【０１５４】
また、本発明が適用できるのは、図３のＮＡＮＤ型ＥＥＰＲＯＭのみならず、図１９のようなＮＯＲ型Ｆｌａｓｈメモリ−、図１８のようなＡＮＤ型（Ｋ．Ｋｕｍｅ ｅｔ ａｌ．；ＩＥＤＭ Ｔｅｃｈ．Ｄｉｇ．，Ｄｅｃ．１９９２，ｐｐ．９９１−９９３） や、図１７のようなＤＩＮＯＲ型（Ｓ．Ｋｏｂａｙａｓｈｉ ｅｔａｌ．；ＩＳＳＣＣ Ｔｅｃｈ．Ｄｉｇ．，１９９５，ｐｐ．１２２） 、図１６のような仮想グランドアレイ型（Ｒ．Ｃｅｍｅａ ｅｔ ａｌ．；ＩＳＳＣＣ Ｔｅｃｈ．Ｄｉｇ．，１９９５，ｐｐ．１２６） でもよい。また、マスクＲＯＭでももちろん良い。
【０１５５】
また、本発明が適用できるのは、３値メモリセルあるいは４値メモリセルに限らず、もちろん５値メモリセルあるいは８値メモリセル或いは１６値メモリセルなどでも有効である。
【０１５６】
［実施例５］
更に本発明は図３０のようなセンスアンプでも適用可能である。書き込み、読み出し方法は ＩＥＥＥ Ｊｏｕｒｎａｌ ｏｆ Ｓｏｌｉｄ−Ｓｔａｔｅ Ｃｉｒｃｕｉｔｓ ｖｏｌ．３０，ｎｏ．１１，ｐｐ．１１５７−１１６４，Ｎｏｖｅｍｂｅｒ １９９５ に詳細が記されている。消去ベリファイリ−ドのタイミング図は図３１である。
【０１５７】
ベリファイリ−ドは、まず、偶数ペ−ジ（例えば図３０のビット線ＢＬａｉに接続するメモリセル）について行い、ラッチ回路に読み出しデ−タを保持する。次に奇数ペ−ジ（例えば図３０のビット線ＢＬａｉ＋１に接続するメモリセル）について行い、ラッチ回路に読み出しデ−タを保持する。
【０１５８】
まず、Ｒｅｓｅｔを“Ｈｉｇｈ”にすることによりノ−ドＮ１を“Ｌｏｗ”に、ノ−ドＮ２を“Ｈｉｇｈ”に設定する。続いてビット線ＢＬａｉを２Ｖにプリチャ−ジした後に、時刻ｔ１ｓに選択ゲ−ト線ＳＧ１、ＳＧ２をＶｃｃ、ワ−ド線ＣＧ１〜ＣＧ８は０Ｖにすると、メモリセルが消去十分の場合には、ビット線は０Ｖになり、消去不十分の場合には２Ｖを保つ。時刻ｔ２Ｓにφ１がＶｃｃになり、ビット線およびダミ−ビット線の電位がデ−タ回路内に転送される。その後、Ｒｅａｄが“Ｈｉｇｈ”になることによりセンスされる。
【０１５９】
つまり、消去不十分の場合には、ｎチャネルトランジスタＱ ｒｅａｄ はオンしてノ−ドＮ２は“Ｌｏｗ”、ノ−ドＮ１は“Ｈｉｇｈ”になる。消去十分の場合にはｎチャネルトランジスタＱ ｒｅａｄ はオフしてノ−ドＮ２は“Ｈｉｇｈ”を保たれる。このように偶数ペ−ジのデ−タはラッチ回路に保持される。偶数ペ−ジの読み出し中は、ビット線間容量結合ノイズを低減するためにビット線ＢＬａｉ＋１は０Ｖに保たれる。
【０１６０】
続いて、奇数ペ−ジ（例えば図３０のビット線ＢＬａｉ＋１に接続するメモリセル）についてベリファイリ−ドを行う。ビット線ＢＬａｉ＋１を２Ｖにプリチャ−ジした後に、時刻ｔ５ｓに選択ゲ−ト線ＳＧ１、ＳＧ２をＶｃｃ、ワ−ド線ＣＧ１〜ＣＧ８は０Ｖにすると、メモリセルが消去十分の場合には、ビット線は０Ｖになり、消去不十分の場合には２Ｖを保つ。時刻ｔ６ｓにφ２がＶｃｃになり、ビット線の電位がデ−タ回路内に転送される。その後、Ｒｅａｄが“Ｈｉｇｈ”になることによりセンスされる。
【０１６１】
つまり、消去不十分の場合には、ｎチャネルトランジスタＱ ｒｅａｄ はオンしてノ−ドＮ２は“Ｌｏｗ”、ノ一ドＮ１は“Ｈｉｇｈ”になる。消去十分の場合には、ｎチャネルトランジスタＱ ｒｅａｄ はオフしてノ−ドＮ２は“Ｈｉｇｈ”に保たれる。奇数ペ−ジの読み出し中は、ビット線間容量結合ノイズを低減するために、ビット線ＢＬａｉは０Ｖに保たれる。
【０１６２】
以上のベリファイリ−ド動作の結果、偶数ペ−ジと奇数ペ−ジのうち、１つでも消去不十分のセルがあると、Ｎ１は“Ｈｉｇｈ”、Ｎ２は“Ｌｏｗ”になる。偶数ペ−ジと奇数ペ−ジが共に消去十分の場合に限り、Ｎ１は“Ｌｏｗ”、Ｎ２は“Ｈｉｇｈ”になる。
【０１６３】
消去終了の検出はラッチ回路のデ−タをＩ／Ｏ線に出力する他に、例えば図３０のように消去終了一括検知トランジスタＱＳＮを用いて一括検知してもよい。上記のように偶数ペ−ジ及び奇数ペ−ジのデ−タを第１のラッチ回路に読み出した後に、まずＶＲＴを例えばＶｃｃにプリチャ−ジする。消去が不十分なメモリセルが存在するカラムではノ−ドＮ１は“Ｈｉｇｈ”になり、ｎチャネルＭＯＳトランジスタＱＳＮがオンしＶＲＴはプリチャ−ジ電位から低下する。選択したすべてのメモリセルが十分に消去される場合に限り、すべてのカラムでノ−ドＮ１は“Ｌｏｗ”になる。その結果、全てのデ−タ回路内のｎチャネルＭＯＳトランジスタＱＳＮがオフになるので、ＶＲＴはプリチャ−ジ電位を保ち、消去終了が検知される。
【０１６４】
【発明の効果】
以上、説明したように、本発明の不揮発性半導体記憶装置によれば、次のような効果を奏する。
【０１６５】
すなわち、複数のビット線で１つのセンスアンプを共有するメモリセルアレイにおいて、消去時に複数のビット線に接続するメモリセルはほぼ同時に消去が行われ、消去後、それぞれのビット線に接続するメモリセルに対して消去ベリファイリ−ドを行うが、この消去ベリファイリ−ドの時間を大幅に短縮することができる。また、多値メモリについて、周辺回路の面積増加を防ぐため、複数のビット線で１個のデ−タ回路を共有する場合においても、消去ベリファイリ−ドの時間を長くすることがない。
【図面の簡単な説明】
【図１】本発明の実施の形態に関わる半導体記憶装置を示すブロック図。
【図２】カラム系回路の構成の一例を示す図。
【図３】ＮＡＮＤセルの構成を示す図。
【図４】ロウデコ−ダの構成の一例を示す図。
【図５】ロウデコ−ダの構成の一例を示す図。
【図６】デ−タの読み出し動作を示す波形図。
【図７】デ−タの書き込み動作を示す波形図。
【図８】デ−タの消去動作を示す波形図。
【図９】消去ベリファイリ−ド動作を示す波形図。
【図１０】消去ベリファイリ−ド動作を示すフロ−チャ−ト。
【図１１】消去ベリファイリ−ド動作を示すフロ−チャ−ト。
【図１２】消去ベリファイリ−ド動作を示すフロ−チャ−ト。
【図１３】消去ベリファイリ−ド動作を示す波形図。
【図１４】消去ベリファイリ−ド動作を示すフロ−チャ−ト。
【図１５】カラム系回路の構成の一例を示す図。
【図１６】グランドアレイ型セルの構成を示す図。
【図１７】ＤＩＮＯＲセルの構成を示す図。
【図１８】ＡＮＤセルの構成を示す図。
【図１９】ＮＯＲセルの構成を示す図。
【図２０】本発明の第１の構成を示す図。
【図２１】本発明の第２の構成を示す図。
【図２２】本発明の第３の構成を示す図。
【図２３】本発明の第４の構成を示す図。
【図２４】本発明の第５の構成を示す図。
【図２５】カラム系回路の構成の一例を示す図。
【図２６】本発明の第６の構成を示す図。
【図２７】本発明の第７の構成を示す図。
【図２８】カラム系回路の構成の一例を示す図。
【図２９】消去ベリファイリ−ド動作を示す波形図。
【図３０】カラム系回路の構成の一例を示す図。
【図３１】消去ベリファイリ−ド動作を示す波形図。
【図３２】ＮＡＮＤセル型ＥＥＰＲＯＭのメモリセルアレイの１単位を示す図。
【図３３】図３２のＸＸＸＩＩＩ−ＸＸＸＩＩＩ線に沿う断面図。
【図３４】図３２のＸＸＸＩＶ−ＸＸＸＩＶ線に沿う断面図。
【図３５】図３２のデバイスの等価回路を示す図。
【図３６】ＮＡＮＤセル型ＥＥＰＲＯＭのメモリセルアレイの等価回路を示す図。
【符号の説明】
１ ：半導体記憶装置（チップ）、
２ ：メモリセルアレイ、
３ ：ロウデコ−ダ、
４ ：センスアンプ兼ラッチ回路、
５ ：ワ−ド／ビット線制御信号発生回路、
６ ：ウエル電位制御回路、
７ ：アドレスバッファ、
８ ：Ｉ／Ｏバッファ、
９ ：コマンドバッファ、
１０ ：カラムデコ−ダ、
１１ ：ｐ型シリコン基板、
１２ ：フィ−ルド酸化膜、
１３ ：ゲ−ト酸化膜、
１４ ：浮遊ゲ−ト電極、
１５ ：絶縁膜、
１６ ：制御ゲ−ト電極、
１７ ：層間絶縁膜、
１８ ：ビット線、
１９ ：ｎ型拡散層、
２０ ：ソ−ス線、
２１ ：基準電位配線、
２２ ：プリチャ−ジ回路、
Ｉ１〜Ｉ５ ：インバ−タ、
ＱＰ１〜ＱＰ３ ：ＰチャネルＭＯＳトランジスタ、
ＱＮＬ１〜ＱＮＬ６ ：ＮチャネルＭＯＳトランジスタ、
ＱＮＨ１〜ＱＮＨ６ ：ＮチャネルＭＯＳトランジスタ、
Ｇ１ ：ＮＡＮＤ回路、
ＢＬ ：ビット線、
Ｍ１〜Ｍ８ ：メモリセル、
Ｓ１，Ｓ２ ：選択ゲ−トトランジスタ。[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an electrically rewritable nonvolatile semiconductor memory device (EEPROM).
[0002]
[Prior art]
In recent years, a NAND cell type EEPROM has been proposed as one of electrically rewritable nonvolatile semiconductor memory devices (EEPROM).
[0003]
In this EEPROM, a plurality of memory cells having an n-channel FET MOS structure in which, for example, a floating gate and a control gate are stacked as a charge storage layer are shared between adjacent ones with the source and drain thereof. Are connected in series, and this is connected as a unit to the bit line.
[0004]
FIG. 32 is a plan view of one NAND cell portion of the memory cell array. FIG. 33 is a sectional view taken along the line XXXIII-XXXIII of FIG. 32, and FIG. 34 is a sectional view taken along the line XXXIV-XXXIV of FIG.
[0005]
A memory cell array including a plurality of NAND cells is formed on a p-type silicon substrate (or p-type well) 11 surrounded by an element isolation oxide film 12. Describing focusing on one NAND cell, in this embodiment, eight memory cells M1 to M8 are connected in series to form one NAND cell. Each of the memory cells is formed by forming a floating gate 14 on a substrate 11 via a gate insulating film 13. The memory cells are connected in series so that adjacent ones of the n-type diffusion layers 19 which are the source and drain of these memory cells are shared.
[0006]
On the drain side and the source side of the NAND cell, respectively, a first selection gate 14, 16 and a second selection gate 14 formed simultaneously with the floating gate and the control gate of the memory cell. , 16 are provided. The substrate on which the elements are formed is covered with a CVD oxide film 17, on which bit lines 18 are provided. The control gates 14 of the NAND cells are commonly provided as control gate lines CG1, CG2,... CG8. These control gate lines CG1, CG2,... CG8 are word lines. The selection gates 14 and 16 are also continuously provided as selection gate lines SG1 and SG2 in the row direction, respectively.
[0007]
FIG. 35 shows an equivalent circuit diagram of such a NAND cell, and FIG. 36 shows an equivalent circuit of a memory cell array in which NAND cells are arranged in a matrix.
[0008]
The source line is connected to a reference potential wiring such as Al or poly-Si via a contact, for example, at one place for every 64 bit lines. This reference potential wiring is connected to a peripheral circuit. The control gate and the first and second selection gates of the memory cell are arranged continuously in the row direction.
[0009]
Normally, a set of memory cells connected to the control gate is called one page, and one set of a drain side (first selection gate) and a source side (second selection gate) is selected. A set of pages sandwiched by gates is called one NAND block or simply one block. One page is composed of, for example, 256 bytes (256 × 8) memory cells. Data is written to memory cells of one page almost simultaneously. One block is composed of, for example, 2048 bytes (2048 × 8) memory cells. Memory cells for one block are erased almost simultaneously.
[0010]
The operation of the NAND type EEPROM is as follows.
[0011]
Data writing is performed sequentially from the memory cell farthest from the bit line. The boosted write voltage Vpp (= about 20 V) is applied to the control gate of the selected memory cell, and the intermediate potential is applied to the control gate of the other unselected memory cells and the first selected gate. (= About 10 V), and 0 V ("0" write) or an intermediate potential ("1" write) is applied to the bit line according to the data.
[0012]
At this time, the potential of the bit line is transmitted to the selected memory cell. When the data is "0", a high voltage is applied between the floating gate of the selected memory cell and the substrate, electrons are tunnel-injected from the substrate to the floating gate, and the threshold voltage moves in the positive direction. . When the data is "1", the threshold voltage does not change.
[0013]
Data erasure is performed almost simultaneously in block units. That is, all control gates and selection gates of the block to be erased are set to 0 V, and a boosted potential VppE (about 20 V) is applied to the p-type well and the n-type substrate. VppE is also applied to the control gate and the select gate of the block that is not erased. As a result, floating gate electrons are emitted to the wells in the memory cells of the block to be erased, and the threshold voltage shifts in the negative direction.
[0014]
In the data read operation, the bit line is precharged and then floated, the control gate of the selected memory cell is set to 0 V, and the control gates of the other memory cells and the selected gate are powered. The operation is performed by setting the voltage Vcc (for example, 3 V) and the source line to 0 V, and detecting whether or not a current flows in the selected memory cell on the bit line.
[0015]
That is, if the data written in the memory cell is "0" (threshold Vth> 0 of the memory cell), the memory cell is turned off, and the bit line maintains the precharge potential, but "1". If (threshold Vth <0 of the memory cell), the memory cell is turned on and the bit line drops by .DELTA.V from the precharge potential. By detecting these bit line potentials with a sense amplifier (data circuit), the data of the memory cell is read.
[0016]
Here, a case where one sense amplifier is shared by a plurality of bit lines in a NAND type EEPROM is considered. In the erase operation, cells connected to the bit line sharing the sense amplifier are erased almost simultaneously. Conventionally, after erasing, erase verify read and detection of the result are performed for each bit line sharing the sense amplifier. For example, when two bit lines share one sense amplifier, the data is doubled. Erase verify read time is required.
[0017]
[Problems to be solved by the invention]
Recently, as one of the techniques for increasing the capacity of an EEPROM, a multi-value storage cell in which three or more values of information are stored in one cell is also known (for example, Japanese Patent Application Laid-Open No. Hei 7-93979, Hei 5-311732).
[0018]
In an EEPROM, a data circuit for holding write data and read data is generally composed of a latch circuit. However, in order to hold multi-valued write data or read data, it is necessary to use a latch circuit. The data circuit requires two or more latch circuits (for example, JP-A-7-93979 and Japanese Patent Application No. 5-311732).
[0019]
Therefore, in order to prevent an increase in the area of the peripheral circuit even when the memory cell is multi-valued, it is necessary that a single data circuit shares a plurality of bit lines (for example, IEEE Journal of Solid-State Circuits vol. 29, No. 11, pp. 1366-1373, Noevber 1994).
[0020]
Here, for example, when one data circuit is shared by two bit lines, the steps from the erase verify read to the detection of the result are connected to the respective bit lines as in the related art. As described above, there is a problem that the time for verify reading is twice as long as the case where the data circuit is not shared, as described above.
[0021]
[Means for Solving the Problems]
In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention comprises a first and a second memory cell group comprising a predetermined number of electrically rewritable memory cells and simultaneously selected at the time of erasing. A memory cell array, a node connected to a first bit line connected to the first memory cell group and a second bit line connected to the second memory cell group, and an erase verify relay A data circuit for storing data corresponding to the information read from the first memory cell group and the information read from the second memory cell group at the time of reading. The first data read to the data circuit via the node by the erase verify read for the first memory cell group and the second memory cell group. -Erase verify By taking the logic of the second data read out to the node by a read operation, if both the first and second data are sufficiently erased, the data is sent to the data circuit. Data indicating erasure completion is held, and when at least one of the first and second data is insufficiently erased, data indicating erasure re-execution is held in the data circuit. It is characterized by being performed.
[0022]
The memory cells forming the first memory cell group and the memory cells forming the second memory cell group share a word line with each other.
[0023]
A plurality of data circuits are provided in the word line direction, and a collective detection circuit for detecting collectively that all the memory cells selected for these data circuits have been sufficiently erased. It is attached.
[0024]
A nonvolatile semiconductor memory device according to the present invention includes a memory cell array including a predetermined number of electrically rewritable memory cells and having first and second memory cell groups selected at the time of erasing; And a node connected to a second bit line connected to the second memory cell group, and a node connected to a second bit line connected to the second memory cell group. At this time, after the first data read from the first memory cell group is held in the data circuit, the data is read from the first data and the second memory cell group. The potential of the node is set based on the second data to be obtained.
[0025]
The memory cells forming the first memory cell group and the memory cells forming the second memory cell group share a word line with each other.
[0026]
A nonvolatile semiconductor memory device according to the present invention includes a memory cell array including a predetermined number of electrically rewritable memory cells and having first and second memory cell groups selected at the time of erasing; And a bit line connected to the second memory cell group, and a node connected to the bit line, wherein the first memory cell group is used for erase verify reading. After the first data read from the memory cell is held in the data circuit, the data is read based on the first data and the second data read from the second memory cell group. The method is characterized in that the potential of the node is set.
[0027]
The memory cells forming the first memory cell group and the memory cells forming the second memory cell group are connected to different word lines.
[0028]
A nonvolatile semiconductor memory device according to the present invention includes a memory cell array including a predetermined number of electrically rewritable memory cells and having a plurality of memory cell groups selected at the time of erasing, and the plurality of memory cell groups. And a node connected to a bit line connected to the memory cell group, and verifying whether the erasure has been performed sufficiently after erasing the plurality of memory cell groups substantially simultaneously. At this time, the verify read of the first memory cell group is performed, the first data read to the node is held in the data circuit, and the second memory cell group is read. When verify reading of a group is performed, if at least one of the first data and the second data read from the second memory cell group is insufficiently erased, Reduce the node to an insufficiently erasable level, Serial first de - data and the second de - when data is erased enough together, the Roh - and adjusting de to erase sufficient level.
[0029]
A nonvolatile semiconductor memory device according to the present invention includes a memory cell array including a predetermined number of electrically rewritable memory cells and having a plurality of memory cell groups selected at the time of erasing, and the plurality of memory cell groups. And a node connected to a bit line connected to the memory cell group, and verifying whether the erasure has been performed sufficiently after erasing the plurality of memory cell groups substantially simultaneously. At this time, the verify read of the first memory cell group is performed, the first data read to the node is held in the data circuit, and the second memory cell group is read. When verify reading of a group is performed, if at least one of the first data and the second data read from the second memory cell group is insufficiently erased, Reduce the node to an insufficiently erasable level, If both the first data and the second data are sufficiently erased, the node is adjusted to a sufficiently erased level and the m-th (m is a natural number not less than 2 and not more than n) m-th data is adjusted. When verify reading of the memory cell group is performed, if at least one of the first data, the second data,..., The m-th data is insufficiently erased, When the first data, the second data,..., And the m-th data are all sufficiently erased, the node is set to an insufficiently erased level. When verifying the n-th memory cell group by adjusting the erase level to a sufficient level, the first data, the second data,..., The n-th data If at least one of the nodes is insufficiently erased, the node is set to an insufficiently erased level, and the first data, the second data,... In the case of - and adjusting the erase sufficient level mode.
[0030]
The memory cells forming the plurality of memory cell groups are connected to different word lines.
[0031]
A nonvolatile semiconductor memory device according to the present invention includes a memory cell array including a predetermined number of electrically rewritable memory cells and having first and second memory cell groups selected at the time of erasing; And a node connected to a first bit line connected to the second memory cell group and a second bit line connected to the second memory cell group. A first latch circuit for holding information read from one memory cell group and a data circuit having a second latch circuit for holding information read from the second memory cell group; It is characterized by having.
[0032]
The memory cells forming the first memory cell group and the memory cells forming the second memory cell group share a word line with each other.
[0033]
A plurality of data circuits are provided in the word line direction, and a collective detection circuit for detecting collectively that all the memory cells selected for these data circuits have been sufficiently erased. It is attached.
[0034]
A nonvolatile semiconductor memory device according to the present invention includes a memory cell array including a predetermined number of electrically rewritable memory cells and having first and second memory cell groups selected at the time of erasing; A bit line connected to the second memory cell group, a node connected to the bit line, and information read from the first memory cell group at the time of erase verify read. A data circuit having a first latch circuit for holding and a second latch circuit for holding information read from the second memory cell group.
[0035]
The memory cells forming the first memory cell group and the memory cells forming the second memory cell group are connected to different word lines.
[0036]
A plurality of data circuits are provided in the word line direction, and a collective detection circuit for detecting collectively that all the memory cells selected for these data circuits have been sufficiently erased. It is attached.
[0037]
A nonvolatile semiconductor memory device according to the present invention includes a memory cell array including a plurality of memory cells that are electrically rewritable and has a plurality of memory cell groups selected at the time of erasing. A node connected to a connected bit line and a first, second,..., M-th (m is a natural number) memory cell of the plurality of memory cell groups during erase verify read. A data circuit having m latch circuits for holding each information read from the group.
[0038]
The memory cells constituting each memory cell group share a word line with each other.
[0039]
A plurality of data circuits are provided in the word line direction, and a collective detection circuit for detecting collectively that all the memory cells selected for these data circuits have been sufficiently erased. It is attached.
[0040]
A nonvolatile semiconductor memory device according to the present invention includes a memory cell array including a predetermined number of electrically rewritable memory cells and having a plurality of memory cell groups selected at the time of erasing, and the plurality of memory cell groups. , A node connected to the bit line, a node connected to the bit line, and the first, second,... (where m is a natural number) a data circuit having m latch circuits for holding each information read from the memory cell group.
[0041]
The memory cells constituting each memory cell group are connected to different word lines.
[0042]
A plurality of data circuits are provided in the word line direction, and a collective detection circuit for detecting collectively that all the memory cells selected for these data circuits have been sufficiently erased. It is attached.
[0043]
BEST MODE FOR CARRYING OUT THE INVENTION
[Example 1]
Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.
[0044]
FIG. 1 is a block diagram showing a configuration of a semiconductor memory device according to one embodiment of the present invention.
[0045]
This semiconductor memory device 1 has a memory cell array 2 in which memory cells selected by word lines and bit lines are arranged in a matrix, and a row decoupling circuit for selecting a word line and applying a predetermined voltage to the memory cell. A sense amplifier for sensing a bit line voltage corresponding to data when reading data from a memory cell and outputting a voltage corresponding to write data to the bit line when writing data to the memory cell; A latch circuit 4, a word line / bit line control signal generating circuit 5 for providing control signals to word lines and bit lines, and selectively connected to the sense amplifier / latch circuit 4 when writing data to a memory cell. A precharge circuit 22 for outputting a voltage which does not change the data of a memory cell to a bit line which is not changed, and a semiconductor memory for input data to be written to the memory cell and output data to be read from the memory cell. An I / O buffer 8 for exchanging with the outside of the device 1, a column decoder 10 for selecting the sense amplifier / latch circuit 4 and connecting to the I / O line, a command buffer 9 for generating commands such as writing and reading, an input address or It comprises an address buffer 7 for generating a column address and a row address in response to an input test command.
[0046]
In a semiconductor memory device which needs to apply a voltage to a well of a memory cell by operation, a cell well potential control circuit 6 is further provided.
[0047]
FIG. 2 is a circuit diagram showing a column decoder 10, a sense amplifier / latch circuit 4, a precharge circuit 12, and a connection relationship between a bit line and an I / O line in the semiconductor memory device of the present embodiment. . In the present embodiment, a nonvolatile semiconductor memory device using a ternary NAND flash memory cell is used.
[0048]
FIGS. 3, 16, 17, 18, and 19 show configurations of various memory cell units (FIG. 3 shows NAND cell units), and FIGS. 4 and 5 show configurations of row decoders.
[0049]
The ternary sense amplifier / latch circuit 4 comprises a binary sense amplifier / latch circuit composed of inverters I1 and I2 and a binary sense amplifier / latch circuit composed of inverters I3 and I4. Have been. The precharge circuit 22 is connected to each bit line one by one. One ternary sense amplifier / latch circuit 4 is selectively connected to two bit lines BitlineE and BitlineO by switches QNH3 and QNH4. Further, the ternary sense amplifier and latch circuit 4 is connected to an I / O line by a column decoder 10. The ternary data "0 to 2" of the memory cell and its threshold voltage, and the latch data N1 and N2 of the ternary sense amplifier / latch circuit 4 correspond as shown in Table 1 below.
[0050]
[Table 1]

[0051]
6 to 8 are waveform diagrams showing data read, write, and erase operations, respectively. In the present embodiment, BitlineE is selected for reading and writing, and BitlineO is not selected.
[0052]
First, a read operation will be described. The selected bit line is charged to 1.5V and then floated. Thereafter, the unselected word lines WL2 to WL8 and the selected gate lines SGS and SGD are set to the power supply voltage VCC. The selection word line is at 0V. When the data of the selected memory cell is "0", the bit line is discharged to 0V, otherwise the bit line remains at 1.5V.
[0053]
The bit line voltage is read into the first binary sense amplifier by the signal SBL1. Therefore, the node N1 becomes L when the data is "0", and becomes H when the data is "1" or "2". The selected word line is set to VG1 (= 1.8 V). If the data of the selected memory cell is "1", it is discharged to 0V, and if it is "2", it remains at 1.5V. If "0", the bit line is already at 0V. The bit line voltage is read into the second binary sense amplifier by the signal SBL2. Therefore, the node N2 becomes L when the data is "0" or "1", and becomes H when the data is "2" (Table 1). The latched data is serially read out to the I / O line.
[0054]
Next, a write operation will be described. At power-on, when the voltage reaches a voltage sufficient for normal operation of the chip, the power-on signal Pon becomes H. Using this signal, the latch data N1, 2 of the ternary sense amplifier / latch circuit 4 are both set to L. When a command for inputting write data is input, the latch data N1 and N2 are inverted using the command signal and both become H.
[0055]
The selected bit line is set to VCC, VD3-Vt (= 1 V) and 0 V, respectively, in accordance with the write data "0-2". A voltage VCC for not changing data is applied to the unselected bit lines. The selected gate line SGD is set at VCC, the SGS is set at 0 V, the selected word line is set at VPP (= 20 V), and the unselected word line is set at VM10 (= 10 V). Here, of the voltages output from the sense amplifier and latch circuit 4 to the bit lines, 0 V corresponds to the write voltage and VCC corresponds to the non-write voltage.
[0056]
In the selected memory cell in which 0 V and 1 V are applied to the bit line, a tunnel current flows because the gate-channel voltage is high, and the threshold voltage of the memory cell rises. Since the tunnel current flows more when the bit line is at 0 V than when it is at 1 V, the threshold voltage is higher. The selected memory cell to which VCC is applied has a low gate-channel voltage, so that a tunnel current does not flow and holds "0".
[0057]
Finally, the erasing operation will be described. When an erase command is input, VPP (= 20 V) is applied to the well of the memory cell array 2. Since the gate of the selected memory cell is set to 0 V, a tunnel current flows in the opposite direction to that during writing, and the threshold voltage of the memory cell decreases. On the other hand, since the gates of the non-selected memory cells and the selection transistors are floated, they rise close to VPP together with the wells of the memory cell array 2. Therefore, the tunnel current does not flow and the threshold voltage does not change.
[0058]
<Erase verify read>
Hereinafter, the erase verify read operation will be described with reference to a timing chart. When erasing is performed in block units, the memory cells in one block (for example, the memory cells selected by word lines WL1 to WL8) are read twice in an odd page and an even page. Verify reading is performed separately. FIG. 9 is a timing chart. FIG. 10 is a block diagram for explaining the erase verify read.
[0059]
The verify read is first performed on an even page (for example, a memory cell connected to the bit line BitlineE in FIG. 2), and the read data is held in the first latch circuit. Next, the read operation is performed on an odd page (for example, a memory cell connected to the bit line BitlineO in FIG. 2) and the read data is held in the second latch circuit.
[0060]
First, after precharging the bit line BitlineE to 1.5V, setting the selected gate lines SGS and SGD to Vcc and the word lines WL1 to WL8 to 0V at time t1, if the memory cell is sufficiently erased, Means that the bit line goes to 0V and keeps 1.5V in case of insufficient erasing. At time t2, BLSHFE becomes 1.5V, the potential of the bit line is transferred to the data circuit, and then SBL1 becomes "High", so that the data is transferred to the node N1 and sensed. Is done. As described above, the data of the even page is held in the first latch circuit. During the reading of the even-numbered page, the bit line BitlineO is kept at 0 V in order to reduce the capacitive coupling noise between bit lines.
[0061]
Subsequently, the process is performed on an odd page (for example, a memory cell connected to the bit line BitlineO in FIG. 2). After precharging the bit line BitlineO to 1.5V, setting the selected gate lines SGS and SGD to Vcc and the word lines WL1 to WL8 to 0V at time t4, if the memory cells are sufficiently erased, The bit line becomes 0V, and keeps 1.5V in case of insufficient erasing. At time t5, BLSHFO becomes 1.5V, the potential of the bit line is transferred into the data circuit, and then SBL2 becomes "High", so that the data is transferred to node N2 and sensed. Is done. Thus, the data of the odd page is held in the second latch circuit. During the reading of the odd page, the bit line BitlineE is kept at 0 V in order to reduce the capacitive coupling noise between the bit lines.
[0062]
The read data of the even page and the odd page are held in a first latch circuit and a second latch circuit, respectively. Thereafter, by sequentially selecting the columns by the column decoder, the data of the first and second latch circuits are output almost simultaneously. This makes it possible to determine whether the erasure has been sufficiently performed.
[0063]
As can be seen from FIG. 10, in the conventional example, the verify read is performed using only the first latch circuit, whereas in the present embodiment, both the first latch circuit and the second latch circuit are used. The speed of verify reading can be increased.
[0064]
In the above embodiment, the read data held in the first latch circuit during the reading of the odd-numbered page memory cells after the even-numbered page memory cells are first read and read into the first latch circuit. May be output through DLi and nDLi.
[0065]
Similarly, the memory cells in the first block and the second block which have been erased almost simultaneously are subjected to the verify read twice, and then the read data is read out of the first and second blocks, respectively. 2 may be held by the second latch circuit. Thus, when erasing a plurality of blocks almost simultaneously, erasing may be performed as shown in FIG. That is, the first, second,..., N-th (n is a natural number) blocks are erased almost simultaneously, and then the above-described verify read in units of one block is performed for each block erased. Do.
[0066]
Further, when the data circuit is composed of first, second,..., N-th latch circuits, each read data is stored in the first, second,. Of course, it is also possible to keep them.
[0067]
The present invention is also effective in the case where one data circuit is provided for one bit line for the cell array as shown in FIG. As an example, the data circuit has two latch circuits as shown in FIG.
[0068]
When erasing the first block and the second block in FIG. 36 at the same time, in the verify read, first the verify read of the first block is performed, and the data read to the first latch circuit is read. Hold. Next, verify reading of the second block is performed, and the read data is held in the second latch circuit. After that, the data of the first block and the data of the second block held in the first latch circuit and the second latch circuit are sequentially selected by the column decoder using the column decoder. The signals are output almost simultaneously from the first and second latch circuits. This makes it possible to determine whether the erasure has been performed sufficiently.
[0069]
Also in this case, the verify read is performed using only the first latch circuit in the conventional example, whereas in the present embodiment, both the first latch circuit and the second latch circuit are used. The speed of the verify read can be increased even with the memory cell array of FIG.
[0070]
Detecting the end of erasing, in addition to outputting the data of the first, second,. Collective detection may be performed using QNL9, QNL10,.
[0071]
As described above, even-page data and odd-page data are stored in the first and second latch circuits, respectively, or data from the first block to the n-th block is stored in the first,. After reading out to the n-th latch circuit, first, VRT is precharged to, for example, Vcc. At least one of the nodes N1, N2,... Becomes "High" in a column in which memory cells with insufficient erasure exist, and at least one of the n-channel MOS transistors QNL9, QNL10,. Turns on and VRT falls from the precharge potential. Only when all the selected memory cells are sufficiently erased, the nodes N1 and N2 become "Low" in all columns. As a result, the n-channel MOS transistors QNL9, QNL10,... In all the data circuits are turned off, so that VRT maintains the precharge potential and the end of erasing is detected.
[0072]
[Example 2]
(1) One block erase
FIG. 12 is a schematic diagram for explaining the operation of the erase verify read of one block, and FIG. 13 is a timing chart.
[0073]
The verify read is first performed on an even page (for example, a memory cell connected to the bit line BitlineE in FIG. 2), and the read data is held in the first latch circuit. Next, the read operation is performed on an odd page (for example, a memory cell connected to the bit line BitlineO in FIG. 2) and the read data is held in the first latch circuit.
[0074]
Prior to the verify read, the node N1 is set to "Low" and the node N3 is set to "High". First, after precharging the bit line BitlineE to 1.5V, the selected gate lines SGS and SGD are set to Vcc and the word lines WL1 to WL8 are set to 0V at time t1v. Means that the bit line goes to 0V and keeps 1.5V in case of insufficient erasing. At time t2v, BLSHFE becomes 1.5V, and the potential of the bit line is transferred into the data circuit. Thereafter, at time t3v, nVERIFY becomes “Low”. Since the node N3 is set to "High", the p-channel transistor Qp3 is turned off, and the potential of the node N4 does not change.
[0075]
In this one-block erase verify read operation, the operation of setting nVERIFY to "Low" and the setting of the first latch circuit (the operation of setting node N3 to "High") at time t3v are omitted. Can be.
[0076]
Thereafter, when SBL1 becomes "High", data is transferred to the node N1 and sensed. As described above, the data of the even page is held in the first latch circuit. During the reading of the even-numbered page, the bit line BitlineO is kept at 0 V in order to reduce the capacitive coupling noise between bit lines. As a result of the above verify read, the node N1 becomes "High" when the erasure is insufficient, and the node N1 becomes "Low" when the erasure is sufficient.
[0077]
Subsequently, verify reading is performed on an odd page (for example, a memory cell connected to the bit line BitlineO in FIG. 2). After precharging the bit line BitlineO to 1.5V, setting the selected gate lines SGS and SGD to Vcc and the word lines WL1 to WL8 to 0V at time t5v, if the memory cell is sufficiently erased, The bit line becomes 0V, and keeps 1.5V in case of insufficient erasing. At time t6v, BLSHFO becomes 1.5V, and the potential of the bit line is transferred into the data circuit. Thereafter, at time t7v, nVERIFY becomes “Low”.
[0078]
As a result of reading the even-numbered page, if the erasure is sufficient, since the node N3 is latched at "High", the p-channel transistor Qp3 is turned off and the potential of the node N4 does not change. That is, if the odd page is insufficiently erased, the node N4 becomes "High", and if the erase is sufficient, the node N4 becomes "Low".
[0079]
On the other hand, if the erasure is insufficient as a result of reading the even page, since the node N3 is latched at "Low", the p-channel transistor Qp3 is turned on and the potential of the node N4 is odd. -"High" regardless of the data of the page.
[0080]
Thereafter, when SBL1 becomes "High", data is transferred to the node N1 and sensed. During the reading of the odd page, the bit line BitlineE is kept at 0 V in order to reduce the capacitive coupling noise between the bit lines.
[0081]
As a result of the above-described verify read operation, if at least one of the even-numbered page and the odd-numbered page has an insufficiently erased cell, N1 becomes "High". N1 becomes "Low" only when both the even page and the odd page are sufficiently erased.
[0082]
[Table 2]

[0083]
By setting nVERIFY to "Low" at time t7v in this manner, erasure verify read can be performed using only the first latch circuit.
[0084]
After reading the read data of the even page and the odd page to the first latch circuit, the data of the first latch circuit is output by sequentially selecting the columns by the column decoder. This makes it possible to determine whether the erasure has been performed sufficiently.
[0085]
(2) When erasing a plurality of blocks almost simultaneously
Next, erasing and verify reading of a plurality of blocks will be described with reference to FIGS. First, the first, second,..., N-th (n is a natural number) blocks are erased almost simultaneously. Thereafter, erase verify read of each block is performed. The difference from the first embodiment is that it is not necessary to output the data read out to the first latch circuit every time the verify read of each block is performed, as shown in FIG. 2,... It is sufficient to perform the data only once after reading the data of the n-th block (n is a natural number) into the first latch circuit.
[0086]
The erase verify read of the first block is almost the same as the verify read of one block erase. The timing chart is almost the same as FIG. 13 is different from FIG. 13 in that the read data of the first latch circuit is not output to DLi and nDLi after the erase verify of the second block, and the first to n-th erase verify read is completed after the end of the erase verify read. The read data of the latch circuit is output to DLi and nDLi.
[0087]
The verify read is first performed on an even page of the first block (for example, a memory cell connected to the bit line BitlineE in FIG. 2), and the read data is held in the first latch circuit. Next, the process is performed on an odd page (for example, a memory cell connected to the bit line BitlineO in FIG. 2), and the read data is held in the first latch circuit.
[0088]
Prior to the verify read, the node N1 is set to "Low" and the node N3 is set to "High". First, after precharging the bit line BitlineE to 1.5V, the selected gate lines SGS and SGD are set to Vcc and the word lines WL1 to WL8 are set to 0V at time t1v. Means that the bit line goes to 0V and keeps 1.5V in case of insufficient erasing. At time t2v, BLSHFE becomes 1.5V, and the potential of the bit line is transferred into the data circuit. Thereafter, at time t3v, nVERIFY becomes “Low”. Since the node N3 is set to "High", the p-channel transistor Qp3 is turned off, and the potential of the node N4 does not change.
[0089]
In the erase verify read operation for one block, the operation of setting nVERIFY to "Low" at time t3v and the setting of the first latch circuit (the operation of setting node N3 to "High") are omitted. it can.
[0090]
Thereafter, when SBL1 becomes "High", data is transferred to the node N1 and sensed.
[0091]
Thus, the data of the even-numbered page of the first block is held in the first latch circuit. During the reading of the even-numbered page, the bit line BitlineO is kept at 0 V in order to reduce the capacitive coupling noise between bit lines. As a result of the above verify read, the node N1 becomes "High" when the erasure is insufficient, and the node N1 becomes "Low" when the erasure is sufficient.
[0092]
Subsequently, verify reading is performed on the odd-numbered pages of the first block (for example, the memory cells connected to the bit line BitlineO in FIG. 2). After precharging the bit line BitlineO to 1.5V, setting the selected gate lines SGS and SGD to Vcc and the word lines WL1 to WL8 to 0V at time t5v, if the memory cell is sufficiently erased, The bit line becomes 0V, and keeps 1.5V in case of insufficient erasing. At time t6v, BLSHFO becomes 1.5V, and the potential of the bit line is transferred into the data circuit. Thereafter, at time t7v, nVERIFY becomes “Low”.
[0093]
As a result of reading the even-numbered page of the first block, if the erasure is sufficient, since the node N3 is latched at "High", the p-channel transistor Qp3 is turned off and the potential of the node N4 is reduced It does not change. That is, if the odd page is insufficiently erased, the node N4 becomes "High", and if the erase is sufficient, the node N4 becomes "Low".
[0094]
On the other hand, if the erasure is insufficient as a result of reading the even page, since the node N3 is latched at "Low", the p-channel transistor Qp3 is turned on and the potential of the node N4 is odd. -"High" regardless of the data of the page.
[0095]
Thereafter, when SBL1 becomes "High", data is transferred to the node N1 and sensed. During the reading of the odd page, the bit line BitlineE is kept at 0 V in order to reduce the capacitive coupling noise between the bit lines.
[0096]
As a result of the above verify read operation, if at least one of the even page and the odd page of the first block is insufficiently erased as shown in Table 2, N1 is "High". become. Only when both the even and odd pages of the first block are sufficiently erased, N1 becomes "Low".
[0097]
Subsequently, erase verify read of the second block is performed. The timing chart is almost the same as FIG. 13 is different from FIG. 13 in that the read data of the first latch circuit is not output to DLi and nDLi after the erase verify of the second block, and the first to n-th erase verify read is completed after the end of the erase verify read. The read data of the latch circuit is output to DLi and nDLi.
[0098]
The verify read is performed on even pages of the second block (for example, memory cells connected to the bit line BitlineE in FIG. 2) and the read data is held in the first latch circuit. Next, the read operation is performed on the odd-numbered pages of the second block (for example, the memory cells connected to the bit line BitlineO in FIG. 2) and the read data is held in the first latch circuit.
[0099]
Unlike the erase verify read of the first block, the first latch circuit is not set, and the first latch circuit holds the result of the erase verify read of the first block. That is, as a result of performing the erase verify read of the first block, if at least one of the even-numbered page and the odd-numbered page has an insufficiently erased cell, N1 is "High".
[0100]
First, after precharging the bit line BitlineE to 1.5V, the selected gate lines SGS and SGD are set to Vcc and the word lines WL1 to WL8 are set to 0V at time t1v. Means that the bit line goes to 0V and keeps 1.5V in case of insufficient erasing. At time t2v, BLSHFE becomes 1.5V, and the potential of the bit line is transferred into the data circuit. Thereafter, at time t3v, nVERIFY becomes “Low”.
[0101]
If the memory cells in the block that has been verified and read before the second block (in this case, the first block) are insufficiently erased, the node N3 is "Low" and the p-channel transistor Qp3 is turned on. The potential of the node N4 becomes Vcc regardless of the potential of the bit line.
[0102]
On the other hand, if all the memory cells in the block (the first block in this case) verified and read before the second block are sufficiently erased, the node N3 is "High" and the p-channel transistor Qp3 is turned off. However, the potential of the node N4 does not change.
[0103]
In other words, if the odd page of the second block is insufficiently erased, the node N4 becomes "High", and if the erase is sufficient, the node N4 becomes "Low".
[0104]
Thereafter, when SBL1 becomes "High", the data is transferred to the node N1 and sensed.
[0105]
Thus, the data of the even page is held in the first latch circuit. During the reading of the even-numbered page of the second block, the bit line BitlineO is kept at 0 V to reduce the capacitive coupling noise between bit lines. As a result of the above verify read, the node N1 becomes "High" when the erasure is insufficient, and the node N1 becomes "Low" when the erasure is sufficient.
[0106]
Subsequently, verify reading is performed on an odd-numbered page of the second block (for example, a memory cell connected to the bit line BitlineO in FIG. 2). After precharging the bit line BitlineO to 1.5V, setting the selected gate lines SGS and SGD to Vcc and the word lines WL1 to WL8 to 0V at time t5v, if the memory cell is sufficiently erased, The bit line becomes 0V, and keeps 1.5V in case of insufficient erasing. At time t6v, BLSHFO becomes 1.5V, and the potential of the bit line is transferred into the data circuit. Thereafter, at time t7v, nVERIFY becomes “Low”.
[0107]
If there is at least one memory cell sufficient for erasure in the verify read before the verify read operation, the node N3 is latched at "High", so that the p-channel transistor Qp3 is turned off and the node N3 is turned off. -Do not change the potential of the node N4. That is, if the odd page of the second block is insufficiently erased, the node N4 is "High", and if the erase is sufficient, the node N4 is "Low".
[0108]
On the other hand, if all the memory cells have been sufficiently erased by the verify read before this verify read operation, since the node N3 is latched at "Low", the p-channel transistor Qp3 is turned on. The potential of the node N4 becomes "High" irrespective of the odd-numbered page data of the second block.
[0109]
Thereafter, when SBL1 becomes "High", data is transferred to the node N1 and sensed. During the reading of the odd page, the bit line BitlineE is kept at 0 V in order to reduce the capacitive coupling noise between the bit lines.
[0110]
The erase verify read of the i-th block (i is an integer of 2 or more and n or less) may be performed in substantially the same manner as the above-described second erase verify read.
[0111]
As a result of performing the first to n-th erase verify reads, if at least one block is insufficiently erased, the node N1 becomes "High". Only when all the memory cells are sufficiently erased, the node N1 becomes "Low".
[0112]
Thereafter, the data of the first latch circuit is output to DLi and nDLi by sequentially selecting the columns by the column decoder. This makes it possible to determine whether or not the erasure has been sufficiently performed in all the blocks that have been erased almost at the same time.
[0113]
In addition to outputting the data of the first latch circuit to DLi and nDLi as described above, the detection of the end of erasing may be collectively detected by using an erasing end batch detection transistor QNL9 as shown in FIG. .
[0114]
As described above, after reading data from the first block to the n-th block into the first latch circuit, first, VRT is precharged to, for example, Vcc. In a column in which a memory cell with insufficient erasure is present, the node N1 becomes "High", the n-channel MOS transistor QNL9 turns on, and VRT falls from the precharge potential. Only when all the selected memory cells are sufficiently erased, the node N1 becomes "Low" in all the columns. As a result, the n-channel MOS transistors QNL9 in all the data circuits are turned off, so that VRT maintains the precharge potential and the end of erasure is detected.
[0115]
As described above, according to the present invention, when erasing a plurality of blocks at the same time, read data is sequentially read out to the first latch circuit as shown in FIG. 14 during erase verify reading. After reading the data of all the blocks into the first latch circuit, the data may be output to DLi and nDLi only once, or may be detected all at once, so that the erase verify read can be performed at high speed. it can.
[0116]
[Example 3]
(1) A memory cell array including a predetermined number of electrically rewritable memory cells and including a memory cell group selected almost simultaneously at the time of erasing;
A bit line for transmitting and receiving data to and from the memory cell;
A signal line (node) electrically connectable to the bit line;
A data circuit for reading the state of the memory cell after erasing by sensing the potential of the signal line and holding the information;
After erasing a plurality of memory cell groups almost simultaneously, at the time of verify reading for checking whether erasing has been performed sufficiently,
The first data read out to the signal line by the verify read of the first memory cell group and held in the data circuit and the verify read of the second memory cell group are read. Sometimes, taking the logic with the second data read to the signal line,
If at least one of the first data and the second data is insufficiently erased, the potential of the signal line is set to an insufficiently erased level.
When both the first data and the second data are sufficiently erased, erase potential setting means for automatically setting the potential of the signal line to a sufficient erase level is provided as shown in FIGS. It is characterized by having. The first memory cell group and the second memory cell group may share word lines as shown in FIG. 26, and may be connected to different bit lines. Alternatively, as shown in FIG. 27, the first memory cell group and the second memory cell group may be selected as different word lines and connected to the same bit line. Further, a switch circuit may or may not be provided between the signal line and the bit line.
[0117]
(2) A memory cell array including a predetermined number of electrically rewritable memory cells and including a memory cell group selected almost simultaneously at the time of erasing;
A bit line for transmitting and receiving data to and from the memory cell;
A data circuit for sensing the state of the memory cell after erasing and holding the information;
A signal line (node) electrically connectable to the bit line;
A nonvolatile semiconductor memory device comprising:
The data circuit reads the state of the memory cell by sensing the potential of the signal line,
After erasing a plurality of memory cell groups almost simultaneously, at the time of verify reading for checking whether erasing has been performed sufficiently,
Verify reading of the first memory cell group is performed, and the first data read to the signal line is held in the data circuit.
When verify reading of the second memory cell group is performed, the potential of the signal line is adjusted based on the first data held in the data circuit. Therefore, the bit line may be connected to the signal line via the switch circuit as shown in FIG. FIG. 20B may also be used. In FIG. 20B, since the bit line also serves as the signal line, the first data for holding the potential of the signal line in the data circuit when performing the verify read of the second memory cell group. When the adjustment is performed based on the data, the potential of the bit line is also adjusted. Of course, even in the case of FIG. 20A, when verify reading of the second memory cell group is performed, the potential of the signal line is based on the first data held in the data circuit. When adjusting the potential, the potential of the bit line may be adjusted by turning on the switch circuit.
[0118]
(3) a memory cell array including a predetermined number of electrically rewritable memory cells and including a memory cell group selected almost simultaneously at the time of erasing;
A bit line for transmitting and receiving data to and from the memory cell;
A data circuit for sensing the state of the memory cell after erasing and holding the information;
A signal line (node) electrically connectable to the bit line;
A nonvolatile semiconductor memory device comprising
The data circuit reads the state of the memory cell by sensing the potential of the signal line,
After erasing a plurality of memory cell groups almost simultaneously, at the time of verify reading for checking whether erasing has been performed sufficiently,
Verify reading of the first memory cell group is performed, and the first data read to the signal line is held in the data circuit.
When verify-reading the second memory cell group, the potential of the signal line is adjusted based on the first data held in the data circuit,
Further, the plurality of memory cell groups include memory cells that share word lines with memory cells in other memory cell groups and are connected to different bit lines. .
[0119]
Therefore, for example, the configuration shown in FIG. Of course, the switch circuit need not be provided in FIG. Further, for example, verify reading of the first block connected to BitlineE in FIG. 15 is performed, and the read first data is held in the first latch circuit in FIG. Thereafter, verify reading of the second block is performed, which is connected to BitlineO and shares the word line with the first block, and the read second data is stored in the node N4 in FIG. Forward. After adjusting the second data of the node N4 based on the first data held in the first latch circuit, the data of the node N4 is transferred to the first latch circuit. Hold.
[0120]
(4) a memory cell array including a predetermined number of electrically rewritable memory cells and including a memory cell group selected almost simultaneously at the time of erasing;
A bit line for transmitting and receiving data to and from the memory cell;
A data circuit for sensing the state of the memory cell after erasing and holding the information;
A signal line (node) electrically connectable to the bit line;
A nonvolatile semiconductor memory device comprising
The data circuit reads the state of the memory cell by sensing the potential of the signal line,
After erasing a plurality of memory cell groups almost simultaneously, at the time of verify reading for checking whether erasing has been performed sufficiently,
Verify reading of the first memory cell group is performed, and the first data read to the signal line is held in the data circuit.
When verify-reading the second memory cell group, the potential of the signal line is adjusted based on the first data held in the data circuit,
Further, the plurality of memory cell groups include memory cells having different word lines from memory cells in other memory cell groups and connected to the same bit line.
[0121]
Therefore, for example, the configuration shown in FIG. Of course, the switch circuit (transfer gate of the n-channel transistor) in FIG. 22 may not be provided. Further, for example, verify reading of the first block connected to BitlineE in FIG. 15 is performed, and the read first data is held in the first latch circuit in FIG.
[0122]
Thereafter, verify reading of a second block is performed, which is connected to Bitline E and connected to a word line different from the first block, and the read second data is stored in a node N4 in FIG. Transfer to After adjusting the second data of the node N4 based on the first data held in the first latch circuit, the data of the node N4 is transferred to the first latch circuit. Hold.
[0123]
(5) a memory cell array including a predetermined number of electrically rewritable memory cells and including a memory cell group selected almost simultaneously at the time of erasing;
A bit line for transmitting and receiving data to and from the memory cell;
A data circuit for sensing the state of the memory cell after erasing and holding the information;
A signal line (node) electrically connectable to the bit line;
A nonvolatile semiconductor memory device comprising
The data circuit reads the state of the memory cell by sensing the potential of the signal line,
After erasing a plurality of memory cell groups almost simultaneously, at the time of verify reading for checking whether erasing has been performed sufficiently,
Verify reading of the first memory cell group is performed, and the first data read to the signal line is held in the data circuit.
When verify reading of the second memory cell group is performed, the first data and the second data are stored based on the first data held in the data circuit. If at least one of the data is insufficiently erased, the level is adjusted to the insufficiently erased level, and if both the first data and the second data are sufficiently erased, the level is adjusted to the sufficient erased level. It is characterized by the following.
[0124]
For example, verify reading of the first block connected to BitlineE of FIG. 15 is performed, and the read first data is held in the first latch circuit of FIG. Thereafter, verify reading of the second block is performed, which is connected to BitlineO and shares the word line with the first block, and the read second data is stored in the node N4 in FIG. Forward.
[0125]
If at least one of the first data and the second data is insufficiently erased based on the first data held in the first latch circuit, a node N4 is output. Is adjusted to an insufficiently erased level, and when both the first data and the second data are sufficiently erased, the node N4 is adjusted to a sufficiently erased level. Thereafter, the data of the node N4 is held in the first latch circuit.
[0126]
Further, the following case may be adopted. For example, verify reading of the first block connected to BitlineE of FIG. 15 is performed, and the read first data is held in the first latch circuit of FIG. Thereafter, verify reading of a second block is performed, which is connected to Bitline E and connected to a word line different from the first block, and the read second data is stored in a node N4 in FIG. Transfer to
[0127]
If at least one of the first data and the second data is insufficiently erased based on the first data held in the first latch circuit, a node N4 is output. Is adjusted to an insufficiently erased level, and when both the first data and the second data are sufficiently erased, the node N4 is adjusted to a sufficiently erased level. Thereafter, the data of the node N4 is held in the first latch circuit.
[0128]
(6) a memory cell array including a predetermined number of electrically rewritable memory cells and including a memory cell group selected almost simultaneously at the time of erasing;
A bit line for transmitting and receiving data to and from the memory cell;
A data circuit for sensing the state of the memory cell after erasing and holding the information;
A signal line (node) electrically connectable to the bit line;
A nonvolatile semiconductor memory device comprising
The data circuit reads the state of the memory cell by sensing the potential of the signal line,
After erasing a plurality of memory cell groups almost simultaneously, at the time of verify reading for checking whether erasing has been performed sufficiently,
Verify reading of the first memory cell group is performed, and the first data read to the signal line is held in the data circuit.
When verify reading of the second memory cell group is performed, the first data and the second data are stored based on the first data held in the data circuit. When at least one of the data is insufficiently erased, the level is adjusted to an insufficiently erased level, and when both the first data and the second data are sufficiently erased, the level is adjusted to a sufficient level of erase. ,
When verify reading of the m-th (m is a natural number not less than 2 and not more than n) memory cell group is performed, the potential of a signal line is set to a first voltage based on data held in a data circuit. If at least one of the data, the second data,..., The m-th data is insufficiently erased, the first data and the second data are set to the insufficiently erased level. If all of the data,..., M-th data, are sufficiently erased, the level is adjusted to a sufficiently erased level.
When verify reading of the n-th memory cell group is performed, the first data and the second data are stored in the data line based on the data held in the data circuit. ,..., If at least one of the n-th data is insufficiently erased (or written), the first data, the second data,. ... If all the n-th data is sufficiently erased, the level is adjusted to a sufficiently erased level.
[0129]
For example, verify reading of the first block connected to BitlineE of FIG. 15 is performed, and the read first data is held in the first latch circuit of FIG.
[0130]
Thereafter, verify reading of the first block is performed, which is connected to BitlineO and shares a word line with the first block, and the read second data is stored in the node N4 of FIG. Forward. Based on the first data held in the first latch circuit, if at least one of the first data and the second data is insufficiently erased, the node N4 is changed. If the first data and the second data are both sufficiently erased, the node N4 is adjusted to the sufficient erase level. Thereafter, the data of the node N4 is held in the first latch circuit.
[0131]
Next, verify reading of the second block, which is connected to Bitline E and connected to a word line different from the first block, is performed, and the read third data is output to the node shown in FIG. Transfer to node N4. Based on the data held in the first latch circuit, if at least one of the first data, the second data, and the third data is insufficiently erased, the program proceeds to the next step. If the first data, the second data, and the third data are all sufficiently erased, the node N4 is adjusted to the sufficient erase level. Thereafter, the data of the node N4 is held in the first latch circuit.
[0132]
Further, verify reading of the second block, which is connected to BitlineO and shares a word line with the second block, is performed, and the read fourth data is stored in a node N4 in FIG. Forward. Then, based on the data held in the first latch circuit, at least one of the first data, the second data, the third data, and the fourth data is erased. If the data is insufficient, the node N4 is set to an insufficiently erased level, and the first data, the second data, the third data, and the fourth data are all sufficiently erased. The node N4 is adjusted to a level sufficient for erasing. Thereafter, the data of the node N4 is held in the first latch circuit.
[0133]
(7) a memory cell array including a predetermined number of electrically rewritable memory cells and including a memory cell group selected almost simultaneously at the time of erasing;
A bit line for transmitting and receiving data to and from the memory cell;
A data circuit for sensing the state of the memory cell after erasing and holding the information;
A signal line (node) electrically connectable to the bit line;
A nonvolatile semiconductor memory device comprising
The data circuit includes a plurality of latch circuits,
The data circuit reads the state of the memory cell by sensing the potential of the signal line,
After erasing a plurality of memory cell groups almost simultaneously, at the time of verify reading for checking whether erasing has been performed sufficiently,
Verify reading of the first memory cell group is performed, and the first data read to the signal line is held in a first latch circuit in the data circuit.
Verify reading of the second memory cell group is performed, and the potential of the signal line from which the second data has been read is held in a second latch circuit in the data circuit. And For example, FIGS. 23 and 24, a switch circuit may or may not be provided. If there is no switch circuit, the bit line and the signal line have the same potential. Even when there is a switch circuit, the switch circuit may be made conductive when adjusting the potential of the signal line.
[0134]
(8) a memory cell array including a predetermined number of electrically rewritable memory cells and including a memory cell group selected almost simultaneously at the time of erasing;
A bit line for transmitting and receiving data to and from the memory cell;
A data circuit for sensing the state of the memory cell after erasing and holding the information;
A signal line (node) electrically connectable to the bit line;
A nonvolatile semiconductor memory device comprising
The data circuit includes a plurality of latch circuits,
The data circuit reads the state of the memory cell by sensing the potential of the signal line,
After erasing a plurality of memory cell groups almost simultaneously, at the time of verify reading for checking whether erasing has been performed sufficiently,
Verify reading of the first memory cell group is performed, and the first data read to the signal line is held in a first latch circuit in the data circuit.
Verify read of the second memory cell group is performed, and the potential of the signal line from which the second data has been read is held in a second latch circuit in the data circuit.
Further, the plurality of memory cell groups include memory cells having different word lines from memory cells in other memory cell groups and connected to the same bit line.
[0135]
Therefore, for example, the configuration shown in FIG. Of course, the switch circuit need not be provided in FIG. Further, for example, verify reading of the first block connected to BitlineE in FIG. 15 is performed, and the read first data is held in the first latch circuit in FIG. Thereafter, verify reading of the second block is performed, which is connected to Bitline E and connected to a word line different from the first block, and the read second data is stored in the second latch of FIG. Hold in circuit. Then, the first data held in the first latch circuit and the second data held in the second latch circuit are output through the IO line.
[0136]
(9) a memory cell array including a predetermined number of electrically rewritable memory cells and including a memory cell group selected almost simultaneously at the time of erasing;
A bit line for transmitting and receiving data to and from the memory cell;
A data circuit for sensing the state of the memory cell after erasing and holding the information;
A signal line (node) electrically connectable to the bit line;
A nonvolatile semiconductor memory device comprising
The data circuit includes a plurality of latch circuits,
The data circuit reads the state of the memory cell by sensing the potential of the signal line,
After erasing a plurality of memory cell groups almost simultaneously, at the time of verify reading for checking whether erasing has been performed sufficiently,
Verify reading of the first memory cell group is performed, and the first data read to the signal line is held in a first latch circuit in the data circuit.
Verify read of the second memory cell group is performed, and the potential of the signal line from which the second data has been read is held in a second latch circuit in the data circuit.
The plurality of memory cell groups include memory cells that share word lines with memory cells in other memory cell groups and are connected to different bit lines.
[0137]
Therefore, for example, the configuration shown in FIG. Of course, the switch circuit need not be provided in FIG. Further, for example, verify reading of the first block connected to BitlineE in FIG. 15 is performed, and the read first data is held in the first latch circuit in FIG. Thereafter, verify reading of a second block is performed, which is connected to BitlineO and shares a word line with the first block, and the read second data is stored in a second latch circuit of FIG. To hold. Then, the first data held in the first latch circuit and the second data held in the second latch circuit are output through the I / O line.
[0138]
(10) a memory cell array including a predetermined number of electrically rewritable memory cells and including a memory cell group selected almost simultaneously at the time of erasing;
A bit line for transmitting and receiving data to and from the memory cell;
A data circuit for sensing the state of the memory cell after erasing and holding the information;
A signal line (node) electrically connectable to the bit line;
A nonvolatile semiconductor memory device comprising
The data circuit includes a plurality of latch circuits,
The data circuit reads the state of the memory cell by sensing the potential of the signal line,
After erasing a plurality of memory cell groups almost simultaneously, at the time of verify reading for checking whether erasing has been performed sufficiently,
Verify reading of the first memory cell group is performed, and the first data read to the signal line is held in a first latch circuit in the data circuit.
Verify read of the second memory cell group is performed, and the potential of the signal line from which the second data has been read is held in a second latch circuit in the data circuit.
The verify read of the m-th (m is a natural number of 2 or more) memory cell group is performed, and the potential of the signal line from which the m-th data is read is set to the m-th data line in the data circuit. It is characterized by being held in a latch circuit.
[0139]
(11) Each of the data circuits has a batch detection circuit for detecting at once that all the erased memory cells are sufficiently erased. This batch detection circuit may be, for example, the transistor QNL9 in FIG.
[0140]
(12) The memory cell group may have a block configuration as shown in FIG. 36, for example.
[0141]
[Example 4]
In the above embodiment, the multi-level NAND type EEPROM has been described as an example, but the present invention is not limited to this. That is, since the binary flash memory performs erasure almost in the same manner as the multi-level flash memory, the present invention can of course be applied to the binary flash memory.
[0142]
Here, an example of an open bit line type cell array as shown in FIG. 28, in which two bit lines are shared by one data circuit, will be described. Note that the details of the read and write operations are described in T.K. Tanaka et. al. IEEE Journal of Solid-State Circuits vol. 29, No. 11, pp. 136-1373, November 1994.
[0143]
Hereinafter, the verify read after the blocks selected by CG1 to CG8 in FIG. 28 are erased will be described with reference to the timing chart of FIG.
[0144]
The verify read is first performed on an even page (for example, a memory cell connected to the bit line BLai in FIG. 28) of the first block, and the read data is held in the latch circuit. Next, the read operation is performed on an odd page (for example, a memory cell connected to the bit line BLai + 1 in FIG. 28) and the read data is held in the latch circuit.
[0145]
First, after precharging the bit line BLai to 1.8 V and BLbi to 1.5 V, when the selected gate lines SG1 and SG2 are set to Vcc and the word lines CG1 to CG8 are set to 0V at time t1y, the memory When the cell is sufficiently erased, the bit line potential becomes lower than the dummy-bit line potential of 1.5 V, and when the cell is insufficiently erased, the bit line is kept at 1.8 V. At time t2y, φ1 becomes Vcc, and the potentials of the bit line and dummy bit line are transferred into the data circuit. Thereafter, when φa becomes “High”, the data is transferred and sensed. Thus, the data of the even-numbered page is held in the latch circuit.
[0146]
During reading of the even-numbered page, the bit lines BLai + 1 and BLbi + 1 are kept at 0 V in order to reduce capacitive coupling noise between bit lines. As a result of the above verify read, the node N1 becomes "High" when the erasure is insufficient, and the node N1 becomes "Low" when the erasure is sufficient.
[0147]
Subsequently, verify reading is performed on an odd page (for example, a memory cell connected to bit line BLai + 1 in FIG. 28). After precharging the bit line BLai + 1 to 1.8 V and the dummy bit line BLbi + 1 to 1.5 V, at time t5y, the selected gate lines SG1 and SG2 are set to Vcc and the word lines CG1 to CG8 are set to 0V. When the memory cell is sufficiently erased, the potential of the bit line becomes 1.5 V or lower of the dummy bit line, and when the memory cell is insufficiently erased, 1.8 V is maintained. At time t6y, φ2 becomes Vcc, and the potential of the bit line is transferred into the data circuit. Thereafter, φAV becomes “High” at time t7y.
[0148]
As a result of reading the even-numbered page, if the erasure is sufficient, since the node N1 is latched at "Low", the n-channel transistor QNS is turned off and the potential of the node N4 does not change. That is, if the odd page is insufficiently erased, the node N4 becomes "High", and if the erase is sufficient, the node N4 becomes "Low".
[0149]
On the other hand, if the erasure is insufficient as a result of reading the even-numbered page, since the node N1 is latched at "High", the n-channel transistor QNS is turned on and the potential of the node N4 is odd. -"High" regardless of the data of the page.
[0150]
Thereafter, when φa and φb become “High”, the data is transferred and sensed. During the reading of the odd-numbered page, the bit lines Blai and Blb2 are kept at 0 V to reduce the capacitive coupling noise between the bit lines.
[0151]
As a result of the above-described verify read operation, if at least one of the even-numbered page and the odd-numbered page has an insufficiently erased cell, N1 becomes "High". Only when both the even and odd pages are sufficiently erased, N1 becomes "Low".
[0152]
In addition to outputting the data of the latch circuit to the IOAs and IOBs as shown in FIG. 29, the completion of erasing may be detected by using an erasing completion batch detection transistor QNN as shown in FIG. 28, for example. After the data of the even and odd pages or the data from the first block to the n-th block is read out to the first latch circuit as in the second embodiment, first, , VRT are precharged to, for example, Vcc.
[0153]
In a column where a memory cell with insufficient erasure exists, the node N1 becomes "High", the n-channel MOS transistor QNN turns on, and VRT falls from the precharge potential. Only when all the selected memory cells are sufficiently erased, the node N1 becomes "Low" in all the columns. As a result, the n-channel MOS transistors QNN in all the data circuits are turned off, so that VRT maintains the precharge potential and the end of erasure is detected.
[0154]
The present invention can be applied to not only the NAND type EEPROM of FIG. 3 but also a NOR type flash memory as shown in FIG. 19, and an AND type (K. Kume et al .; IEDM Tech. Dig) as shown in FIG. , Dec. 1992, pp. 991-993), a DINOR type as shown in FIG. 17 (S. Kobayashi et al .; ISSCC Tech. Dig., 1995, pp. 122), and a virtual ground array type as shown in FIG. (R. Cemea et al .; ISSCC Tech. Dig., 1995, pp. 126). Also, a mask ROM may be used.
[0155]
The present invention can be applied not only to a ternary memory cell or a quaternary memory cell but also to a quinary memory cell, an octal memory cell, or a 16-level memory cell.
[0156]
[Example 5]
Further, the present invention can be applied to a sense amplifier as shown in FIG. The writing and reading methods are described in IEEE Journal of Solid-State Circuits vol. 30, no. 11, pp. 1157-1164, November 1995. FIG. 31 is a timing chart of the erase verify read.
[0157]
The verify read is first performed for an even page (for example, a memory cell connected to the bit line BLai in FIG. 30), and the read data is held in the latch circuit. Then, an odd page (for example, a memory cell connected to the bit line BLai + 1 in FIG. 30) is performed, and the latch circuit holds read data.
[0158]
First, by setting Reset to "High", the node N1 is set to "Low" and the node N2 is set to "High". Subsequently, after the bit line BLai is precharged to 2V, the selected gate lines SG1 and SG2 are set to Vcc and the word lines CG1 to CG8 are set to 0V at time t1s. The bit line goes to 0V and keeps 2V in case of insufficient erasing. At time t2S, φ1 becomes Vcc, and the potentials of the bit line and dummy bit line are transferred into the data circuit. After that, the signal is sensed when Read becomes “High”.
[0159]
That is, in the case of insufficient erasing, the n-channel transistor Qread is turned on, the node N2 becomes "Low", and the node N1 becomes "High". If the erase operation is sufficient, the n-channel transistor Qread is turned off, and the node N2 is kept at "High". Thus, the data of the even-numbered page is held in the latch circuit. During the reading of the even-numbered page, the bit line BLai + 1 is kept at 0 V to reduce the capacitive coupling noise between bit lines.
[0160]
Subsequently, verify reading is performed on odd pages (for example, memory cells connected to bit line BLai + 1 in FIG. 30). After precharging the bit line BLai + 1 to 2V, setting the selected gate lines SG1 and SG2 to Vcc and the word lines CG1 to CG8 to 0V at time t5s. If the memory cell is sufficiently erased, the bit line Becomes 0V, and keeps 2V in case of insufficient erasing. At time t6s, φ2 becomes Vcc, and the potential of the bit line is transferred into the data circuit. After that, the signal is sensed when Read becomes “High”.
[0161]
That is, in the case of insufficient erasing, the n-channel transistor Qread is turned on, the node N2 becomes "Low", and the node N1 becomes "High". If the erase operation is sufficient, the n-channel transistor Qread is turned off, and the node N2 is kept at "High". During the reading of the odd-numbered page, the bit line BLai is kept at 0 V in order to reduce the capacitive coupling noise between bit lines.
[0162]
As a result of the above-described verify read operation, if at least one of the even-numbered page and the odd-numbered page has an insufficiently erased cell, N1 becomes "High" and N2 becomes "Low". Only when both the even page and the odd page are sufficiently erased, N1 becomes "Low" and N2 becomes "High".
[0163]
In addition to outputting the data of the latch circuit to the I / O line, the detection of the end of erasing may be collectively detected by using, for example, the erasing end detecting transistor QSN as shown in FIG. After reading the data of the even and odd pages to the first latch circuit as described above, first, VRT is precharged to, for example, Vcc. In a column in which a memory cell with insufficient erasure is present, the node N1 becomes "High", the n-channel MOS transistor QSN turns on, and VRT falls from the precharge potential. Only when all the selected memory cells are sufficiently erased, the node N1 becomes "Low" in all the columns. As a result, the n-channel MOS transistors QSN in all data circuits are turned off, so that VRT maintains the precharge potential and the end of erasing is detected.
[0164]
【The invention's effect】
As described above, according to the nonvolatile semiconductor memory device of the present invention, the following effects can be obtained.
[0165]
That is, in a memory cell array in which one sense amplifier is shared by a plurality of bit lines, memory cells connected to the plurality of bit lines are erased almost simultaneously at the time of erasing, and after erasing, the memory cells connected to the respective bit lines are erased. An erase verify read is performed for this, but the time for the erase verify read can be greatly reduced. In addition, in order to prevent an increase in the area of the peripheral circuit in the multi-valued memory, even when one data circuit is shared by a plurality of bit lines, the time for the erase verify read is not lengthened.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a semiconductor memory device according to an embodiment of the present invention.
FIG. 2 illustrates an example of a configuration of a column circuit.
FIG. 3 is a diagram showing a configuration of a NAND cell.
FIG. 4 is a diagram showing an example of a configuration of a row decoder.
FIG. 5 is a diagram showing an example of a configuration of a row decoder.
FIG. 6 is a waveform chart showing a data read operation.
FIG. 7 is a waveform chart showing a data write operation.
FIG. 8 is a waveform chart showing an operation of erasing data.
FIG. 9 is a waveform chart showing an erase verify read operation.
FIG. 10 is a flowchart showing an erase verify read operation.
FIG. 11 is a flowchart showing an erase verify read operation.
FIG. 12 is a flowchart showing an erase verify read operation.
FIG. 13 is a waveform chart showing an erase verify read operation.
FIG. 14 is a flowchart showing an erase verify read operation.
FIG. 15 illustrates an example of a configuration of a column circuit.
FIG. 16 is a diagram showing a configuration of a ground array type cell.
FIG. 17 is a diagram showing a configuration of a DINOR cell.
FIG. 18 is a diagram showing a configuration of an AND cell.
FIG. 19 illustrates a structure of a NOR cell.
FIG. 20 is a diagram showing a first configuration of the present invention.
FIG. 21 is a diagram showing a second configuration of the present invention.
FIG. 22 is a diagram showing a third configuration of the present invention.
FIG. 23 is a diagram showing a fourth configuration of the present invention.
FIG. 24 is a diagram showing a fifth configuration of the present invention.
FIG. 25 illustrates an example of a configuration of a column circuit.
FIG. 26 is a diagram showing a sixth configuration of the present invention.
FIG. 27 is a diagram showing a seventh configuration of the present invention.
FIG. 28 illustrates an example of a configuration of a column circuit.
FIG. 29 is a waveform chart showing an erase verify read operation.
FIG. 30 illustrates an example of a configuration of a column circuit.
FIG. 31 is a waveform chart showing an erase verify read operation.
FIG. 32 is a diagram showing one unit of a memory cell array of a NAND cell type EEPROM.
FIG. 33 is a sectional view taken along the line XXXIII-XXXIII in FIG. 32;
FIG. 34 is a sectional view taken along the line XXXIV-XXXIV of FIG. 32;
FIG. 35 is a view showing an equivalent circuit of the device shown in FIG. 32;
FIG. 36 is a diagram showing an equivalent circuit of a memory cell array of a NAND cell type EEPROM.
[Explanation of symbols]
1: semiconductor storage device (chip),
2: memory cell array,
3: Low Decoder,
4: Sense amplifier and latch circuit
5: Word / bit line control signal generation circuit
6: well potential control circuit,
7: Address buffer,
8: I / O buffer,
9: Command buffer,
10: column decoder,
11: p-type silicon substrate,
12: field oxide film,
13: gate oxide film,
14: floating gate electrode,
15: insulating film,
16: control gate electrode,
17: interlayer insulating film,
18: bit line,
19: n-type diffusion layer,
20: source wire,
21: reference potential wiring,
22: precharge circuit,
I1 to I5: Inverter,
QP1 to QP3: P-channel MOS transistors,
QNL1 to QNL6: N-channel MOS transistors,
QNH1 to QNH6: N-channel MOS transistors
G1: NAND circuit,
BL: bit line,
M1 to M8: memory cells,
S1, S2: select gate transistors.

Claims (22)

A memory cell array including a predetermined number of electrically rewritable memory cells and having first and second memory cell groups selected at the time of erasing ;
A node connected to a first bit line connected to the first memory cell group and a second bit line connected to the second memory cell group;
A data circuit that holds data corresponding to information read from the first memory cell group and information read from the second memory cell group during an erase verify read ;
In the erase verify read for the first group of memory cells, a first data read out to said data circuit through the node, the erase verify read for the second memory cell group, read out to the node By taking the logic with the second data, if the first and second data are both sufficiently erased , the data circuit holds data indicating the completion of the erasure , and the first and second data are stored in the data circuit. When at least one of the data is insufficiently erased , the data circuit holds data indicating re-execution of erasure , wherein the data circuit holds data indicating re-execution of erasure . 2. A memory cell constituting the first memory cell group and a memory cell constituting the second memory cell group share a word line with each other. Nonvolatile semiconductor memory device. A plurality of the data circuits are provided in the word line direction, and a collective detection circuit is provided to collectively detect that all the memory cells selected for these data circuits are sufficiently erased. 2. The non-volatile semiconductor memory device according to claim 1, wherein: A memory cell array including a predetermined number of electrically rewritable memory cells and having first and second memory cell groups selected at the time of erasing ;
A first bit line connected to the first memory cell group and a node connected to a second bit line connected to the second memory cell group;
At the time of erase verify read , the first data read from the first memory cell group is held in a data circuit, and then the first data and the second data read from the second memory cell group are stored in the data circuit. A non-volatile semiconductor storage device, wherein the potential of the node is set based on the setting. 5. A memory cell constituting the first memory cell group and a memory cell constituting the second memory cell group share a word line with each other. Nonvolatile semiconductor memory device. A memory cell array including a predetermined number of electrically rewritable memory cells and having first and second memory cell groups selected at the time of erasing ;
A bit line connected to the first and second memory cell groups;
A node connected to the bit line,
At the time of erase verify read , the first data read from the first memory cell group is held in a data circuit, and then the first data and the second data read from the second memory cell group are stored in the data circuit. A non-volatile semiconductor storage device, wherein the potential of the node is set based on the setting. 7. The memory cell constituting the first memory cell group and the memory cells constituting the second memory cell group are connected to different word lines. 10. The nonvolatile semiconductor memory device according to claim 1. A memory cell array comprising a plurality of electrically rewritable memory cells and having a plurality of memory cell groups simultaneously selected at the time of erasing ;
A node connected to a bit line connected to the plurality of memory cell groups,
When the plurality of the memory cell groups after erasing substantially simultaneously verify read to check erase it was sufficiently,
Performing a verify read of the first memory cell group, holding the first data read to the node in a data circuit,
When verify-reading of the second memory cell group is performed, if at least one of the first data and the second data read from the second memory cell group is insufficiently erased , the node the insufficiently erased level, the first when the data and the second data is erased enough together, the nonvolatile semiconductor memory device and adjusting the erase sufficient level the node. A memory cell array comprising a plurality of electrically rewritable memory cells and having a plurality of memory cell groups simultaneously selected at the time of erasing ;
A node connected to a bit line connected to the plurality of memory cell groups,
When the plurality of the memory cell groups after erasing substantially simultaneously verify read to check erase it was sufficiently,
Performing a verify read of the first memory cell group, holding the first data read to the node in a data circuit,
When verify-reading of the second memory cell group is performed, if at least one of the first data and the second data read from the second memory cell group is insufficiently erased , the node Is adjusted to an insufficiently erased level, and when the first data and the second data are both sufficiently erased , the node is adjusted to a sufficient erased level ;
(Is m, 2 to n a natural number) first m when performing a verify read of the memory cell groups of the first data, second data, ..., at least one of insufficient erasure of the data of the m in the case of, the insufficiently erased level the node, the first data, the second data, ..., when the data of the first m are all erased sufficiently, sufficiently erased level the node Adjust to
When at least one of the first data, the second data,..., And the n-th data is insufficiently erased during the verify read of the n-th memory cell group, the node is insufficiently erased. level, the first data, the second data, ..., the first when n the data are all erased sufficiently nonvolatile semiconductor and adjusting the erase sufficient level the node Storage device. 10. The nonvolatile semiconductor memory device according to claim 8, wherein the memory cells constituting the plurality of memory cell groups are connected to different word lines. A memory cell array including a predetermined number of electrically rewritable memory cells and having first and second memory cell groups selected at the time of erasing ;
A node connected to a first bit line connected to the first memory cell group and a second bit line connected to the second memory cell group;
Data having a first latch circuit for holding information read from the first memory cell group and a second latch circuit for holding information read from the second memory cell group during erase verify read And a circuit. 12. The memory cell constituting the first memory cell group and the memory cell constituting the second memory cell group share a word line with each other. Nonvolatile semiconductor memory device. A plurality of the data circuits are provided in the word line direction, and a collective detection circuit is provided to collectively detect that all the memory cells selected for these data circuits are sufficiently erased. The nonvolatile semiconductor memory device according to claim 11, wherein A memory cell array including a predetermined number of electrically rewritable memory cells and having first and second memory cell groups selected at the time of erasing ;
A bit line connected to the first and second memory cell groups;
A node connected to the bit line;
Data having a first latch circuit for holding information read from the first memory cell group and a second latch circuit for holding information read from the second memory cell group during erase verify read And a circuit. 15. The memory cell constituting the first memory cell group and the memory cells constituting the second memory cell group are connected to different word lines. 10. The nonvolatile semiconductor memory device according to claim 1. A plurality of the data circuits are provided in the word line direction, and a collective detection circuit is provided to collectively detect that all the memory cells selected for these data circuits are sufficiently erased. The nonvolatile semiconductor memory device according to claim 14, wherein: A memory cell array comprising a plurality of electrically rewritable memory cells and having a plurality of memory cell groups simultaneously selected at the time of erasing ;
A node connected to a bit line connected to each memory cell group;
.., M (m is a natural number) of the plurality of memory cell groups at the time of erase verify read , m latch circuits each holding information read from the memory cell groups. And a data circuit having the same. 18. The non-volatile semiconductor memory device according to claim 17, wherein the memory cells constituting each memory cell group share a word line with each other. A plurality of the data circuits are provided in the word line direction, and a collective detection circuit is provided to collectively detect that all the memory cells selected for these data circuits are sufficiently erased. 18. The non-volatile semiconductor storage device according to claim 17, wherein: A memory cell array comprising a plurality of electrically rewritable memory cells and having a plurality of memory cell groups simultaneously selected at the time of erasing ;
A bit line connected to the plurality of memory cell groups;
A node connected to the bit line;
.., M (m is a natural number) of the plurality of memory cell groups at the time of erase verify read , m latch circuits each holding information read from the memory cell groups. And a data circuit having the same. 21. The nonvolatile semiconductor memory device according to claim 20, wherein the memory cells forming each memory cell group are connected to different word lines. A plurality of the data circuits are provided in the word line direction, and a collective detection circuit is provided to collectively detect that all the memory cells selected for these data circuits are sufficiently erased. 21. The non-volatile semiconductor storage device according to claim 20, wherein:

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