JPH07176196A - Batch erasing type non-volatile storage device - Google Patents

Abstract

PURPOSE:To efficiently rewrite data, to increase operational speed of memory access and to improve hadleability by performing erasing and writing operation in a memory array which is constituted of transistors performing erasing and writing operation by injecting and discharging electric charges to/from a floating gate in a word line unit. CONSTITUTION:A memory array is constituted by arranging storage transistors in a matrix state at intersections of a word line and reading and writing data lines DLL, DLR, and a latch circuit is provided corresponding to the lines DLL, DLR. Erasing operation is performed in a unit of a word line WL connected to a control gate and also writing and reading operations are performed in a word line unit through the latch circuit. At the time of a random access mode, a read-out path is formed by connecting output lines IOL and IOR to an input terminal of a current sense amplifier CAS through a MOSFET controlled with a switch by a signal RB, and a selected memory cell can be read out at high speed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a batch erasing type non-volatile memory device (flash EEPROM;
The present invention relates to an eraseable & programmable read only memory), which is effective when used for speeding up the rewriting time.

[0002]

2. Description of the Related Art An electrical batch erasing type EEPROM is a system in which all of the memory cells formed on a chip are collectively operated, or a group of memory cells among the memory cells formed on the chip are collectively operated. It is a non-volatile memory device that has a function of erasing physically. Such a batch erase type EEPR
Regarding OM, for example, 1980 IEE, International, Solid-State
Circuits Conference (IEEE INTERNATIONAL SOL
ID-STATE CIRCUITS CONFERENCE) pages 152-153, 19
1987 IEE, International, Solid-State Circuits Conference
(IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENC
E) pages 76-77, IEE Journal
Of Solid State Circuits, Vol. 23, No. 5 (1988), pages 1157 to 1163 (IEEE, J. Solid-S
tate Cicuits, vol.23 (1988) pp.1157-1163).

[0003]

In the applicant of the present application, a write operation is performed by a tunnel current as a memory transistor having a control gate and a floating gate, and charges are injected into the floating gate contrary to the conventional case. By doing so, a memory transistor has been developed which performs an erase operation by making the threshold voltage higher than the selection level of the word line. In this configuration, since the threshold voltage of the erase operation for the memory transistor is set higher than the selection level of the word line, the charge of the floating gate is extracted to the substrate side as in the conventional case. Like a memory transistor that lowers the voltage, it does not make other memory cells unreadable by turning it on even though the word line is at the non-select level due to depletion due to overerasure. .

However, in the case where the write operation is performed by the tunnel current, the voltage applied to the drain of the memory transistor at the time of read is made as low as possible so that the tunnel current is not generated by the read operation and erroneous erasure is prevented. There is a need. Therefore, the memory cycle of the read operation from the memory transistor as described above becomes relatively slow. Therefore, the inventor of the present application can perform the erase operation in units of word lines, and accordingly, the write operation and the read operation are also performed in units of word lines, so that memory access per unit data is performed. I thought about speeding up and improving usability.

An object of the present invention is to provide a batch erasing type non-volatile memory device which is easy to use while achieving high speed operation. The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0006]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, due to the relative potential relationship between the control gate and the substrate, charges are injected from the substrate side to the floating gate through the tunnel insulating film to perform an erase operation, and the relative potential between the control gate and the drain is compared. Depending on the relationship, memory transistors are formed by arranging memory transistors, which perform a write operation by discharging charges from the floating gate to the drain side through the tunnel insulating film, in a matrix at the intersections of the word lines and the data lines. A latch circuit is provided corresponding to the data line, and an erase operation is performed in units of word lines to which the control gates are coupled, and a write operation and a read operation are performed in units of word lines via the latch circuits. , Random for each selected data line
An access read path is provided.

[0007]

According to the above-mentioned means, data consisting of a large number of bits can be efficiently rewritten on a word line basis, so that memory access per unit data can be speeded up and compatibility with a magnetic memory device as a file memory can be achieved. In addition, it is possible to directly read a small amount of data by random access, which improves usability.

[0008]

1 and 2 are block diagrams showing an embodiment of a batch erase type nonvolatile memory device according to the present invention. FIG. 1 shows a block diagram centering on the memory array, and FIG. 2 shows a block diagram of the remaining peripheral circuits. Each circuit block shown in FIGS. 1 and 2 is formed on a single semiconductor substrate such as single crystal silicon, though not particularly limited, by a known semiconductor integrated circuit manufacturing technique.

In this embodiment, although not particularly limited, the memory array is composed of two memory mats MAT. Each memory mat (Memory MAT) has a sub decoder (Sub Decod) that forms a selection signal of the word line WL.
er) is provided. The memory mat is actually composed of a plurality of small memory mats as described later,
Sub-decoders are provided on both sides of each small memory mat.
Since the word lines are formed with a narrow pitch for high integration, the sub-decoders sandwiched between the small memory mats form word line selection signals for the small memory mats on both sides. Therefore, the word lines of the small memory mat are alternately connected to two sub-decoders sandwiching the word line.

The main decoder is a selection MOSFE for selecting a plurality of memory cells as described later.
It is composed of a selection signal of T and a circuit which forms a selection level and a non-selection level of the sub-decoder. Gate decoder (G
ate Decoder) forms a word line selection signal corresponding to one memory cell in one memory block, which will be described later, selected by the main decoder.

The memory transistor formed in the small memory mat is not particularly limited, but both the erase and write operations are such that charges are injected into and discharged from the floating gate by a tunnel current.

The sense amplifier SA is not particularly limited, but it is composed of a CMOS latch circuit as will be described later, and the amplification operation is controlled by the sense amplifier control circuit (SA Control). Two sets of sense amplifiers are provided corresponding to the odd and even data lines of the above two memory mats. One of the pair of input / output nodes of the sense amplifier is connected to the data line of the one memory mat, and the other is connected to the data line of the other memory mat. This structure is different from the folded data line system such as the dynamic RAM, and is connected to the data lines of the memory mat divided into upper and lower parts with the sense amplifier as the center. By separating the sense amplifiers as described above, it is possible to match the pitch of the data lines and the sense amplifiers arranged in high density, and by operating the sense amplifiers alternately, pipeline read operation is possible. It is said that

When the sense amplifier receives a read signal necessary for the amplifying operation from the data line in order to speed up the operation and reduce the power consumption, it is disconnected from the data line immediately before or after the start of the amplifying operation. The signal taken in is amplified and held. Therefore, Y gate circuit (Ygate)
The signal selected by is passed through the input / output lines I / OR and I / OR to the main amplifier (Main Amp) and output buffer (Output
Buffer), and in parallel with such signal output operation, the word line corresponding to the next address can be switched.

Status Register
Can receive status data by the signal TS, and can monitor the operating state from the outside through the output buffer if necessary. In this embodiment, the continuous access operation and the electrically writing and erasing operations are performed as described above, and it is necessary to know the internal state from the outside in the middle of each operation. A register is provided.

The voltage generator (Voltage Generator) is
It receives a power supply voltage VCC such as 3.3V (or 5V) and the ground potential VSS of the circuit, and writes by a control signal TV,
Various voltages VWG, V required for each read and erase operation
WV, VWS, VEG, VED, VEV, VWD and V
It serves as a DC-DC converter that forms r. Here, VWG is a word line voltage at the time of programming, VWV is a word line voltage at the time of programming verification, VWD is a drain voltage at the time of programming, and VE.
V is a word line voltage at the time of erase verify, VEG is a word line voltage at the time of erase, VED is a drain voltage at the time of erase, VWS is a gate voltage of a selection MOSFET at the time of write, and a data line is a sense amplifier. It is the gate voltage of the transfer MOSFET connected and the precharge voltage of the Vr data line.

The address buffer (Address Buffer) takes in the address signal Ai supplied from the external terminal and causes the address latch (Address Latch) to hold the address signal. The signal TA is a control signal for latching the address signal, and TSC is an internal serial clock.

Address Generator
Performs an address stepping operation by an internal serial clock TSC generated in synchronization with a clock SC supplied from the outside, and outputs a Y-system address signal Ay and an address signal A.
8 and the word line switching signal AC are generated. That is, in the semiconductor memory device of this embodiment, only by inputting a designated start address, an address signal for subsequent continuous access is internally generated corresponding to a clock SC supplied from an external terminal. . The address signals Ay, AC, / AC and A8 are supplied to the sense amplifier control circuit SAC. Here, / attached to the signal AC indicates that it is a bar signal. Such signal / A
C indicates that the low level is the active level. This also applies to the other signals below.

The Y gate forms a selection signal for one data line in the read operation by the Y-system address signal Ay, selects the amplified signal of the sense amplifier corresponding to the selection signal, and transmits it to the data output buffer OB. . In the write operation in the serial mode, a select signal for one data line is formed and the write data input from the input buffer is transmitted to the sense amplifier. In the random mode, the corresponding signal is transmitted to the data line or the bit line. In the present application, the data line and the bit line are used with the same meaning. These are sometimes called digit lines.

The Command Decoder is
The command input from the input buffer is decoded and the command data Di is transferred to the control circuit (Control Circu
tell it). The signal TC is a command decoder control signal, which fetches commands and controls the decoder.

The control circuit includes a chip enable signal / CE, an output enable signal / OE, a write enable signal / WE and a clock S supplied from an external terminal.
Upon receiving C, the reset signal RESET, and the signals AC and Di internally generated as described above, various timing signals necessary for the operation of the internal circuit are formed. The signal TXM is a main decoder control signal and is a signal for switching positive / negative logic at the time of program-program verify. The signal TXG is a gate decoder control signal. Signal TV
Is a power supply circuit control signal. The signal TA is an address buffer control signal and controls address latching and the like. The signal TI is a data input buffer control signal,
Controls the acquisition of data and commands.

The signal TO is a data output buffer control signal and controls data output and the like. The signal TC is a command decoder control signal, and controls the fetching and decoding of commands. The signal TS is a status register control signal and controls the setting or resetting of the status register SREG. The signal TSA is a sense amplifier control signal and is used for controlling activation timing. The signal TSC is the internal serial clock. The signal AC is a word line switching signal.

In addition, the signal TS is a reset or set control signal for the status register, the signal Do is status data, and the signal SCO is an internal serial clock signal. RB is a random access control signal and SB is a serial access control signal.
The address AxOR / L output from the address latch is an X-system address signal supplied to the main decoder.
The address signal Ax1R / L is an X-system address signal supplied to the gate decoder. The signal ATD is a change sensing signal for the address signal, mode, and / CE, and TDEK is a power supply control signal for the sense amplifier.

FIG. 3 shows a schematic circuit diagram of one embodiment of the memory mat and its peripheral portion. The memory cell is a stacked gate MOSFET having a control gate and a floating gate similar to those of the conventional memory cell. In this embodiment, both a writing operation and an erasing operation are performed by utilizing a tunnel current passing through a thin oxide film as described later.

A plurality of the memory MOSFETs are made into one block, and the drain and the source are commonly used. Memory M
The common drain of the OSFET is a selection MOSFET.
It is connected to the data line DL through T. Memory MOSFE
The common source of T is connected to the common source line through the select MOSFET. The common source line is switch-controlled by the signal MSC and connected to the voltage VMW. The control gate of the storage MOSFET is connected to the word line WL. The selection MOSFET is selected by a selection line extending in parallel with the word line WL. That is, the selection MOSFET is a main word line selected by the main decoder MAN-DEC.

As described above, the memory cell is divided into blocks, and the data line DL is connected to each block through the selection MOSFET.
With the configuration for applying the VMW (ground potential) of the circuit or the circuit, the stress on the non-selected memory cells can be reduced. That is, the word line is selected and the data line is in the non-selected state, or conversely, the word line is in the non-selected state and the data line is in the non-selected state, so that the data in the write or erase operation is changed. The voltage for writing or erasing is prevented from being applied to the memory cell that should hold. With this configuration, the above-mentioned stress is only applied to a small number of memory cells in the block.

In this embodiment, although not particularly limited, adjacent data lines DL are divided into odd-numbered and even-numbered data lines, as will be described later. And short MOSFET is provided corresponding to each. This short MOSFE
T is designed to alternately select the odd-numbered and even-numbered data lines DL, set the data line DL in the non-selected state to the fixed level of the circuit ground potential, and cause mutual coupling noise in the adjacent data lines DL. Is to reduce. A sense amplifier S for amplifying a read signal appearing on the data line DL corresponding to the configuration of the data line DL.
For A, a transfer MOSFET as a switch circuit, which will be described later, is also divided into an odd number and an even number, and is selected.

One of the memory cells in the block selected by the main decoder MAN-DEC is selected by the sub-decoder SUB-DEC. The sub-decoder SUB-DEC selects one word line WL in the block. Such a selection signal for one word line is formed by a gate decoder (Pre Dec). That is, the sub-decoder SUB-DEC receives the selection signal of the word line formed by the gate decoder and the selection / non-selection level formed according to the operation mode formed by the main decoder MAN-DEC,
A drive signal for selecting / non-selecting a word line in the block is formed.

A sub-decoder SUB-DEC is provided so as to sandwich the small memory mat MAT. For example, the sub-decoder SUB-DEC sandwiched between two small memory mats is
The drive signal for every other word line on both sides thereof is formed. Sub-decoder SUB-DEC distributed vertically
Form a selection signal for every other word line provided between them. In this way, the word lines of the small memory mat are alternately connected to the two sub-decoders sandwiching them.

FIG. 4 shows a schematic circuit diagram of an embodiment of the sense amplifier and its peripheral portion. Of the pair of inputs and outputs of the sense amplifier, the peripheral portion corresponding to the data line of one of the small memory mats is shown as a representative, and the circuit on the side of the other small memory mat, which is a symmetrical circuit, is partially omitted. Has been done.

In this embodiment, the sense amplifier SA is shown as a sense latch SL because it has an amplifying operation and a data holding function. The sense latch SL is composed of a CMOS inverter circuit in which inputs and outputs are cross-connected, and the CMOS inverter circuit, and the CMOS inverter circuit is selectively supplied with activation voltages VSAP and VSAN. Activated.

A pair of input / output nodes of the sense latch SL are provided in common for the MOSFET switch-controlled by the selection signal formed by the Y decoder (YG Dec) and the adjacent odd and even switch MOSFETs. And a pair of input / output lines IOL and IOR via a switch MOSFET. The switch MOSFET provided in common is switch-controlled by a selection signal formed by a Y-system predecoder (YPG Dec) provided between the sense latch trains. Thus, the Y gate is composed of two MOSFETs whose switches are controlled by the selection signals of the two Y system decoders.

In the figure, a predecoder is provided for each sense latch column corresponding to four data lines in order to facilitate understanding of the invention. As shown in the figure, the predecoder as a Y-system subdecoder is provided in a space between the sense latch rows SL for each small memory mat, in other words, in an empty area corresponding to the X-system subdecoder SUB Dec. By separating the Y-system decoder in this way, the number of selection signal lines supplied to the gate of the column switch MOSFET can be reduced. That is, the column switch M
It is necessary to make a wiring area wide by arranging a large number of selection signal lines corresponding to the number of OSFETs in parallel with the sense latch column, but the number of wirings is reduced by dividing the Y decoder into two as described above. be able to.

A precharge signal RPC is applied to the data line DL.
2 and RPC1 receive precharge MOSFE respectively
T is provided. A transfer MOSFET controlled by selection signals TR1 and TR2 is provided between the data line DL and the input / output node of the sense amplifier. The right side circuit of the sense latch SL corresponding to these MOSFETs is omitted.

Although not shown in the figure, the pair of inputs of the sense latch has an input node M set to 0V.
An OSFET is provided. As a result, the input signal is set to 0V before the amplification operation is started. The pair of inputs of the sense latch SL is the transfer MOSF.
The data lines DL01L to DL04L and the like are connected via ET. The transfer MOSFET includes odd-numbered data lines DL01L and DL03L and an even-numbered data line D.
It is divided into two corresponding to L02L and DL04L, and selection signals TR1 and TR2 are respectively supplied. Correspondingly, the gates of the precharge MOSFETs provided in the odd data lines DL01L and DL03L are supplied with the precharge voltage RPC1, and the gates of the precharge MOSFETs provided in the even data lines DL02L and DL04L are supplied with the precharge voltage. RPC2 is supplied.

In this embodiment, like the above, when one of the pair of memory mats is activated, the other is deactivated. In this inactivated memory mat, the transfer MOSFET is turned on and the corresponding data line is connected to the input of the sense amplifier, although it is inactivated. Then, as described above, on the non-active memory mat side, the precharge voltage of the data line is set low so as to be an intermediate potential between the high level and the low level of the data line of the activated memory mat. In this way, the data line of the memory mat on the inactive side is used as the reference voltage of the sense amplifier.

Although not particularly limited, in response to the sense latch SL being composed of a CMOS latch circuit,
During a write operation, write data is held in each latch. That is, the Y gate YG is sequentially opened to set write data, and then the even-numbered and odd-numbered transfer MOSFETs are simultaneously turned on to simultaneously perform the write operation.
In accordance with such a write operation, the operating voltage of the sense amplifier is switched to a voltage such as 4V corresponding to the write voltage. On the other hand, at the time of read operation and write verify, even-numbered and odd-numbered data lines are alternately activated in a zigzag pattern except for the first memory cycle, thereby enabling pipeline continuous access.

FIG. 5 shows a layout diagram in the direct peripheral portion of the memory mat of one embodiment of the batch erasing type nonvolatile memory device according to the present invention. Sense latches SL are arranged vertically in the central portion of the vertically long area. Two memory mats are provided sandwiching the row of sense latches SL. The memory mats divided into the above two are small memory mats MAT0L to MAT7L and MA, respectively.
It is composed of T0R to MAT7R. Small memory mat M
Memory mats for redundant data lines and management bits are provided above the AT0L and MAT0R. The redundancy data line of this memory mat is the small memory mat MAT0.
Those corresponding to L to MAT7L and MAT0R to MAT7R are collected and formed here.

As in this embodiment, by not providing redundant data lines for each of the memory mats MAT0L to MAT7L and MAT0R to MAT7R one by one, the management bits are stored in one memory mat. Since a certain storage area can be secured together with the storage area, the layout can be simplified. Note that the management bit is specified by one word line,
It is configured integrally with normal data by physically connecting it at the same address. The management bit is provided with a parity bit for ECC, a bit for recording a rewriting history, and the like.

X-system sub-decoders SUB-Dec are arranged on both sides of the small memory mat. Decharge MOSFE is placed between the small memory mat and the periphery of the left chip.
A T (DMOS) and a source MOSFET (SMOS) are provided. The main decoder (Ma
in Dec) is arranged. A gate decoder (Pre Dec) is provided at the upper left end of the gate decoder, and a driver circuit for driving the DMOS and SMOS is provided below the gate decoder.

The above-mentioned Y gate is also included in the sense latch SL of FIG. A Y-system decoder YG Dec is arranged on the upper portion corresponding to the Y gate portion, and the X-system sub-decoder SUB D is provided between the sense latches SL.
A predecoder YPG Dec as a Y-system sub-decoder is provided in a portion corresponding to ec.

FIG. 6 is a block diagram of an embodiment of a read control system in the batch erase type nonvolatile memory device according to the present invention. In this embodiment, a random access system for high speed byte access and a serial access system for high speed access of a large amount of data are provided.

Y address buffer (Y Address Buf
fer) takes in the address signal input from the external terminal Ai in the random access mode, and receives the output signal of the binary counter (Binary Counter) in the serial access mode (serial address generator). The address signal thus formed is taken in. The binary counter is a pulse CU formed by a timing generator (Timing Generator) based on the serial clock SC.
The count output is formed by counting P.

As described above, in the serial access mode, the address signal is internally formed. Therefore, by inputting the count-up signal to the redundancy comparison in the immediately preceding cycle, access to the address corresponding thereto is made. In this case, if there is a defect, the redundant circuit is switched to the redundant circuit before the defect, thereby enabling high-speed access.

The determination of the serial access mode and the random access mode is made by the command control circuit (Commmand Control), and the serial control signal SB and the random control signal RB are formed. This command control includes a write enable signal /
At a predetermined timing designated by WE, the signal Di is inputted from a data terminal (not shown) to designate the operation mode.

The main amplifier MA is used for both the serial access and the random access as described above to simplify the circuit. As will be described below, when the random access mode is entered by the signal RB, the Y-system timing generation circuit (Timing)
Signals PIO and DIO are generated by the generator to activate the current sense circuit. At this time, the sense amplifier (or sense latch) is not involved in random access because the activation signal is not formed and the output is in the high impedance state. When the serial access mode is entered by the signal SB, the signals PIO, DI are generated by the Y-system timing generation circuit (Timing Generator).
No O is generated and the current sense circuit remains inactive. At this time, the sense amplifier (or sense latch) performs an amplification and holding operation of a signal corresponding to one word line when an activation signal is formed.

FIG. 7 shows a circuit diagram of an embodiment of a Y-system sense path in the batch erase type nonvolatile memory device according to the present invention. The memory part is a single memory MOSFE
Only T and its associated MOSFETs are shown as representatives.

The word line WL to which the storage MOSFET on the sense side is connected and the selection signals STDL and STSL to which the gate of the selection MOSFET is connected are set to a predetermined selection level. On the other hand, the reference (Ref
erence) side storage MOSFET is connected to the word line and the selection MOSFET gate is connected to the selection signal ST
DR and STSR are set to the ground potential VSS of the circuit. That is, the read signal to the data line DLL on the selected side is amplified and held by the sense latch using the precharge voltage applied to the data line DLR on the non-selected side as a reference voltage. The data lines DLL and DLR correspond to the left and right memory mats.

The holding voltage of the sense latch is connected to the input / output lines IOL and IOR through a column switch MOSFET switch-controlled by the Y decoder selection signal YG and a switch MOSFET switch-controlled by the predecoder selection signal YPG. It This input / output line I
The OL and IOR are provided with MOSFETs which are controlled by the equalize signal EQ and supply the precharge voltage VIO to the input / output lines IOL and IOR.

In the serial access mode, the signals of the input / output lines IOL and IOR are applied to a pair of inputs of the balanced differential amplifier of the first stage composed of the differential amplifier circuits A1 and A2 through MOSFETs switch-controlled by the signal SB. Tell. The input of these first-stage circuits is an equalizing MOSFET whose switch is controlled by an equalizing signal EQ.
Is provided. The output signals of the amplifier circuits A1 and A2 forming the balanced differential amplifier are similar to each other.
It is amplified by the balanced differential amplifier composed of 3 and A4 and transmitted to the next-stage selector SEL. These balanced differential amplifiers A1 to A4 compose the main amplifier MA.

In the random access mode, the input / output lines IOL and IOR are connected to the input of the current sense amplifier CAS through the MOSFET switch-controlled by the signal RB. At this time, the sense latch SL for serial access is disabled. That is, the operating voltages VSAP and VSAN of the sense latch SL.
Is set to a fixed voltage such as IV so that the MOSFETs forming the CMOS inverter circuit do not operate. The current sense amplifier CSA is provided corresponding to the data line selected by the column switch.
In other words, the current sense amplifier CSA is provided with only a small number corresponding to the number of output terminals, so that a relatively large current can flow. Thus, in the random access mode, the selected memory cell can be read at high speed.

In the selector SEL, the read signal from the memory mat on the right side and the read signal from the memory mat from the left side are amplified by the differential amplifier circuit, so that the logic level and the signal level are reversed. For example, if the left side is used as a reference, the read signal from the left memory mat is passed through to the output latch circuit consisting of the NAND gate circuit, and the read signal from the right memory mat is crossed left and right. To the output latch circuit. The output signal of the output latch circuit is
A gate circuit whose gate is controlled by the output control signal OE, an output control circuit including an inverter circuit that inverts one output signal, and an output MOSFET including a P-channel MOSFET and an N-channel MOSFET
Is transmitted to the external terminal IO through an output buffer composed of an output circuit consisting of.

FIG. 8 shows a circuit diagram of an embodiment of the current sense amplifier CSA. FIG. 1A shows an overall circuit diagram thereof, FIG. 1B shows a reference voltage generation circuit used therefor, and FIG. 3C shows a reference voltage generation circuit used for a dummy current generation unit. 6D, a circuit diagram of the dummy current generating circuit is shown.

The current sense amplifier determines whether or not a memory current flows through the storage transistor selected from the input terminal IN. A MOS that is turned on by the signals CEB0B and RB in the random access mode
A memory current is supplied to the FET through the feedback MOSFET. MO switch-controlled by signal PIOB
The SFET forms a current for rapidly charging up a relatively large load capacitance in the data line of the selected storage MOSFET.

On the other hand, the dummy current source I has the memory M
About half the current flowing through the OSFET is made to flow. This dummy current source I uses the reference voltage VRI trimmed and adjusted by the trimming signals T1 to T3 as shown in (C) and the MOSFET M constituting the constant current source of (D).
By supplying to the gates of 1 and M2, the current value can be adjusted with respect to process variations. MOSF
ETM1 and M2 are selection MOSFs of the memory block
A narrow channel MOSFET compatible with ET is used to absorb the influence of process variations. That is, the selected storage transistor has a selection MOSFET on the drain side and a selection MOSFET on the source side.
Is provided, and the memory current is determined by the combined conductance of the selection MOSFET and the storage transistor. Therefore, by forming the dummy current I using the same MOSFET as that, it is possible to perform current sensing with high accuracy.

Regarding the operation of the above current sense amplifier, the dummy current source is not connected by the signal MS for the memory mat on the selected side. Therefore, the input terminal IN is set to the low level and the high level depending on whether or not the memory current flows. N-channel type MOSFE which receives this input voltage
An output signal is formed by being amplified by the conductance ratio between T and the P-channel MOSFET that receives the signal VCM. At this time, the output voltage is N which constitutes the current path.
The signal is fed back to the gate of the channel type MOSFET and acts to limit the signal level at the input terminal IN. As a result, the signal amplitude at the input terminal IN is limited by the feedback path as described above. This acts to limit the signal amplitude when reading a plurality of storage transistors one after another in the random access mode, and realizes high-speed reading.

Regarding the operation of the current sense amplifier, the dummy current source is connected by the signal MS for the memory mat corresponding to the non-selected side. In the memory mat on the non-selected side, since the selection MOSFET is in the OFF state as described above, the data line is in the high impedance state and the memory current does not flow, but the dummy current I flows instead. Output terminal OUT according to this dummy current
Signal level of the output signal of the selection side is high level /
It can be an intermediate level from the low level. As a result, the main amplifier differentially amplifies the output signals of the two current sense amplifiers to form a read signal.

FIG. 9 shows a timing diagram for explaining the random access mode. Memory access is started by the low level of the chip enable signal / CE. The address signal Ai is taken in, and the timing pulse ATD corresponding to the change of the address signal is formed. This causes the signal DIO to go high,
The data line is reset to low level. Then, the signal PIOB is set to the low level to start precharging the data line through the current sense amplifier. At the same time, equalization is performed on the input / output line and the main amplifier MA side by the signal EQ, and the input / output line IO is set to a predetermined bias voltage.

The selection operation of the word line WL is performed in response to the address signal Ai, and the precharge operation of the data line DL is stopped by the high level of the signal PIOB. As a result, the potential of the input / output line IO changes depending on the presence / absence of a current flowing through the storage transistor. The current sense amplifier amplifies it, and the main amplifier (OP Amp)
Is further amplified by and is formed into an output signal DOUT. Such a random access mode is basically performed by an operation similar to that of a conventional EPROM, and is 16 when read in 8-bit units.
Since only a small number of devices are provided, the operating current per device is set to a relatively large value so that high-speed reading is performed.

FIG. 10 shows a timing diagram for explaining the serial access mode. A timing diagram from the storage transistor to the sense latch is shown in (A), and a timing diagram from the sense latch to the output terminal is shown in (B).

In (A), the data line is precharged while the signal PRC1 is at the high level. In this precharge operation, the sense side is precharged to a high level and the reference side is set to a precharge potential which is an intermediate level between the high level and the low level on the sense side. Select M by high level of signals SSS and SSD
When the OSFET is turned on and the storage transistor coupled to the selected word line is turned on, the precharge voltage of the data line DL is pulled from the high level to the low level.

The signal TR1 for connecting the data line DL to the sense latch is set to the high level, and the read voltage and the reference voltage of the storage transistor are taken into the sense latch. The sense amplifier starts operating in response to the high level of the signal SAN1 and starts amplification of the read signal. When this amplified signal is increased, the signal TR1 is set to low level and the data line is disconnected from the sense latch. As a result, the data line DL having a large parasitic capacitance is disconnected, so that the high level of the internal node of the sense latch is quickly raised to the high level. As described above, the signal TR1 is set to the low level during the amplification of the sense latch to disconnect the data line DL, so that the sense latch can be speeded up and the power consumption can be reduced.

Since the sense latch and the data line DL are separated by the low level of the signal TR1 as described above, the next word is changed by the high level of the signal RPC2 in parallel with the operation up to the power supply voltage level of the sense latch. Precharging of the data line DL corresponding to the line selection operation (Phase 2) is simultaneously performed. Thereafter, the signal S
A read level appears on the data line DL corresponding to the stored information of the storage transistor due to SS and SSD. Signal TR
The read signal is transmitted to the corresponding sense latch by 2 and the amplifying operation of the sense latch is started by the signal SAN2. By disconnecting the data line DL by the low level of the signal TR2, the amplification operation of the sense latch is performed at high speed.

The signals PRC1, TR1 and SAN1 are set to an odd system, the signals PRC2, TR2 and SAN2 are set to an even system, and the amplification operation of the sense latch and the data line precharge operation of the next phase are overlapped with each other. Since it is performed, continuous access across a plurality of word lines can be performed at high speed.

As shown in (B), the data of one word line held in the sense latch as described above is generated by synchronizing with the signals YGE and YP generated in synchronization with the serial clock SC.
A column system selection operation is performed by G. At the same time, the count-up signal CUP is generated and the next column address signal is generated. The holding signal of the sense latch selected by the column-system selecting operation is output through the input / output line IO through the main amplifier (OP Amp) and the output circuit. The column-level selection circuit is reset by the low level of the serial clock SC, and is set to the high level again to output the signal of the next address.

FIG. 11 is a schematic layout diagram of the redundant circuit in the collective erase type nonvolatile memory device according to the present invention. The figure shows two small memory mats MAT.
, And memory mats for redundancy and management bits are shown as representatives. Also, what is indicated by a thick black line is a sub-decoder (SUB-Dec).

In the small memory mat MAT, the data line DL is provided with a main body memory portion and a word line relief redundant memory (WL) portion. The relief data lines are collectively provided in the same memory mat as the storage unit for the management bit. That is, as shown in FIG. 5, each small memory mat does not have a redundant data line for repairing a data line, and is provided collectively as one repair data line.

FIG. 12 shows a circuit diagram of an embodiment of the redundancy circuit for saving the data line. If the data line DL is defective, the redundancy comparison circuit sets the signal YRHITB to low level. As a result, the switch MOSFET corresponding to the predecoder on the data line DL side and the switch MOSFET for transmitting the address signal input to the YG decoder.
When T turns off, the selection operation on the main body side is prohibited. Signal Y above
The switch MOSFET corresponding to the predecoder on the redundant data line side is turned on by the low level of RHITB. Then, when the signal YR0 is set to the high level in the redundancy comparison, the switch corresponding to YG0 is turned on and the data line for relief is used. When the signal YR1 is set to the high level in the redundancy comparison, the switch corresponding to YG1 is turned on and the data line for relief is used.

FIG. 13 shows a circuit diagram of an embodiment of the redundancy circuit for relieving the word line. If the word line WL is defective, the redundancy comparison circuit sets the signal XRHITB to low level. As a result, the switch MOSFET for transmitting the address signal input to the predecoder (gate driver) of the word line is turned off, and the selection operation on the main body side is prohibited. When the signal XR0 or XR1 is set to the high level in the redundancy comparison, the selection signal is supplied to the sub decoder on the redundancy side. The sub-decoder on the redundant side is provided with the signal XRH.
The ITB is activated by supplying power with the low level. As a result, the redundant word line is selected. The sub-decoder on the main body side is provided with the signal XRHITB.
The word line on the main body side is not selected because it is in the non-operation state due to the low level.

FIG. 14 is a schematic circuit diagram of an embodiment of the collective judgment circuit provided in the collective erase type nonvolatile memory device according to the present invention. A circuit on the memory mat side is shown in (A), and a determination circuit is shown in (B). As shown in (A), a pair of input / output nodes of the sense latch is provided with a gate-connected MOSFET, a source connected to the ground potential of the circuit, and a drain connected in common to form a wired MOSFET.

Although not particularly limited, the MOSFETs are provided corresponding to the odd number side and the even number side in response to performing the selection operation separately for the odd number data line and the even number data line as described above. As shown in (B), the signal with the wired logic of the drain is determined by the same current sensing as described above. That is, a MOS with a common drain
If any one of the FETs is turned on, it is determined by current sensing that they do not match and the output signal OUT is formed.

For example, if the potential of the data line DL is set to low level when the stored information in the memory is logic "1", the low level is taken into the sense latch. At the end of writing and when all "1", MOSF on the sense side
All ETs are turned off. On the contrary, when all are "0", all the MOSFETs on the reference side are turned off. From this, by selecting either the sense side or the reference side, all "1" and "0" can be determined respectively.

FIG. 15 shows a circuit diagram of an embodiment of the collective judgment circuit. As described above, since the data line of the memory mat is divided into an odd number and an even number, and the memory mat is provided on the left and right around the sense latch, it is possible to correspond to four kinds of wired logic.
Two current sense outputs are available. That is, the even output MATRVEN of the right mat and the even output MA of the left mat
TLEVEN and odd matte output MATRODD on the right mat
And odd-numbered output MATLODD of the left mat are selected so that both nodes N1 and N2 are at a high level in accordance with the read address, so that all "1" or "0" and a ticker pattern It is possible to determine a pattern of "1" and "0" such as. If there is a defective data line, desired data may be set using the set MOSFET provided in the sense latch.

By using this collective determination circuit, all "0"
Since writing is the same as the erased state, it is possible not to write all "0". In other words, the determination is made before writing, and if the write data is all "0", the writing is omitted and the write end signal is output. Further, the self-determination of the ticker pattern as described above can be performed, so that the test time can be significantly shortened. Here, for convenience, erase is set to logic "0" (high threshold voltage), and writing is set to "1" (low threshold voltage). However, it goes without saying that if the same data, it is a determination circuit.

FIG. 16 is a block diagram of an embodiment of a memory device using the batch erase type nonvolatile memory device according to the present invention. In the memory device of this embodiment, the flash memory as in the above embodiment is used for the data storage section. In the writing and reading of data in the flash memory, an error / detection of data is performed by an ECC circuit configured by a dedicated LSI.

The sector management table is composed of the EEPROM or the like. Although not particularly limited, this sector management table is for performing writing, reading, and erasing in units of one word line and treating it as one sector. By rewriting the data in units of sectors, the number of times of rewriting (the number of times of writing or the number of times of erasing) is counted, and when it exceeds an allowable value, access to the sector is prohibited and reliability is increased.

The write operation to the flash memory is
It takes a longer time than the read time. Therefore,
The write operation from the host system or the like is not directly performed to the flash memory, but the write data is input to the write buffer. Although not particularly limited, the write buffer fetches the storage data of one sector having the storage capacity of one sector. The write data fetched in the write buffer is sequentially written in byte units to the sense amplifier of the flash memory. When the data for one sector is written in the sense amplifier, the write operation as described above is started.

In the read operation, when the head address is supplied to the flash memory as described above, the data for one sector has an internal address generation circuit (address counter).
Are output serially in 1-byte units according to the order of the addresses formed by.

The above-described write operation, read operation, and control of the sector management table are performed by a one-chip microcomputer (one-chip microcomputer).
The memory device of this embodiment is made compatible with conventional hard memory devices and floppy disk memory devices, and is connected to a standard bus via a standard bus interface unit. Although not shown, this standard bus includes a central processing unit CPU, a main memory,
A cache memory (first cache memory, second cache memory) or the like is connected.

The functions and effects obtained from the above-mentioned embodiment are as follows. That is, (1) charges are injected from the substrate side to the floating gate through the tunnel insulating film to perform the erase operation due to the relative potential relationship between the control gate and the substrate, and the relative relation between the control gate and the drain is obtained. Memory transistors are arranged in a matrix at the intersections of the word lines and the data lines to perform a write operation by discharging charges from the floating gate to the drain side through the tunnel insulating film according to the potential relationship. A sense latch circuit is provided corresponding to the data line of the memory array to perform an erase operation in units of word lines to which the control gates are coupled, and a write operation and a read operation in units of word lines via the sense latch circuits. Random access reading for each selected data line By providing an output path, it is possible to efficiently rewrite data consisting of multiple bits in word line units, so speed up memory access per unit data and achieve compatibility with a magnetic memory device as a file memory. In addition, it is possible to directly read a small amount of data by random access, and thus it is possible to obtain the effect of improving usability.

(2) The above-mentioned sense latch circuit and current sense circuit should be selectively controlled in operation according to the read mode in word line units and the read mode in selected data line units. As a result, the effect that the operating current can be used efficiently can be obtained.

(3) A pair of input / output of the sense latch circuit is provided with a wired logic MOSFET which is switch-controlled by a holding signal of the latch circuit, and data match / mismatch is determined from the drain output of the MOSFET. By doing so, it is possible to confirm the erasure and shorten the test, and it is possible to obtain the effect of improving usability.

(4) Wired logic MOSFE
T is divided into odd-numbered ones and even-numbered ones,
By combining each wired logic output and its inverted signal through a multiplexer, a self-determination function such as a test pattern such as a checker pattern composed of all "0", all "1" or "0" and "1". Can be provided.

(5) A pair of memory arrays are provided on both sides of the sense latch, and the data lines of the memory array are extended so as to extend on both sides of the sense latch, and the word lines are extended so as to be orthogonal thereto. At the same time, a plurality of the memory array pairs are provided corresponding to the data terminals in a one-to-one correspondence, and the redundant data lines are collectively arranged as a pair of memory arrays for the memory array consisting of the plurality of pairs. The effect that the layout can be simplified can be obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention of the present application is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Needless to say. For example, the memory MOSFET may have any configuration as long as it is erased and programmed by the tunnel current as described above.
INDUSTRIAL APPLICABILITY The present invention can be widely used as a batch erasing type nonvolatile memory device in which erasing and writing are performed by tunnel current.

[0085]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, due to the relative potential relationship between the control gate and the substrate, charges are injected from the substrate side to the floating gate through the tunnel insulating film to perform an erase operation, and the relative potential between the control gate and the drain is compared. Depending on the relationship, memory transistors are formed by arranging memory transistors, which perform a write operation by discharging charges from the floating gate to the drain side through the tunnel insulating film, in a matrix at the intersections of the word lines and the data lines. A sense latch circuit is provided corresponding to the data line, and an erase operation is performed in a unit of a word line to which the control gate is coupled, and a write operation and a read operation are performed in a unit of a word line via the sense latch circuit. Read access for random access for each selected data line. By providing the above, it is possible to efficiently rewrite data consisting of a large number of bits in units of word lines, so that it is possible to speed up memory access per unit data and to achieve compatibility with a magnetic memory device as a file memory. At the same time, a small amount of data can be directly read by random access, which improves usability.

The sense latch circuit and the current sense circuit operate by selectively performing operation control according to the read mode in word line units and the read mode in selected data line units. The current can be used efficiently.

A wired logic MOSFET whose switch is controlled by a signal held by the latch circuit is provided at a pair of inputs and outputs of the sense latch circuit.
By determining whether the data matches or does not match from the drain output of the FET, the erase confirmation and the test can be shortened and the usability is improved.

The above-mentioned wired logic MOSFETs are divided into odd-numbered MOSFETs and even-numbered MOSFETs, and the wired logic outputs and their inverted signals are combined through a multiplexer, whereby all "0" s and all "1s" are combined. It is possible to provide a self-determination function such as a test pattern such as a checker pattern composed of "or" or "0" and "1".

A pair of memory arrays are provided on both sides of the sense latch, and the data lines of the memory array are extended so as to extend to both sides of the sense latch.
The word lines are extended so as to be orthogonal to the word lines, and a plurality of the memory array pairs are provided corresponding to the data terminals in a one-to-one correspondence. The layout can be simplified by arranging the memory array as the memory array.

[Brief description of drawings]

FIG. 1 is a partial block diagram showing an embodiment of a batch erasing nonvolatile memory device according to the present invention.

FIG. 2 is a remaining block diagram showing an embodiment of a batch erase nonvolatile memory device according to the present invention.

FIG. 3 is a schematic circuit diagram showing an embodiment of the memory mat of FIG. 1 and its peripheral portion.

FIG. 4 is a schematic circuit diagram showing one embodiment of the sense amplifier of FIG. 1 and its peripheral portion.

FIG. 5 is a layout diagram of a memory mat direct peripheral portion showing an embodiment of a batch erasing type nonvolatile memory device according to the present invention.

FIG. 6 is a block diagram showing an embodiment of a read control system in the batch erase nonvolatile memory device according to the present invention.

FIG. 7 is a circuit diagram showing an embodiment of a Y-system sense path in the batch erase nonvolatile memory device according to the present invention.

8 is a circuit diagram showing an embodiment of the current sense amplifier CSA of FIG.

FIG. 9 is a timing diagram for explaining a random access mode of the batch erase type nonvolatile memory device according to the present invention.

FIG. 10 is a timing diagram for explaining a serial access mode of the batch erase nonvolatile memory device according to the present invention.

FIG. 11 is a schematic layout diagram of a redundant circuit in the batch erase nonvolatile memory device according to the present invention.

12 is a circuit diagram showing an example of a redundancy circuit for relieving data lines in FIG.

13 is a circuit diagram showing an embodiment of a redundancy circuit for repairing the word line of FIG.

FIG. 14 is a schematic circuit diagram showing an embodiment of a batch determination circuit provided in the batch erase type nonvolatile memory device according to the present invention.

FIG. 15 is a circuit diagram showing an embodiment of a batch determination circuit provided in the batch erase type nonvolatile memory device according to the present invention.

FIG. 16 is a lock diagram showing an embodiment of a memory device using the batch erasing type nonvolatile memory device according to the present invention.

[Explanation of symbols]

MAT, MAT0L to MAT7R ... Small memory mat, S
UB-DEC ... Sub-decoder, MAN-DEC ... Main decoder, SL ... Sense latch circuit, YPGDEC ... Y
Predecoder, YG Dec ... Y decoder, CSA ... Current sense amplifier.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical indication location H01L 27/115 7210-4M H01L 27/10 434 (72) Inventor Atsushi Nozoe 2326 Imai, Ome, Tokyo Address Hitachi, Ltd. Device Development Center (72) Inventor Takashi Yamazaki 2326 Imai, Ome-shi, Tokyo Address Hitachi, Ltd. Device Development Center (72) Inventor Masatsugu Kubo 5-20 Kamimizumotocho, Kodaira-shi, Tokyo No. 1 Hitate Super LSI Engineering Co., Ltd. (72) Inventor Michitaro Kanemitsu 5-20-1 Kamimizuhoncho, Kodaira-shi, Tokyo Hitate Super LSI Engineering Co., Ltd. (72 ) Inventor Takayuki Kawahara 1-280 Higashi Koigokubo, Kokubunji City, Tokyo Hitachi Central Research Laboratory (72) Inventor Yoshinobu Nakagome 1-280, Higashi Koigokubo, Kokubunji City, Tokyo Inside Central Research Laboratory, Hitachi, Ltd.

Claims (6)

[Claims] 1. A relative potential relationship between a control gate and a substrate causes an electric charge to be injected from a substrate side to a floating gate through a tunnel insulating film to perform an erasing operation. A memory array in which storage transistors that perform a write operation by discharging charges from the floating gate to the drain side through the tunnel insulating film due to a potential relationship are arranged in a matrix at intersections of word lines and data lines; A sense latch circuit provided corresponding to the data line of the array and a current sense circuit for determining the current of the memory transistor connected to the selected data line are provided, and the control gate is connected in units of word lines. Erase operation, and write operation and read operation in word line units via the sense latch circuit. A batch erasing non-volatile memory device, which is capable of performing a read operation or a read operation by random access in units of data lines selected via the current sense circuit. 2. The sense latch circuit and the current sense circuit are selectively subjected to operation control in accordance with a read or write mode in word line units and a read mode in selected data line units. The batch erasing type non-volatile memory device according to claim 1, wherein: 3. A read mode for increasing the speed of reading from the memory array by passing a large current through a small number of current sense circuits, and a read mode for obtaining a read signal having a large block length by operating a large number of sense latches. The batch erasing non-volatile memory device according to claim 1, further comprising a mode. 4. A pair of input and output of the sense latch circuit is provided with a wired logic MOSFET which is switch-controlled by a signal held by the sense latch circuit, and data match / mismatch can be determined from the drain output of the MOSFET. The method according to claim 1, which is performed.
Alternatively, the batch erasing type nonvolatile memory device according to claim 2. 5. The wired logic MOSFET comprises:
7. An odd-numbered one and an even-numbered one are divided, and each wired logic output and its inverted signal are combined through a multiplexer to enable determination of a self-test pattern. Four
All-in-one non-volatile memory device. 6. A pair of memory arrays are provided on both sides of the sense latch, and the data lines of the memory array are extended to extend on both sides of the sense latch and the word lines are orthogonal to the data lines. A plurality of memory array pairs are provided correspondingly to the data terminals in a one-to-one correspondence. The batch erasable non-volatile memory device according to claim 1, wherein