JPH06342598A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To prevent increase in a chip area and to speed up a reading operation while changing from a standby condition to an operating condition by eliminating an equalizing circuit and providing a reference potential lowering means. CONSTITUTION:Memory cells, which consist of nonvolatile transistors, are arranged in a matrix form in a memory cell array 1 and the dummy cell of a dummy cell array 3 has a transistor construction. A reading potential generating means 6 applies a prescribed potential to a selected memory cell and generates a reading potential corresponding to the data stored in the memory cell based on the current that flows in the memory cell. A reference potential generating means 8 applies a prescribed potential to the dummy cell of the dummy cell array 3 and generates a reference potential based on the current which flows in the dummy cell. A reference potential lowering means 9 lowers the reference potential for a constant duration when a prescribed time is elapsed after a standby condition is changed to an operating condition. An amplifying means 10 compares the reading out potential with the reference potential, amplifies the output which corresponds to the result of the comparison and outputs the signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device capable of erasing and writing data.

[0002]

2. Description of the Related Art So-called UV-EPRO, which erases data by irradiating it with ultraviolet rays and electrically writes the data
M (Ultraviolet-Erasable and Programmable Read Onl
y Memory) or an EEPROM (Electrically Erasable and Pr) that electrically erases and writes data.
grammable Read Only Memory), the read potential V corresponding to “1” or “0” of cell data in the sense amplifier circuit when reading data.
"1" or "0" data is read according to the result of comparison and comparison between _S (respectively referred to as V _S1 and V _{SO as} required) and a reference potential (referred to as V _R ).

EEPROM for electrically erasing data
14A is a plan view of a nonvolatile transistor used as the memory cell of FIG. 14A, and FIG. 14B is a sectional view taken along line AA ′ of FIG. 14A.

This transistor is formed of a two-layer polycrystalline silicon structure. The first-layer polycrystalline silicon layer constitutes a floating gate 21, and the second-layer polycrystalline silicon layer constitutes a control gate 23. Has been done. Also, FIG.
4 (a) and FIG. 14 (b), 24 is a source, 2
Reference numeral 5 is a drain, 27 is a silicon substrate, 22 is a contact hole, 28 is a data line formed of aluminum (Al), and is connected to the drain 25 through the contact hole 22. Data writing, reading and erasing operations in the memory cell having such a structure will be briefly described below.

In the write operation, the drain potential is set to 8V, the control gate potential is set to 12V, and the source voltage is set to 0V, and hot electrons are applied to the floating gate.
on). The read operation is
This is performed by setting the control gate potential to 5V, the drain potential to 1V, and the source potential to 0V. At this time, when the storage data of the memory cell is "0" (write state), almost no cell current flows between the source and the drain, and when the storage data is "1" (erase state), about 100 μA is applied between the source and the drain. Cell current flows.

In the erase operation, the control gate potential is 0V, the drain potential is floating, and a high potential, for example, 12V is applied to the source. At this time, the electrons in the floating gate are extracted by the source due to the tunnel effect.

The overall structure of a conventional nonvolatile semiconductor memory device including such a nonvolatile memory cell and sense amplifier will be described with reference to FIG. In FIG. 15, the memory device includes a memory cell array 1 in which a large number of memory cells are arranged in a matrix, and dummy cells having the same structure as a plurality of memory cells provided in one column in the column direction of the memory cell array 1. A dummy cell array 3, a read potential generating circuit 6 for applying a predetermined potential to a selected memory cell at the time of data reading and generating a read potential according to a cell current of the selected memory cell, and a data reading At the same time, a predetermined drain potential is supplied to the drain of the dummy cell selected at this time, and a reference potential generating circuit 8 for generating a reference potential at the time of data reading and the corresponding nodes of the reading and reference potential generating circuits 6 and 8 are equalized. And the read voltage supplied from the read potential generating circuit 6. And a current mirror type amplifier circuit 10 which compares the reference potential supplied from the reference potential generation circuit 8 with the reference potential and sends out a potential corresponding to the data of the selected memory cell to an output circuit (not shown). I have it.

The read potential generating circuit 6, the reference potential generating circuit 8 and the current mirror type amplifying circuit 10 constitute a conventional sense amplifier, and this sense amplifier is specifically constructed as shown in FIG. 16, for example. .

In FIG. 16, P1 to P23 are P channel enhancement transistors, and D1 to D12.
Is an N-channel depletion transistor, and N
1 to N24 are N-channel enhancement transistors, and I1 to I12 are N-channel type transistors having a threshold value near zero volt (V). In the figure, the read potential generation circuit 6 includes transistors P1, D1, I1 connected in series, a transistor N1, transistors P2, D2, I2 connected in series, and transistors N2, N3, N4, N5. N6, N7, N8
And transistors P3 and P4 connected in series. A driving voltage V _CC is added to the sources of the transistors P1, P2, P3, and the transistors N1, N2, N
The sources of 4, N6, N8, I1 and I2 are grounded. The gate of the transistor D1 is connected to the connection point between the transistor D1 and the transistor I1. The drain of the transistor N1 is connected to the connection point of the transistors D1 and I1. The gate of the transistor D2 is connected to the connection point of the transistors D2 and I2. The drain of the transistor N2 is connected to the connection point of the transistors D2 and I2. The drive voltage V _CC is applied to the drain of the transistor N3, and the gates of the transistors D1 and I
1 and the source thereof is connected to the node ND ₁ . The drain of the transistor N4 is the node ND
Leak control signal S _CL connected to ₁ and supplied to the gate
Therefore, a small amount of current is passed to prevent overcharge of the data line when data “0” is read for a long time (for example, 1 μA).
degree). The transistor N5 has a drain connected to the node ND ₁ and a source connected to one end of a transfer gate provided between the read potential generating circuit 6 and the memory cell array 1, and is turned on only when reading data. The drain of the transistor N6 is connected to the node ND _1, and the drain of the transistor N8 is connected to the node ND ₂ . The node ND ₂ is connected to the node ND ₁ via the transistor N7. The drive voltage V _CC is applied to the source of the transistor P3, and the gate and drain of the transistor P4 are connected to the node ND ₂ .
Also, the transistors P1, P2, P3, N1, N2, N
The first control signal S ₁ which becomes “L” at the time of reading data is input to the gates of 6 and N 8. The gate of the transistor N5 has a third control signal *
S ₃ is supplied.

In the read potential generating circuit 6, the series circuit composed of the transistors P1, D1 and I1, the series circuit composed of the transistors P2, D2 and I2 and the transistors N3 and N7 have the optimum drain voltage of the memory cell. For example, it is kept at 1 V and the read potential V _S according to the data of the selected memory cell is set to the node ND.
₂ to the current mirror amplifier circuit 10. In addition,
The transistor P4 supplies a constant current as a load transistor of the node ND ₂ .

The read potential V _S will be described. When the data of the selected memory cell in the memory cell array 1 is at "0" level, no current flows in the memory cell and the transistors P3 and P4 are supplied to the node ND _2.
A potential of 3 V, for example, is charged via the. When the data of the selected memory cell is "1", the memory cell has 1
Since a cell current of about 00 μA flows, the potential V _SA1 of the node ND ₂ becomes, for example, about 1 V depending on the voltage division ratio between the load transistor P4 and the selected memory cell.

On the other hand, the reference potential generating circuit 8 is a copy circuit of the read potential generating circuit 6, and includes transistors P11, D11, I11 connected in series, a transistor N11, and a transistor P12 connected in series.
D12, I12 and transistors N12, N13, N1
4, N15, N16, N17 and N18, and transistors P13 and P14 connected in series. That is, for example, the transistor P11 of the reference potential generation circuit 8
Corresponds to the transistor P1 of the read potential generation circuit 6. A fourth control signal * S ₄ is supplied to the gate of the transistor N15.

The reference potential generating circuit 8 includes a transistor N
15 and the dummy data line DL _R , which are connected to the dummy cell and are connected to the transistors P11, D11, I11, P1.
2, D12, I12, N13, N17 keep the drain potential of the dummy cell at a predetermined potential. Also, it supplies a constant current having a reference potential V _R by the transistor P14. ND ₄ to which this reference potential V _R is output is connected to the dummy data line DL _R via the transistors N17 and N15. Since the dummy cells DC1 to DCm are erased cells, a cell current of about 100 μA flows during reading. The reference potential V _R at this time has a value which is a current ratio between the load transistor P14 and the selected dummy cell. On the other hand, this reference potential V _R is
It is necessary to set the intermediate potential between the read potential V _S when the data “0” is stored in ij and the read potential V _S when the data “1” is stored. Therefore, the load transistor P14 of the reference potential generation circuit 8 is a transistor having a larger amount of current than the corresponding transistor P4 of the read potential generation circuit 6.

The current mirror type amplifier circuit 10 includes a differential amplifier pair composed of transistors P21, P22, P23, N22 and N23, a transistor N24 and an inverter I.
It has V1, IV2 and IV3. Transistor P
The gate of 22 is a node N to which the read potential V _S is output.
It is connected to D _2, and the gate of the transistor P23 is connected to the node ND ₄ which outputs the reference potential V _R. The drain of the transistor N24 is connected to the drains of the transistors P22 and N22, and the source is grounded. Further, the inverters IV1, IV2 and IV3 are connected in series and invert the potential at the connection point of the transistors P22 and N22 and send it to the output circuit. Therefore, the read potential V _S and the reference potential V _R are respectively supplied to the transistors P22 and P23 of the differential pair, and the output D _B is sent to the output circuit 12 depending on the magnitude of the values. The output D _B becomes “1” when “0” data is read, and becomes “0” when “1” data is read.

The node ND ₁ and the node ND ₃ are connected by a transistor N20, and the node ND ₂ and the node ND ₄ are connected by a transfer gate composed of transistors P20 and N21. These transistors form an equalizing circuit 7. is doing. The equalizing circuit 7 includes a first equalizing section including a transistor N20 for equalizing a node ND ₁ and a node ND ₃ and a second equalizing section including transistors N21 and P20 for equalizing a node ND ₂ and a node ND _4. And are equipped with.

Further, in such a semiconductor memory device, in the standby state where reading is not normally performed, the first external control signal S ₁ which becomes "H" in the standby state is usually provided in order to suppress power consumption. , The gates of the transistors N1, N2, N6, N8 of the read potential generating circuit 6 and the transistors N11, N12, N16, N1 of the reference potential generating circuit 8.
8 is applied to the gates of each node ND ₁ , ND ₂ , ND
₃ and ND ₄ are grounded. At this time, the inverted signal * S ₂ of the second signal given to the gates of the transistors P21 and N24 and the gates of the transistors N20 and N21 of the current mirror type amplifier circuit 10 is at the “H” level, and the transistor P20. control signal S ₂ second given to the gate of is "L" level.

Each signal * CE, S ₁ , WL, * S ₂ , D ₀ , V _S , V when the standby state transits to the read state
The change in _R is shown in FIG. In FIG. 17, the first control signal S is received in response to the chip enable signal * CE from the outside.
_{When 1} changes from “H” to “L”, the read potential generating circuit 6 and the reference potential generating circuit 8 are in the operating state, and the data D ₀ is output from the current mirror amplifier circuit 10 to the output circuit (not shown). Also, the word line potential W
It takes time for L to rise due to the capacity of the memory cell, and normal reading cannot be performed during this period. On the other hand, since the drain potential is charged from the transistor P4 to the selected data line regardless of the data in the memory cell, a current flows and the level of the read potential V _S becomes low. Similarly, the dummy data line DL _R is also initially charged. As described above, since the amount of current of the transistor P4 is smaller than that of the transistor P14, it takes more time to charge the memory cell side than the reference potential side. In order to shorten the charging time on the memory cell side, the signal * S ₂ is changed from “H” to “L” after a lapse of a certain time after the signal S ₁ is changed to “L”.
Then, by changing the signal S ₂ from “L” to “H”, the levels of the nodes ND ₂ and ND _{4 and} the levels of the nodes ND ₁ and ND ₃ are equalized (equalized), and the initial charging is performed. Hastened. After that, the signal * S
_{When 2} changes from "L" to "H", the current mirror type amplifier circuit 10 is driven and cell data is output to speed up reading.

[0018]

In such a conventional nonvolatile semiconductor memory device, when "0" is read when the chip enable signal * CE is changed from "H" to "L", the data is read. When the signals * S ₂ and S ₂ change when the initial charge to the line is insufficient, the levels of the read potential V _S and the reference potential V _R are inverted (time t _{1 in} FIG. 17).
~t between the _two). Therefore, there is a problem that the operation becomes "1" reading to "0" reading and the reading becomes slow.

[0019] Further, in order to speed up the initial reading, which equalizes node ND ₂ and the reference node ND ₄ of potential generation circuit 8 read potential generation circuit 6. Therefore, when a plurality of read potential generating circuits 6 are provided, the same number of reference potential generating circuits 8 and dummy cell arrays 3 are required, which causes a problem of increasing the chip area.

The present invention has been made in consideration of the above circumstances, and it is possible to prevent an increase in the chip area as much as possible and to perform high-speed reading when the standby state is changed to the operating state. It is an object to provide a nonvolatile semiconductor memory device.

[0021]

According to a first aspect of the present invention, there is provided a nonvolatile semiconductor memory device comprising a memory cell array in which memory cells composed of nonvolatile transistors are arranged in a matrix, a dummy cell having a transistor structure, and a selected memory. A predetermined potential is applied to a cell and a read potential generating means for generating a read potential corresponding to the data stored in the memory cell based on the current flowing in the memory cell, and a predetermined potential are applied to the dummy cell, Reference potential generating means for generating a reference potential based on the flowing current, reference potential lowering means for lowering the reference potential for a predetermined time when a first predetermined time has elapsed after changing from the standby state to the operating state, and the standby state Second after changing to operating state
After a predetermined time has passed, the read potential and the reference potential are compared with each other, and an amplifying means for amplifying and outputting the output according to the comparison result is provided.

In the non-volatile semiconductor memory device according to the second aspect of the present invention, a memory cell array in which memory cells made of non-volatile transistors are arranged in a matrix, and dummy cells made of non-volatile transistors provided in each row of the memory cell array are arranged in columns. A dummy cell array arranged in a row, and a read potential generating means for applying a predetermined potential to the selected memory cell and generating a read potential corresponding to the data stored in the memory cell based on the current flowing in the memory cell. A reference potential generating means for applying a predetermined potential to the dummy cell and generating a reference potential based on a current flowing through the dummy cell; and a first potential after changing from a standby state to an operating state.
Read potential initial charging means for increasing the read potential for a predetermined time (rapid charging) when a predetermined time has elapsed, and the read potential and the reference potential after the second predetermined time has elapsed after changing from the standby state to the operating state. And an amplifying unit that amplifies and outputs an output according to the comparison result.

[0023]

According to the nonvolatile semiconductor memory device of the first aspect of the present invention thus configured, the reference potential is lowered by the reference potential lowering means for a certain period of time when a predetermined time has elapsed after the storage device was operated from the standby state. To be made. This makes it possible to minimize the delay in reading due to the initial charging. Further, unlike the conventional case, since the read potential side and the reference potential side are not equalized, the reference potential generating means can be shared by a plurality of read potential generating means, and the chip area can be made as small as possible. it can.

According to the nonvolatile semiconductor memory device of the second aspect of the present invention thus configured, the reference potential is lowered by the reference potential lowering means when a predetermined time has elapsed after the memory device changed from the standby state to the operating state. Decrease for a certain period of time. Alternatively, the read potential is read by the potential initial charging means for a certain period of time and increased (rapid charge). This makes it possible to minimize the delay in reading due to the initial charging. Further, unlike the conventional case, since the read potential side and the reference potential side are not equalized, the reference charge generating means can be shared by a plurality of read potential generating means, and the chip area can be made as small as possible. it can.

[0025]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A preferred embodiment of a nonvolatile semiconductor memory device (hereinafter, also referred to as a memory device) according to the present invention will be described in detail below with reference to FIGS.

First, a storage device according to a first embodiment of the present invention will be described with reference to FIGS. The memory device according to the first embodiment is obtained by removing the equalizing circuit and providing reference potential lowering means (circuit) 9 in the block diagram of the conventional memory device shown in FIG. Other configurations, that is, memory cell array 1, dummy cell array 3, read potential generating circuit 6, reference potential generating circuit 8
The current mirror type amplifier circuit 10 is similar to that of the conventional memory device shown in FIG.

A concrete configuration will be described with reference to the detailed circuit diagram shown in FIG. 2. The memory device of the first embodiment is shown in FIG.
In the conventional memory device shown in FIG. 6, transistors N20 and N2 are provided for equalizing the nodes ND ₁ and ND ₃ and the nodes ND ₂ and ND _4.
The equalizing circuit 7 made up of P1, 1 and P20 is deleted, and the reference potential lowering circuit 9 made up of N-channel enhancement type transistors N30 and N31 connected in series is provided.
And a signal S ₅ is added to the gates of the transistors P21 and N24 of the current mirror type amplifier circuit 10. Transistor N3 of this reference potential lowering circuit 9
The drain of 0 is connected to the node ND ₃ of the reference potential generation circuit 8, and the signal * S ₂ which becomes “L” after a lapse of a fixed time after the memory device is in operation is added to the gate. The drain of the transistor N31 is connected to the source of the transistor N30, the source is grounded, and the drive voltage V _CC is applied to the gate. Therefore, the reference potential lowering circuit 9 lowers the reference potential V _R for a certain period of time after changing to the operating state. The current mirror type amplifier circuit 1
The third control signal S ₅ given to the gates of the transistors P21 and N24 of 0 is a signal which becomes “L” after the signal * S ₂ has changed to “L” and a certain time has elapsed.

FIG. 3 shows the configuration of a non-volatile semiconductor memory device using such non-volatile transistors as memory cells. In FIG. 3, the memory cell array 1 has m · n memory cells CA11, ... CA arranged in a matrix.
It is composed of mn. Each memory cell CAij (i =
1, ... M, j = 1, ... N) are non-volatile transistors composed of a source, a drain, a floating gate, and a control gate, as shown in FIGS. The control gates of the n memory cells CAk1, ... CAkn arranged in the same row (for example, k row) have a corresponding one word line W of the m word lines WL1 ,.
Commonly connected to Lk. Also, the drains of the m memory cells CA1j, ... CAmj arranged in the same column (for example, j column) are commonly connected to the corresponding one data line DLj of the n data lines DL1 ,. It The source of each memory cell CAij is supplied with the potential V _M (high potential during erase, V _SS otherwise) output from a cell source potential supply circuit (not shown).

The m word lines WL1, ... WL
The selection of m is performed by the row decoder 2, and one word line corresponding to the row address is selected. On the other hand, n
The column decoder 4 selects the data lines DL1, ..., DLn of the book. The column decoder 4 selects the data line D corresponding to the column address from the data line D.
This is performed by selecting the transfer gate CTj connected to Lj (j = 1, ... N). That is, the data line is selected by turning on only the transfer gate connected to the data line corresponding to the column address. Further, each data line DLj (j = 1, ... N) is connected to the read potential generating circuit 6 via the corresponding transfer gate CTj. This read potential generation circuit 6
Applies a predetermined potential (for example, 1 V in the memory cell including the transistor shown in FIGS. 14A and 14B) to the drain of the selected memory cell at the time of data reading, and at the same time, the cell of the selected memory cell is A read potential V _S according to the current is generated. The read potential V _S is sent to the current mirror type amplifier circuit 10 as input potentials corresponding to the cell data values “1” and “0”, respectively.

On the other hand, the dummy cell array 3 is composed of m dummy cells DC1, ... DCm. The dummy cell DCi (i = 1, ... M) is a nonvolatile transistor similar to the memory cell CAij, its control gate is connected to the corresponding word line WLi, and its drain is connected to the dummy data line DL _R. The potential V _D is added to the source. The dummy data line DL _R is connected to the reference potential generation circuit 8. This reference potential generating circuit 8
A predetermined drain potential is supplied to the drain of the dummy cell selected at the time of data reading via the dummy data line DL _R, and the reference potential V _R at the time of data reading is output and sent to the amplifier circuit 10. The amplifier circuit 10 compares the reference potential V _R with the read potential V _S and sends a potential according to the data of the selected memory cell to the output circuit 12. The output circuit 12 outputs the data of the selected memory cell to the outside based on the potential sent from the amplifier circuit 10.

Next, the operation of the first embodiment will be described with reference to FIG. FIG. 4 is an operation waveform diagram at the time of reading "0" when the memory device of the first embodiment is in the operating state. In FIG. 4, a signal * CE is a signal indicating that the memory device is in an operating state, and is, for example, a chip enable signal. When the memory device receives this signal * CE, the first control signal S ₁ for operating the memory device changes from "H" to "L". After that, the word line WL for selecting the memory cell rises. At this time, the load transistor N3 of the node ND ₁ and the load transistor N13 of the node ND ₃ each start initial charging. In addition, the second control signal * S at this time
₂ is an "H" level, and the level of the reference potential V _R is lowered by the reference potential lowering circuit 9.

On the other hand, on the memory cell side, the data line DL _S is charged by the load transistor P4. As the charging progresses, the amount of current decreases, the read potential V _S rises,
It is higher than the level of the reference potential V _R. Where the signal *
When S ₂ is changed from “H” to “L”, the transistor N30 of the reference potential lowering circuit 9 is turned off and the reference potential V _R is determined by the cell current of the dummy cell. Further, with respect to the read potential V _S , charging is continued up to the level at which the data “0” is read. After the difference between the level of the reference potential V _{R and} the level of the read potential V _S becomes sufficiently large, the fifth
Control signal S ₅ changes from “H” to “L”, the current mirror type amplifier circuit 10 is driven, and the amplifier circuit 10
"0" output D _O at the time of reading is output from.

In the initial charging when the signal * S ₂ is “H”, the level of the reference potential V _R is set higher than the read potential level at the time of “1” data reading, and “1” is set. since no data reading to the level of the reference potential V _R and the read potential V _S inverted, "1" does not become slow data reading. The level of the reference potential V _R at this time is determined by the transistor N30 of the reference potential lowering circuit 9.

As described above, according to the first embodiment,
It is possible to minimize the delay in reading due to the initial charge when the storage device is in the operating state, and it is possible to perform reading at high speed. Further, since it is not necessary to equalize, a plurality of read potential generating circuits can share the reference potential generating circuit, and the chip area can be reduced as much as possible.

In the above embodiment, the transistor N30 of the reference potential lowering circuit 9 is an N-channel enhancement type transistor, but it is also possible to use a non-volatile transistor of the same type as the memory cell CAij.

Although the control signal * S ₂ and the control signal S ₅ are different signals in the first embodiment, they may be the same signal.

Further, in the first embodiment described above, a plurality of dummy cells DCi corresponding to each word line WLi are used, but one dummy cell (which may be an N-channel transistor or a non-volatile transistor) may be used. The same effect can be obtained.

Next, a storage device according to the second embodiment of the present invention will be described with reference to FIGS.

As shown in the block diagram of FIG. 5, the memory device according to the second embodiment has the equalizer circuit removed from the block diagram of the conventional memory device shown in FIG.
The read potential initial charging means 11 is provided in parallel between the read potential generating circuit 6 and the current mirror type amplifier circuit 10. Other configurations, that is, memory cell array 1, dummy cell array 3, read potential generating circuit 6,
Reference potential generating circuit 8 and current mirror type amplifier circuit 10
Is similar to the conventional storage device of FIG.

Next, a specific configuration will be described with reference to the detailed circuit diagram shown in FIG. In the second embodiment, in the conventional storage device shown in FIG. 16, nodes ND ₁ and ND ₁ are used.
₃ , and transistors N20, N21, P2 provided for equalizing the nodes ND ₂ and ND _4.
0 is deleted, a read potential initial charging circuit 11 including P-channel enhancement transistors P30 and P31 connected in series is added, and transistors P21 and P24 of the current mirror type amplifier circuit 10 are added.
The control signal S ₅ is added to the gate of the. Drain and gate of the transistor P31 of the read potential initial charging circuit 11 is connected to the node ND _2, the drain of the transistor P30 is connected to the source of the transistor P31, the gate, after the storage device is operational, A control signal S ₂ which becomes “H” after a lapse of a certain time is added. The source of the transistor P30 is connected to the drain of the transistor P3 and the source of the transistor P4. Therefore, the read potential initial charging circuit 11 charges the read potential V _S from the transistors P30 and P31 together with the transistors P3 and P4 for a certain period of time after the memory device has changed to the operating state.

Therefore, when the signal S ₂ is "L",
Transistors P4, P31 is the load transistor of the read potential, the signal S ₂ becomes "H", only the transistor P4 becomes the load transistor. At this time, the total transistor size of the load transistors P4 and P31 is set to be equal to or smaller than the load transistor P14 having the reference potential V _R. Note that the signal S applied to the gates of the transistors P21 and N24 of the current mirror type amplifier circuit 10.
_5, after the signal S ₂ is changed to "H", the is more after a certain period of time, the "L" signal.

Next, the operation of the second embodiment will be described with reference to FIG. FIG. 7 is an operation waveform diagram at the time of reading "0" when the storage device of the second embodiment is in the operating state. In FIG. 7, a signal * CE is a signal indicating that the memory device is in an operating state and is, for example, a chip enable signal. When the storage device receives this signal * CE, the signal S ₁ for operating the storage device changes from "H" to "L". After that, the word line WL for selecting the memory cell rises. At this time, the load transistor N3 of the node ND ₁ and the load transistor N13 of the node ND ₃ each start initial charging. Further, the node ND ₄ is set to the reference potential V _R by the load transistor P14. Further, the load transistor P4, P31 causes the node ND ₂ to be rapidly charged. At this time, the read potential, since the current for initial charging of the data line flows, reference potential V initially the level of the _R is lower, the level of the reference potential V _R the amount of current when charging progresses decreases Will be higher than. Where the signal S
_{When 2} is changed from "L" to "H", the transistor P30 of the read potential initial charging circuit 11 is turned off, the charge from the load transistor P31 is stopped, and the charge is performed only from the transistor P4 to the level of the read potential. Will continue to be charged. Then, charging to the level of the reference potential V _{R and} the level of the read potential is continued. And the level of the reference potential V _R, then the difference in level of the read potential becomes sufficiently large, the signal S ₅ is "H" from "L"
The current mirror type amplifier circuit 10 is driven, and the amplifier circuit 10 outputs the output D _O at the time of reading “0”, that is, “H”.

Incidentally, "1" at the time of reading, and the load transistor P4, P31 having read potential, the reference potential V _R
Of the current ratio of the load transistor P14, the read potential is not be higher than the reference potential V _R, nor reading of data "1" is delayed.

As described above, according to the second embodiment, it is possible to reduce the delay in reading due to the initial charging of the data line when the storage device is in the operating state,
Data can be read at high speed. Further, since it is not necessary to equalize, the reference potential generating circuit 8 can be shared by a plurality of read potential generating circuits 6, and the chip area can be made extremely small.

Next, a nonvolatile semiconductor memory device according to the third embodiment of the present invention will be described in detail with reference to FIGS.

FIG. 8 is a block diagram showing a schematic structure of a memory device according to the third embodiment. In FIG. 8, the point different from the conventional memory device shown in FIG. 9 to connect the read potential generating circuit 6
Between the read circuit and the amplifier circuit 10 is a read potential initial charging means 11
Is that they are connected in parallel. Therefore, this third
The storage device of the embodiment is a combination of the features of the storage devices of the first and second embodiments. Other configurations, that is, the memory cell array 1, the dummy cell array 3, the read potential generating circuit 6, the reference potential generating circuit 8 and the current mirror type amplifying circuit 10 are substantially the same as those of the conventional memory device of FIG.

The concrete structure of the storage device according to the third embodiment is shown in FIG. As shown in FIG. 9, the concrete circuit of the memory device of the third embodiment is different from the concrete circuit of the second embodiment in that an N-channel enhancement transistor N30 connected in series to the node ND ₃ is provided. N
The reference potential lowering circuit 9 composed of 31 is added. The transistor N30 of this reference potential lowering circuit 9
The drain is connected to the node ND ₃ of the reference voltage generating circuit 8, the gate signal * S ₂ reverse-phase of the signal S ₂ is supplied. That is, the signal * S ₂ is a signal which becomes “L” after a lapse of a certain time after the memory device is in the operating state. The drain of the transistor N31 is connected to the source of the transistor N30, the source is grounded, and the drive voltage V _CC is added to the gate. Therefore, the reference potential lowering circuit 9 lowers the reference potential V _R for a certain period of time after the storage device changes to the operating state.

Next, the operation of the third embodiment will be described with reference to FIG. In FIG. 10, the read potential at the time of reading the data of "0" level is the same as in the second embodiment until a fixed time elapses (S ₂ = “L”) after the memory device is in the operating state. Load transistors P4 and P31
Is charged rapidly. At this time, the level of the reference potential V _R is lowered by the reference potential lowering circuit 9 while * S ₂ = “H”. Therefore, the read potential when reading the data of level “0” is set as the reference. It becomes possible to charge up to the potential V _R at higher speed.

The memory device according to the first to third embodiments has been described above. The memory device has a memory cell array 1 as shown in FIG. 3 of the first embodiment.
It is assumed that one dummy cell array 3 is provided and one dummy cell array 3 is provided. However, the present invention is not limited to this, and a plurality of memory cell arrays 1 and dummy cells 3 may be provided. That is, FIGS. 11 to 13 showing circuits corresponding to the first to third embodiments respectively show the memory devices of the fourth to sixth embodiments.

11 to 13, the nonvolatile semiconductor memory device according to the fourth to sixth embodiments is the same as that shown in FIG.
The memory cell array 1 and the dummy cell array 3 are divided into a plurality of parts. Also, a plurality of row decoders 2, column decoders 4, read potential generating circuits 6, reference potential generating circuits 8, current mirror type amplifier circuits 10, and word lines W corresponding to the cell array 1 are provided.
L ₁ , WL ₂ , transfer gates CT1, CT2
, CT _n , each of which has a memory section M
S ₁ and MS ₂ are configured. In such a storage device,
For each circuit in the section, for example, only the circuit in the memory section, for example, MS ₁ , which is determined by the section address, is activated. At this time, section MS
₁ of the current mirror type amplifier circuit 10 includes an output V _S of the read potential generation circuit 6, the output V _R of the reference potential generating circuit 8
And outputs the information of the selected memory cell to the common data bus DB _C. At this time, the other memory section MS ₂ is in a standby state. Therefore, the memory section selected by the section address is M
In case of changing from S ₁ to MS ₂ , section MS
It is obvious that high-speed reading can be performed by changing the circuits in ₂ from the standby state to the operating state and starting the same operation as in the first to third embodiments.

[0051]

As described in detail above, according to the nonvolatile semiconductor memory device of the present invention, even if the initial charge to the data line is insufficient, the nonvolatile semiconductor memory device operates from the standby state for a predetermined time. Both potentials are set so that the reference potential is sufficiently lower than the read potential before the time elapses, so the reference potential generation circuit can be shared and the area of the entire chip can be minimized. In addition, the read operation can be performed at high speed when the storage device changes from the standby state to the operating state.

[Brief description of drawings]

FIG. 1 is a block diagram showing a schematic configuration of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a detailed configuration of a nonvolatile semiconductor memory device according to a first example.

FIG. 3 is a block diagram showing a specific configuration of the nonvolatile semiconductor memory device according to the first example.

FIG. 4 is a timing chart for explaining the operation of the nonvolatile semiconductor memory device according to the first example.

FIG. 5 is a block diagram showing a schematic configuration of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

FIG. 6 is a circuit diagram showing a detailed configuration of a nonvolatile semiconductor memory device according to a second example.

FIG. 7 is a timing chart for explaining the operation of the nonvolatile semiconductor memory device according to the second embodiment.

FIG. 8 is a block diagram showing a schematic configuration of a nonvolatile semiconductor memory device according to a third embodiment of the present invention.

FIG. 9 is a circuit diagram showing a detailed configuration of a nonvolatile semiconductor memory device according to a third example.

FIG. 10 is a timing chart for explaining the operation of the nonvolatile semiconductor memory device according to the third example.

FIG. 11 is a block diagram showing a specific configuration of a nonvolatile semiconductor memory device according to a fourth embodiment of the present invention.

FIG. 12 is a block diagram showing a specific configuration of a nonvolatile semiconductor memory device according to a fifth embodiment of the present invention.

FIG. 13 is a block diagram showing a specific configuration of a nonvolatile semiconductor memory device according to a sixth embodiment of the present invention.

14A and 14B are a plan view and a cross-sectional view illustrating the outline of the structure of a nonvolatile transistor.

FIG. 15 is a block diagram showing a schematic configuration of a conventional nonvolatile semiconductor memory device.

FIG. 16 is a circuit diagram showing a detailed configuration of a conventional nonvolatile semiconductor memory device.

FIG. 17 is a timing chart for explaining the operation of the conventional nonvolatile semiconductor memory device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 memory cell array 3 dummy cell array 6 read potential generating means (circuit) 8 reference potential generating means (circuit) 9 reference potential lowering means (circuit) 10 (current mirror type) amplifying means (circuit) 11 read potential initial charging means (circuit) CAij (i = 1, ..., M, j = 1, ... N) Memory cell DCi (i = 1, ..., M) Dummy cell

Claims (8)

[Claims] 1. A memory cell array in which memory cells composed of non-volatile transistors are arranged in a matrix, a dummy cell having a transistor structure, a predetermined potential is applied to a selected memory cell, and a current flowing in the memory cell is used. Read potential generating means for generating a read potential corresponding to the data stored in the memory cell, and a reference potential generating means for applying a predetermined potential to the dummy cell and generating a reference potential based on the current flowing through the dummy cell. A reference potential lowering means for lowering the reference potential between the change from the standby state to the operating state and the lapse of a first predetermined time period; and the second predetermined potential after changing from the standby state to the operating state. After a lapse of time, the read potential is compared with the reference potential, and an output corresponding to the comparison result is amplified and output. Nonvolatile semiconductor memory device characterized in that it comprises a width means. 2. The nonvolatile semiconductor memory device according to claim 1, wherein the dummy cell has a dummy cell array in which nonvolatile transistors provided in each row of the memory cell array are arranged in columns. 3. The non-volatile semiconductor memory according to claim 1, wherein the amplifying means is brought into an operating state after a lapse of a predetermined time after the change from the standby state to the operating state and further after a lapse of a predetermined time. apparatus. 4. A memory cell array in which memory cells composed of non-volatile transistors are arranged in a matrix, a dummy cell having a transistor structure, a predetermined potential is applied to a selected memory cell, and a current flowing in the memory cell is used. Read potential generating means for generating a read potential corresponding to the data stored in the memory cell, and a reference potential generating means for applying a predetermined potential to the dummy cell and generating a reference potential based on the current flowing through the dummy cell. And a read potential initial charging means for rapidly charging the read potential from the change from the standby state to the operating state until the lapse of the first predetermined time, and the second read potential initial charging means after changing from the standby state to the operating state. After a lapse of a predetermined time, the read potential and the reference potential are compared, and the output according to the comparison result is amplified. Nonvolatile semiconductor memory device characterized in that it includes a an amplifier means for outputting. 5. A plurality of the memory cell array, a dummy cell, a read potential generating means, a reference potential generating means, a read potential initial charging means, and an amplifying means are provided to correspond to the selected memory cell array. 5. The non-volatile semiconductor memory device according to claim 4, wherein only each of the means is activated. 6. The non-volatile semiconductor memory according to claim 4, wherein said amplifying means is brought into an operating state after a lapse of a predetermined time after the change from said standby state to an operating state and further after a lapse of a predetermined time. apparatus. 7. A memory cell array in which memory cells composed of non-volatile transistors are arranged in a matrix, a dummy cell having a transistor structure, a predetermined potential is applied to a selected memory cell, and a current flowing in the memory cell is used. Read potential generating means for generating a read potential corresponding to the data stored in the memory cell, and a reference potential generating means for applying a predetermined potential to the dummy cell and generating a reference potential based on the current flowing through the dummy cell. And a reference potential lowering unit that lowers the reference potential during a first predetermined time after a change from the standby state to the operating state, and a first predetermined time after the standby state changes to the operating state. A read potential initial charging means for rapidly charging the read potential until the time elapses, and a change from the standby state to the operating state. After a second predetermined time has elapsed, the read potential and the reference potential are compared with each other, and an amplifying means for amplifying and outputting an output according to the comparison result is provided. Nonvolatile semiconductor memory device. 8. The non-volatile semiconductor memory device according to claim 1, wherein the first predetermined time and the second predetermined time are the same.