JPH06349285A - Nonvolatile semiconductor memory - Google Patents

Abstract

PURPOSE:To obtain a nonvolatile semiconductor memory in which the logic circuit operable under automatic write mode is simplified. CONSTITUTION:A comparing circuit 1 comprises a NOR circuit 3 and two inverters 2, 4 and employed when the simultaneously erased data of a memory transistor is set at '1'. Data is rewritten when the input data from a latch circuit is '0' and the data fed from a sense amplifier to the memory transistor is '1'. Writing of data is finished when the input data is '0' and the data of the memory transistor is also '0'. When the input data is '1', writing of data is finished regardless of the data of the transistor.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device, and more particularly to a non-volatile semiconductor memory device having an automatic write mode for automatically writing input data in a memory cell.

[0002]

2. Description of the Related Art A flash memory 40 is one of electrically rewritable nonvolatile semiconductor memory devices. This memory 40 is a batch erasing type (erasing all bits at the same time) and cannot be rewritten on a byte-by-byte basis, but since one bit can be configured by one memory transistor 30 (memory cell), it becomes an inexpensive nonvolatile semiconductor memory device. I will get it.

FIG. 3 is a partially cutaway sectional view showing the structure of the memory transistor 30 of such a flash memory 40. In the figure, N ⁺ diffusion layers 32 and 33 are formed on the surface of a P-type substrate 31 at predetermined intervals to form a drain and a source, respectively. The drain 32 is connected to the bit line in the array, and the source 33 is normally at ground potential. A floating gate 35 is formed between the drain 32 and the source 33 on the P-type substrate 31 via an insulating film 36, and a control gate 34 is formed on the floating gate 35 via an insulating film 37. . The control gate 34 is an electrode for controlling the memory transistor 30, and is connected to the word line in the array. The floating gate 35 captures electrons by writing and holds the state after writing even when the power is turned off. Then, at the time of erasing, electrons are emitted. The insulating film 36 between the floating gate 35 and the substrate 31 is usually formed of an oxide film having a thickness of 100Å,
It is called a tunnel oxide film. The tunnel oxide film is referred to because the electrons in the floating gate 35 are emitted to the drain 32 or the source 33 due to the tunnel phenomenon during erase. The insulating film 37 between the control gate 34 and the floating gate 35 is usually formed of an oxide film having a thickness of 200Å. In the figure, the drain 32 and the source 3
3, the voltages applied to the control gate 34 are V _D , V _S , and V _G , respectively, and the current flowing in the drain 32 is I
_{Let's say D.}

FIG. 4 shows V _G -I of the memory transistor 30.
_{It is a D} characteristic. Memory transistor 3 in erased state
The threshold value of 0 is generally low, and its value is V _THE . When writing data to the memory, a positive high voltage is applied to the drain 32 and the control gate 34, and the source 33 is applied.
To ground potential. This allows the drain 32-source 3
A channel is formed between the three and current flows, and hot electrons are generated in the depletion layer of the drain 32. This hot electric salon has control gate 3
An electric field generated by the positive high voltage applied to the gate electrode 4 causes the floating gate 35 to be pulled and captured. The electric field generated by the electrons trapped in the floating gate 35 shifts the threshold value of the memory transistor 30 to the higher side to become V _THP .

When erasing data in the memory, a positive high voltage is applied to the source 33, the control gate 34 is set to the ground potential, and the drain 32 is set in a floating state. As a result, the electrons captured by the floating gate 35 are emitted to the source 33 due to the tunnel phenomenon caused by the electric field between the source 33 and the floating gate 35, and the threshold value of the memory transistor 30 shifts to the lower side to become V _THE . Then, for example, a state in which the threshold value becomes high and V _THP by writing is treated as data "0", and a state in which the threshold value becomes low and V _THE by erasing is treated as data "1".

FIG. 5 is a block diagram showing the configuration of the flash memory 40. In the figure, this flash memory 4
0 is provided with a memory array 51, and a large number of memory transistors 30 are two-dimensionally arranged in the memory array 51. The control gate 34 of each memory transistor 30 is connected to a row decoder 42 by a word line, and the drain 32 is connected to a column gate 44 by a bit line. The address is transmitted through the address buffer 41 to the row decoder 42 or the column decoder 4
3, one word line and one column gate 44 are selected by each output and connected to the bit line.

At the time of writing, the input data is the data pin 45.
To input buffer 46 and input data latch circuit 47
Is inputted to the write circuit 48 via the, and the data is written in the selected memory transistor 30. A high voltage is applied to the bit line of memory transistor 30 written at this time, and the bit lines of other memory transistors 30 are set to a low voltage, for example, the ground potential. Further, a high voltage is applied to the selected word line and the unselected word line is set to the ground potential.

On the other hand, in reading, one word line and one bit line are selected as in writing. The selected word line is read power supply potential V _CC (where V _THE <V _CC <V
_THP, which is normally V _CC = 5V), and the sensor amplifier 49 is activated. As shown in FIG. 4, in the memory transistor 30 in the erased state, a large drain current _ID flows because the threshold value V _THE is smaller than the read power supply potential V _CC . Further, in the memory transistor 30 in the written state, the threshold value V _THP is larger than the read power supply potential V _CC , so that the drain current I _D does not flow. In this way, the sense amplifier 49 receives the drain current I _D
The data of the transistor 30 is detected depending on whether the current flows or not, and the detected data is output to the data pin 45 via the output buffer 50.

In the case of batch erasing, all the data are erased at the same time by connecting the sources 33 of all the memory transistors 30 to the erasing circuit 52 and applying a high voltage to the sources 33.

Although a control circuit for writing, reading and erasing is required in the above description, it is omitted here.

Next, the automatic write mode which is one of the operations of the flash memory 40 will be described. In the normal write mode that does not depend on the automatic write mode, first write in the write mode and then write in the read mode to check if the written state is sufficient. If it is, the writing mode is set again and additional writing is performed. Then, this operation is repeated until the state is sufficiently written. These mode settings and write checks are performed externally.

The automatic write mode is such that all such write operations are performed inside the chip. FIG. 6 is a flowchart thereof. In step (abbreviated as S in the figure), when an address and data to be written are input in step S1, writing is executed inside the chip in step S2, and the writing state is checked in step S3. If the written state is sufficient in step S3, the writing is completed, and if it is insufficient, the process returns to step S2 and the writing is performed again.

FIG. 7 is an electric circuit diagram of the comparison circuit 53 for checking the write data. This comparison circuit includes a P channel MOS transistor 55, an N channel MOS transistor 56 and three inverters 57, 58 and 59. The sources of P channel MOS transistor 55 and N channel MOS transistor 56 are connected to each other through node 60, and the drains of P channel MOS transistor 55 and N channel MOS transistor 56 are connected to the input node and output node of inverter 57, respectively. Has been done. Further, the node 60 is connected to the input node of the inverter 58, and
Is connected to the input node of the inverter 59, and the output node of the inverter 59 is connected to the input node of the inverter 58. The inverter 59 is for holding the output of the inverter 58. P channel MOS transistor 55 and N channel MOS
The gate of the transistor 56 is the input data latch circuit 47.
, The input node of the inverter 57 is connected to the sense amplifier 49, and the output node of the inverter 58 is connected to the control circuit 54.

The signal from the input data latch circuit 47 is
When the input data is "1", it becomes "H" level,
When the input data is "0", it becomes "L" level.
Further, the signal from the sense amplifier 49 becomes "H" level when the data of the memory transistor 30 is "1", and becomes "L" level when the data of the memory transistor 30 is "0". Further, when the "L" level signal is output from the comparison circuit 53 to the control circuit 54, the data is rewritten, and when the "H" level signal is output, the data writing is completed.

Therefore, when the data of the memory transistors 30 that are erased collectively is "1", when the input data is "0", the "L" level signal from the input data latch circuit 47 is a P channel MOS transistor. 5
5 and the gates of the N-channel MOS transistor 56 and the P-channel MOS transistor 55 is turned on. When the written data of the memory transistor 30 is "0", "L" from the sense amplifier 49
The level signal is input to the inverter 58 via the P-channel MOS transistor 55, the "H" level signal is output to the control circuit 54, and the data writing is completed. Further, when the written data of the memory transistor 30 is “1”, “H” from the sense amplifier 49 is output.
A level signal is input to inverter 58 via P channel MOS transistor 55, an "L" level signal is output to control circuit 54, and data is rewritten.

On the other hand, when the input data is "1", the "H" level signal from the input data latch circuit 47 is supplied to the P channel MOS transistor 55 and the N channel MOS.
Input to the gate of the transistor 56, N channel MO
The S transistor 56 is turned on. When the written data of the memory transistor 30 is “1”, the “H” level signal from the sense amplifier 49 is directly output to the control circuit 54 via the inverter 57, the N-channel MOS transistor 56 and the inverter 58. Then, the data writing is completed.

Since the data of the memory transistor 30 that has been erased collectively is "1", the data of the transistor 30 after writing is not "0" when the input data is "1".

Further, the comparison circuit 53 operates in the same manner when the data of the memory transistor 30 erased collectively is set to "0", but the description is omitted.

[0019]

In the conventional flash memory 40, the input data and the data of the memory transistor 30 are irrespective of whether the input data is "1" or "0" in the automatic write mode. Since the comparison is performed, there is a problem that the configuration of the comparison circuit 53 is complicated.

The present invention has been made to solve the above problems, and its purpose is to:
It is an object of the present invention to provide a nonvolatile semiconductor memory device having a simple logic circuit configuration for performing the automatic write mode.

[0021]

According to a first nonvolatile semiconductor memory device of the present invention, after input data "0" or "1" is written in a memory cell, the input data and the memory cell are written. In the non-volatile semiconductor memory device that compares the input data and the data written in the memory cell and does not match the input data, the input is performed only when the input data is "0". It is characterized in that a logic circuit for comparing data with the data written in the memory cell is provided.

In the second nonvolatile semiconductor memory device of the present invention, after input data "0" or "1" is written in the memory cell, the input data and the data written in the memory cell are stored. In comparison, in the nonvolatile semiconductor memory device that performs rewriting when the input data and the data written in the memory cell do not match, the input data and the memory only when the input data is “1”. It is characterized in that a logic circuit for comparing with the data written in the cell is provided.

[0023]

In the nonvolatile semiconductor memory device according to the present invention, the input data is "0" in the automatic write mode.
Alternatively, since the input data is compared with the data written in the memory cell only when either "1" is set,
The configuration of the logic circuit that performs the automatic write mode is simpler than the conventional method in which the input data and the data written in the memory cell are compared regardless of whether the input data is "0" or "1". Can be converted.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A flash memory according to an embodiment of the present invention will be described below. In this flash memory, the data of the memory transistor 30 that has been erased collectively is treated as "1" and the written memory transistor 3
Data of 0 is treated as “0”.

FIG. 1 is an electric circuit diagram of a comparison circuit 1 used in the automatic write mode of this flash memory. The comparison circuit 1 includes a NOR circuit 3 and two inverters 2 and 4. The output node of the inverter 2 is connected to one input node 3b of the NOR circuit 3, and the output node of the NOR circuit 3 is connected to the input node of the inverter 4. The other input node 3a of NOR circuit 3 is connected to input data latch circuit 47, the input node of inverter 2 is connected to sense amplifier 49, and the output node of inverter 4 is connected to control circuit 54.

Therefore, when the input data is "0", the signal from the input data latch circuit 47 becomes "L" level, and the output of the NOR circuit 3 becomes in phase with the signal from the sense amplifier 49. That is, if the data has not been sufficiently written and the data in the memory transistor 30 is "1" and the output from the sense amplifier 49 is at the "H" level, the output of the NOR circuit 3 is at the "H" level. Therefore, the output of the comparison circuit 1 becomes the "L" level, and the control circuit 54 is instructed to write again. In addition, sufficient writing is performed and the data of the memory transistor 30 is "0".
If the output from the sense amplifier 49 is "L" level, the output of the NOR circuit 3 becomes "L" level. Therefore, the output of the comparison circuit 1 becomes "H" level, and the control circuit 54 is instructed to complete the automatic writing. On the other hand, when the input data is “1”, the input data latch circuit 46
Since the signal from is at "H" level, the sense amplifier 4
The output of the comparison circuit 1 becomes the "H" level regardless of the output from the control circuit 54, and the completion of the writing is always indicated by the control circuit 54.
To be ordered.

In this embodiment, since the data of the memory transistors 30 that are collectively erased is "1",
When the input data is "1", the data writing to the memory transistor 30 is not performed, and it cannot be judged that the data writing is insufficient. Therefore, there is no problem even if the writing is always completed when the input data is "1".

Next, a flash memory according to another embodiment of the present invention will be described. In this flash memory, the data of the memory transistors 30 that are collectively erased is treated as "0", and the written data of the memory transistors 30 is treated as "1".

FIG. 2 is an electric circuit diagram of the comparison circuit 5 used in the automatic write mode. This comparison circuit 5
Includes an inverter 6 and a NAND circuit 7, and the output node of the inverter 6 is one input node 7b of the NAND circuit 7.
It is connected to the. The other input node 7 of the NAND circuit 7
a is connected to the input data latch circuit 47, the input node of the inverter 6 is connected to the sense amplifier 49, and the NAN
The output node of the D circuit 7 is connected to the control circuit 54.

Therefore, when the input data is "1", the signal from the input data latch circuit 47 becomes "H" level, and the output of the NAND circuit 7 becomes in phase with the signal from the sense amplifier 49. That is, if the writing of data is insufficient and the output from the sense amplifier 49 is at "L" level, the output of the NAND circuit 7 becomes "L" level. Therefore, the output of the comparison circuit 5 becomes the "L" level, and the control circuit 54 is instructed to write again. Also,
If sufficient data is written and the output from the sense amplifier 49 is at "H" level, the output of the NAND circuit 7 is "H".
It becomes a level. Therefore, the output of the comparison circuit 5 is "H".
The level becomes the level, and the control circuit 54 is instructed to complete the writing. On the other hand, when the input data is "0", the signal from the input data latch circuit 47 is at "L" level and the output of the comparison circuit 5 is at "H" level regardless of the output of the sense amplifier 49. Therefore, the input data is "0"
If so, the control circuit 54 is always instructed to complete writing.

In this embodiment, since the data of the memory transistors 30 that are collectively erased is "0",
When the input data is "0", the data writing to the memory transistor 30 is not performed, and it cannot be judged that the data writing is insufficient. Therefore, there is no problem even if the writing is always completed when the input data is "0".

[0032]

As described above, according to the present invention, the input data is "0" or "1" in the automatic write mode.
Since the input data and the data in the memory cell are compared only when either one of the above is selected, the input data and the data in the memory cell are compared regardless of whether the input data is "0" or "1". As compared with the conventional case, the circuit configuration of the logic circuit for performing the automatic write mode can be simplified.

[Brief description of drawings]

FIG. 1 is an electric circuit diagram of a comparison circuit used in an automatic write mode of a flash memory according to an embodiment of the present invention.

FIG. 2 is an electric circuit diagram of a comparison circuit used in an automatic write mode of a flash memory according to another embodiment of the present invention.

FIG. 3 is a partially cutaway sectional view showing a structure of a memory transistor of a flash memory.

4 is a V _G -I _{D of} the memory transistor shown in FIG.
It is a figure which shows a characteristic.

FIG. 5 is a block diagram showing a configuration of a flash memory.

FIG. 6 is a flowchart of a flash memory automatic write mode.

FIG. 7 is an electric circuit diagram of a comparison circuit used in a conventional flash memory automatic write mode.

[Explanation of symbols]

 1,5 Comparison circuit 2,4,6 Inverter 3 NOR circuit 7 NAND circuit

Claims (2)

[Claims] 1. After writing input data "0" or "1" into a memory cell, the input data and the data written in the memory cell are compared, and the input data and the memory cell are written. In a non-volatile semiconductor memory device that performs rewriting if the written data does not match, the input data is compared with the data written in the memory cell only when the input data is "0". A non-volatile semiconductor memory device comprising a logic circuit. 2. The input data "0" or "1" is written in the memory cell, the input data is compared with the data written in the memory cell, and the input data is written in the memory cell. In a non-volatile semiconductor memory device that rewrites when the written data does not match, the input data is compared with the data written in the memory cell only when the input data is "1". A non-volatile semiconductor memory device comprising a logic circuit.