JPH05250889A - Nonvolatile semiconductor storage device - Google Patents

Abstract

PURPOSE:To provide a nonvolatile semiconductor storage device which performs stable operations while the power supply voltage wildly fluctuates and provides a high reliability by varying the reference potential in each of the reading modes or the reading potential. CONSTITUTION:The device is provided with circuits 13 and 16 which generate reading potentials of memory cells and a reference potential and a sense amplifying circuit 14 which decides '1' and '0' of data by comparing a read potential and a reference potential as inputs. And by varying the currents flowing in the circuits 13 and 16 after a data change and during a normal reading, the reading and reference potentials are varied.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a non-volatile semiconductor memory device using a non-volatile transistor as a memory cell, and more particularly to a normal power supply voltage for rewriting data and a power supply voltage for reading data. The present invention relates to a nonvolatile semiconductor memory device that can be operated.

[0002]

2. Description of the Related Art The so-called UV-EPRO, which erases data by irradiating ultraviolet rays and electrically writes the data
M or E that electrically erases and writes data
In the EPROM, when the data is read, the cell data is "1" or "0" in the sense amplifier circuit.
"1" or "0" data is read out according to the result of comparison and judgment between the read potentials (referred to as VSA1 and VSA0, respectively) corresponding to the above and the reference potential (referred to as VREF).

[0003] Here, the EEP capable of electrically erasing data
FIG. 21 shows the structure of a non-volatile transistor used as a memory cell in a ROM. 21A is a pattern plan view of this transistor, and FIG. 21B is a cross-sectional view taken along the line AA ′ of FIG. This transistor has a three-layer polycrystalline silicon structure,
The floating gate 121 is formed by the second polycrystalline silicon layer, and the erase gate 122 is formed by the second polycrystalline silicon layer.
The control gates 123 are each composed of the third-layer polycrystalline silicon layer. In addition, in FIG.
4 is a source, 125 is a drain, 127 is a silicon substrate, and 128 is a field insulating film. Data writing, reading and erasing operations in the memory cell having such a structure will be briefly described below.

In the write operation, the drain potential V _{D is set} to 8
V, control gate potential V _CG is 12 V, erase gate potential V _EG
The respectively set to 5V, and, 0V the source potential V _s
Ground to the floating gate with hot electrons (hot el
ectron). In the read operation, the control gate potential V _CG is 5 V and the drain potential V _D is 1
This is performed by setting V, the erase gate potential V _EG, and the source potential V _s to 0V, respectively. At this time, when the stored data of the memory cell is "0" (write state), almost no Dell current flows between the source and drain, and when the stored data is "1" (erase state), 1 is generated between the source and drain.
A cell current of about 00 μA flows. The erase operation is performed by setting the control date potential V _CG and the drain potential V _D to OV and the erase gate potential V _EG to 20 V, respectively. At this time, the electrons that were previously injected into the floating gate were Fowler-Nordheim (Fow).
(ler-Nordheim) tunneling current draws the erase gate.

Further, whether or not the write operation is normally performed is performed by reading data after the write operation and judging whether the stored data of the memory cell is "0" (program verify). At this time, if the stored data is judged to be "1", the write operation is performed again, and the program verify operation is continued until the stored data becomes "0". Similarly, even after the erase operation, the data is read out and the stored data in the memory cell is "1".
(Erase verify). By the way, the actual nonvolatile semiconductor memory device is configured as shown in FIG.

CA11 to CAmn in the figure are main body memory cells, respectively. Each of these memory cells is shown in FIG.
As shown in FIG. 1, it is composed of a source, a drain, a floating gate, a control gate and an erase gate. These memory cells are arranged in a matrix, and each n memory cells arranged in the same row has m control gates.
Drains of m memory cells connected in common to one of the word lines WL1 to WLm and arranged in the same column are common to one of the n data lines DL1 to DLn. It is connected to the. Further, the erase gates of all the memory cells are commonly connected to the erase line EL, and the sources thereof are respectively connected to the ground potential point. The m word lines WL1 to WLm are not shown in the row
It is selectively driven by the output of the row decoder 111 to which the address is input.

Reference numeral 112 denotes a column decoder to which a column address (not shown) is input, and the above n data lines D
L1 to DLn are column selection transfer gates CT to which the respective outputs of the column decoder 112 are input to the gates.
It is connected to the data line bias circuit 113 via 1 to CTn. The data line bias circuit 113 applies a potential of the above value to the drain of the selected memory cell when reading data from the memory cell, and
A read potential is generated according to the cell current of the selected memory cell. This read potential is "1" of cell data,
The input potentials VS1 and VS0 corresponding to “0” are input to the current drive type sense amplifier circuit 114.

Reference numeral 116 is a dummy cell bias circuit,
Of the dummy cells DC1 to DCm formed of nonvolatile transistors having a source, a drain, a floating gate, a control gate and an erase gate like the main body memory cell CA, the drains corresponding to the selected word lines WL1 to WLm are set to a predetermined potential. To bias.

The sense amplifier circuit 114 generates a reference potential VREF to be compared with the potentials VSA0 and VSA1 from the cell data. This reference potential is input as VREF to the current drive type sense amplifier circuit 114.
Further, the control gate and the erase gate of the dummy cells DC1 to DCm suppress the characteristic difference from the main body memory cell,
Any of the m word lines WL1 to WLm and the erase line E
Connected to L. 117 is the sense amplifier circuit 114
It is a data output circuit for outputting the detection data, which is the result of the comparison and determination in 1. to the outside. Readout potential VSA and reference potential V
The potential of REF is the main body memory cell CA and the dummy cell D.
Although depending on the cell current of C, the relationship is as shown in FIG. In FIG. 23, the read potential VSA after the write operation is performed.
0 means that no cell current flows, so VS with a cell current of 0 μA
It becomes the A potential VSA0.

FIG. 24 shows the power supply potential V of the read potential VSA0 of the "0" cell, the read potential VSA1 of the "1" cell and the reference potential VREF which have been sufficiently written and erased.
It is cc-dependent. VccL is the lower limit of the power supply voltage that guarantees the operation of the nonvolatile semiconductor memory device.
cH is the upper limit.

FIG. 24 shows the reference potentials VSA0 and VSA1 of the cells which have been sufficiently written and erased. Here, consider the cells that have been insufficiently written and erased. Insufficient writing means that the number of electrons injected into the FG is small,
This is a cell in which the threshold voltage Vth has not risen sufficiently. In addition, a cell in which erasing is insufficient is a cell in which electrons in the FG cannot be completely exhausted and Vth has not been sufficiently lowered.

FIG. 25A shows the power supply potential Vcc dependency of the reference potential VREF and the read potential VSA0 of a cell in which writing is insufficient. When the power supply voltage Vcc is increased, the read potential VSA0 changes from a certain voltage Vthc to
Since the cell is turned on and the cell current starts to flow, VSA0 decreases. Here, consider a case where the program verify is performed at the lower limit VccL of the power supply voltage and the normal read is performed at the upper limit VccH of the power supply voltage. At the power supply voltage VccL at the time of program verify, the read potential V
Since SA0 is higher than the reference potential VREF, the data is judged to be "0". However, the potential of the read potential VSA0 becomes lower than the reference potential VREF at the power supply voltage VccH at the time of normal read, and the data is determined to be "1", causing a malfunction.

FIG. 25 (b) shows the power supply voltage dependence of the reference potential VREF and the read potential VSA1 of a cell in which erasing is insufficient. Here, consider a case where the erase verify is performed at the upper limit VccH of the power supply voltage and the normal read is performed at the lower limit VccL of the power supply voltage. At the power supply voltage VccH at erase verify, the cell read potential VSA1
Is lower than the reference potential VREF, the data is judged to be "1". However, at the power supply voltage VccL at the time of reading, the read potential VSA1 is higher than the reference voltage VREF, so that the data is determined to be “0” and malfunction occurs.

[0014]

As described above, in the non-volatile semiconductor memory device using the non-volatile transistor as the memory cell, the power supply voltage varies in the read mode. , Read at high power supply voltage. Alternatively, if reading is performed with a power supply voltage lower than the power supply voltage at the time of erase verify, a malfunction occurs if writing or erasing is insufficient.

The non-volatile semiconductor device of the present invention has been made in view of such a problem, and the purpose thereof is to change the reference potential or the read potential in each read mode so as to have a wide range. It is an object of the present invention to provide a nonvolatile semiconductor memory device that can be stably operated under a power supply voltage and can improve reliability.

[0016]

In order to achieve the above object, the present invention provides a nonvolatile cell including a memory cell including a nonvolatile transistor having a source, a drain, a floating gate and a control gate, and a dummy cell. In a semiconductor memory device, a circuit that generates a read potential and a reference potential of the memory cell based on the amount of current flowing through the memory cell and the dummy cell is compared with a circuit that receives the read potential and the reference potential as input, A sense amplifier circuit that determines 1 "or" 0 ", and by changing the current flowing through at least one of the read potential and the reference potential generation circuit after data change and during normal read, The read potential and the reference potential are changed.

[0017]

That is, according to the present invention, the read potential and the reference potential of the memory cell are generated based on the amount of current flowing through the memory cell and the dummy cell, and the read potential and the reference potential are input to compare the two to obtain data. "1" of
After "0" is decided, after changing the data and during normal reading,
The read potential and the reference potential are changed.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention. In the present embodiment, the dummy word line WLD potential that is the gate potential of the dummy cell (DC) of the reference potential setting transistor is, for example, the power supply voltage Vcc potential, and the word line potential VVFY that is the gate potential of the main body memory cell CA is The verify potential generation circuit 18 sets the power supply voltage higher than the power supply voltage, for example, the programming power supply Vpp. In each of the program verify, erase verify, and normal read modes, the row decoder 11 is used.
Any of the word lines WL1 to WLm selected by
A data line DL1 which is selected by the column decoder, passes through the column gate transistors CT1 to CTn, and is biased to a predetermined potential by the data line bias circuit 13.
To main memory cell CA1 connected to any of DLn
Any one of 1 to CAnm is selected.

At this time, the dummy row decoder 15 causes
The dummy word line WLD is also selected, the dummy cell bias circuit 16 biases the dummy data line DDL to a predetermined potential, and the dummy cell DC is selected. Here, DC1 to DCm whose drains are connected to the dummy data lines are
The data lines DL1 to DLn are added to make the parasitic capacitances of the dummy data lines DDL the same, and the sources are in a floating state.

Similarly, CAD1 to DADn whose gates are connected to dummy word lines are word lines WL1 to WLm.
, And the dummy word line are added to make the parasitic capacitance the same, and the source is in a floating state. Furthermore,
The row decoder 11 and the dummy row decoder 15 have the same shape.

VVFY, which is the gate potential of the selected cell in each mode (program verify, erase verify, or read), has the same potential as the gate potential of the dummy cell during normal read, for example, power supply voltage Vcc. Further, at the time of program verify, the gate potential at the time of normal reading, for example, a potential higher than about 5 V, for example, about 7 V is set. Further, at the time of erase verify, it is set to a potential lower than the gate potential at the time of normal reading, for example, about 3V.

Here, the VVFY potential serving as the gate potential and the read potentials VSA0 and VSA1 of the main body memory cells are used.
The relationship between the reference potential VREF and the reference potential VREF is shown in FIG. Where V
SA0H and VSA0L are the read potentials of the "0" cells,
VSA1 is the read potential of the "1" cell. Also,
VVFYE is a potential that serves as a power supply for the row decoder during erase verify, and is set to, for example, about 3V. VVFYP is a potential serving as a power source of the row decoder at the time of program verify, and is set to about 7V, for example. VccL is the lower limit of the power supply voltage, the reference potential at this time is VREFL, VccH is the upper limit of the power supply voltage, and the reference potential at this time is VREFH.

Now, the main body read potential VSA and VREF at the time of program verification will be considered. VSARH and VSARL in the graph are read potentials of cells in which writing and erasing are insufficient. In the conventional example, the lower limit V of the power supply voltage
When the program verify is performed with ccL, the main body read potential VSARL is higher than the reference potential VREFL, so that the data is determined to be “0”. However, when the cell is normally read at the upper limit VccH of the power supply voltage, the main body read potential VSARH becomes equal to the reference potential VR.
The potential becomes lower than EFH, and the data is judged to be "1", resulting in malfunction.

However, in this embodiment, since the gate potential at the time of program verify is VVFYP, the read potential VSARL of a cell in which writing is insufficient is judged to be "1" which is lower than the reference potential VREFL. Also, V
SAPL and VSAPH are read potentials of a cell in which writing is sufficiently performed. Even if the program verify is performed at the lower limit of the power supply voltage, the read potential VSAPL
Becomes a potential higher than the reference potential VREFL, and the data is judged to be "0". Further, during normal reading, since the upper limit of the power supply voltage VccH is read, the read potential VS
AP has a potential higher than the reference potential VREFH, the data becomes "0", and no malfunction occurs.

Similarly, consider the case of erase verify. The read potential of a cell that is not sufficiently erased is V
In the conventional example, when the erase verify is performed at the upper limit VccH of the power supply voltage, the data becomes "1", but when the normal read is performed at the lower limit VccL of the power supply voltage, the data becomes "0" and malfunction occurs. I will end up. In this embodiment, since the gate potential at the erase verify is VVFYE, it is judged that the cells for which writing is insufficient are "0". VSAEL and VSAEH are read potentials of cells that have been sufficiently erased. When the erase verify is performed with the power supply voltage being the upper limit VccH, the read potential VSAFH is lower than the reference potential VREFH, and the data is determined to be "1". Further, at the time of normal reading, even if the lower limit of the power supply voltage is VccL, the read potential VSAEH is equal to the reference potential VREFL.
The potential is lower than that, the data is judged to be "1", and no malfunction occurs.

The verify potential generation circuit 18 is, for example,
It can be realized by a circuit as shown in FIG. Where T ₁ and T
₆ is a PchE type transistor, T ₅ , T ₇ ,
T ₁₀ and T ₁₃ are NchE type transistors, and T ₄ is
NchD type transistor, T ₂ , T ₃ , T ₈ ,
T ₉ , T ₁₁ and T ₁₂ have a threshold value near 0V, Nc
It is an h transistor, and Vpp is a power supply for programming. Circuit constituted by T ₈ through T ₁₀ are typically becomes PV is "L" level, and outputs a nearly Vpp level potential to the output VPV, at the time of program verify, PV becomes the "H" level, the output VPV , A potential determined by the ratio of the dimensions of the Nch transistors T ₈ and T ₉ having a threshold value near 0 V, usually about 7 V is output. Similarly, in the circuit composed of T _{11 to} T ₁₃ , the EV becomes “H” level during erase verify, and the output VEV has the transistor T
₁₁ , the potential determined by the ratio of the dimensions of T ₁₂ ,
Usually, for example, a potential of about 3V is output.

Further, the verify potential VVFY is from T ₁ to
It is supplied to the row decoder 11 by the circuit of T ₇ , where KSW is a signal which becomes Vpp level at the time of program verify and erase verify, and KSWB is a signal which becomes "L" level at this time. The circuit works. At the time of program verify, the gate potential VPV of the Nch transistor T ₂ having a threshold value near 0V is set to about 7V by the circuit of T _{8 to} T ₁₀ , so that the source side of T ₂ is almost 7V. It becomes the electric potential of. This potential is output to VVFY through T ₃ and T ₅ . When the potential of VVFY is higher than VPV, the transistor T ₂ is cut off, the D-type transistor T _{4 is} discharged through the transistor T ₅ , and V
VFY is approximately 7V. Further, T ₆ is turned on only when the potential of VVFY is sufficiently high to accelerate the discharge.

At the time of erase verify, the gate potential VEV of the transistor T ₃ is set to about 3V by the circuit of T _{11 to} T ₁₃ , so that the transistor T _{3 has} the same potential.
Source ₃ becomes the potential of the order of 3V, and output to VVFY through transistor T _5. Also, VVF
Similarly, when Y is higher than VEV, T ₄ and T ₆ ,
Discharged by T ₇ , VVFY becomes approximately 3V.

FIG. 4 shows another circuit that realizes the verify potential setting circuit 18. In this circuit, in the circuit of FIG. 3, Nch transistors T ₂ and T ₃ having a threshold value near 0V are shared by Nch transistors T ₂₂ having a threshold value near 0V. In this circuit, the gate potential VPVEV of the Nch transistor T ₂₂ having a threshold value near 0 V, which limits the word line potential during program verify and erase verify, is set by the circuits T _{27 to} T ₃₁ . At the time of program verify, the gate potential PV of the transistor T ₂₉ becomes "H" level and the output VP
VEV is set to, for example, about 7V by the dimension ratio of Nch transistors T ₂₇ and T ₂₈ having a threshold value near 0V.

At the time of erase verify, EV which is the gate potential of the transistor T ₃₁ becomes “H” level, and the output VPVEV has Nc having a threshold value near 0V.
According to the dimension ratio of the h transistors T ₂₇ and T ₃₀ ,
For example, it is set near 3V. This circuit has a merit that it is possible to save the circuit space because some transistors can be shared. 3 and 4, the programming power supply Vpp uses an external power supply, but this Vpp may be created inside the nonvolatile semiconductor device.

FIG. 5 shows an embodiment of a verify potential generating circuit for realizing this embodiment only with the power supply voltage Vcc.
Here, OSC is GND only at the time of program verify.
A signal oscillating between −Vcc, PV is a signal which becomes “H” level during program verify, PVB is a signal which becomes “L” level during program verify, and EV is a signal which becomes “H” level during erase verify. ..
Further, T ₄₁ and T ₅₄ are NchD type transistors and T
₄₄ and T ₄₅ are Nch transistors having a threshold value near 0V, and T ₄₉ , T ₅₀ and T ₅₂ , T ₅₃ are NchE type transistors or N transistors having a threshold value near 0V.
The other transistors are NchE type transistors.

In the circuit of FIG. 5, the word line potential VVFYP at the time of program verify is set to the transistors T ₄₁ to.
Generated by T ₅₀ . During program verify,
PV is set to "H" level, PVB is set to "L" level, and OSC is a signal that swings between GND and Vcc. A potential of approximately Vcc is transferred to the node N1 through the transistors T ₄₂ and T ₄₄ .

At the same time, since the signal of OSC is transferred to N1 by the transistor T ₄₁ whose source / drain is connected to OSC, the node N1 becomes a signal obtained by combining Vcc and OSC. This signal goes through node T ₄₅ to node N
2 is transferred to the node N2, and the node N2 becomes almost twice as high as the Vcc level. When the potential of the node N ₂ rises sufficiently, the transistor T ₄₃ is also turned on and Vcc is also supplied from the transistor T ₄₃ . Further the potential at the node N2 is transferred to VVFY through transistor T _46. At this time, the transistors T ₄₈ , T ₄₉ , and T ₅₀ discharge to a predetermined potential, for example, about 7V. The potential at this time is a potential determined by the threshold voltages of the transistors T ₄₉ and T ₅₀ , and the number of stages and the types of transistors are changed so that the potential becomes a predetermined potential. The circuit constituted by transistors T ₅₁ through T _55, since EV is at "L" level, does not work.

The voltage for erase verify is generated by the circuit composed of the transistors T _{51 to} T ₅₅ . During erase verify, EV becomes "H" level, Vcc flows through the transistor T ₅₁ through T ₅₃ VVF
Y is supplied to Y, but at this time, VVFY is set to a predetermined potential, for example, 3 by the threshold voltage of the transistors T _{51 to} T _53.
It becomes about V. Further, if the initial potential of VVFY is higher than the predetermined potential, is discharged by T _54, T _55, it can be stabilized to a predetermined potential. At this time, OSC becomes a constant potential, for example, GND or Vcc level, PV becomes "L" level, PVB becomes "H" level, and the circuit composed of the transistors T _{41 to} T ₅₀ does not operate. Since this circuit can be operated only with a single power supply Vcc,
The ease of incorporation in the system is improved and the applicability is also improved.

In this embodiment, the dummy cell DC is formed in the same cell array as the main cells CA11 to CAmn, and the row decoder 11 and the dummy row decoder 15 have the same shape. It is possible to minimize the variation. Sixth
The second embodiment of the present invention is shown in the drawing.

In this embodiment, the dummy cell DC is formed by a peripheral transistor such as an NchE type transistor or the like, separately from the array of the main cells CA11 to CAmn. At this time, the current flowing through the dummy cell DC is set to be about the same as the current flowing through the cells having the data “1” in the main cells CA11 to CAmn, for example, 100 μA. Here, the dummy cell control circuit 20 is
During normal read, program verify, and erase verify, the row decoder 11 causes the word line WL
This is a circuit that outputs "H" level to the gate WLD of the dummy cell DC at the same time when any one of 1 to WLm is selected. The dummy data lines DDL include data lines DL1 to DL1.
Main cells CA11 to C for matching DLn and parasitic capacitance
The drains of cells DC1 to DCm formed in the same cell array as Amn are connected. The sources of the cells DC1 to DCm are in a floating state, and the gates are connected to any of the word lines WL1 to WLm. Further, in order to match the parasitic capacitance and resistance of the word line in the dummy cell control circuit 20, appropriate capacitance and resistance may be added.

In this embodiment, since the dummy cells are not formed in the cell array but are formed by the peripheral transistors, the cells CAD1 to CADn shown in FIG. 1 are not required and the space saving of the device can be realized.

This embodiment can be applied to a cell transistor having a shape as shown in FIG. FIG. 7A is a pattern plan view of this transistor, and FIG.
FIG. 4B is a sectional view taken along the line AA ′ of FIG.

This transistor is formed of a two-layer polycrystalline silicon structure. The first-layer polycrystalline silicon layer constitutes the floating gate 21, and the second-layer polycrystalline silicon layer constitutes the control gate 23. ing. In addition, FIG.
, 24 is a source, 25 is a drain, 27 is a silicon substrate, 22 is a contact hole, and 28 is Al.
The data line is formed through the contact hole 22 and is connected to the drain 25. Data writing, reading and erasing operations in the memory cell having such a structure will be briefly described below.

In the write operation, the drain potential V _{D is set} to 8
V, control gate potential V _CG is 12 V, source voltage V _S is 0
By setting each to V, hot to the floating gate
It is done by injecting electrons. In the read operation, the control gate potential V _CG is 5V,
This is performed by setting the drain potential V _D to 1V and the source potential to 0V. At this time, when the storage data of the memory cell is “0” (write state), almost no cell current flows between the source and the drain, and when the storage data is “1” (erase state), 100 is generated between the source and the drain.
A cell current of about μA flows.

In the erase operation, the control gate potential V _{CG is set} to 0V,
Floating drain potential, high potential at source,
For example, 12V is applied. At this time, the electrons in the floating gate are extracted by the source due to the tunnel effect.

Further, whether or not the write operation is normally performed is performed by program verify after the write operation to determine whether the stored data is "0". If the stored data is "1", write / program verify is performed, and the operation is continued until the data becomes "0".

Similarly, after erase, erase verify is performed to determine whether the data is "1". If the data is "0", erase / erase verify is performed until the data becomes "1". Since the cell having the structure shown in FIG. 7 has a simple structure, the cell area can be reduced,
A reduction in process steps can also be realized. By the way, an actual nonvolatile semiconductor device using the cell of FIG. 7 is configured as shown in FIG.

CA11 to CAmn in the figure are main body memory cells, respectively. Each of these memory cells is shown in FIG.
As shown in, it is composed of a source, a drain, a floating gate, and a control gate. These memory cells are arranged in a matrix, and the control gates of each n memory cells arranged in the same row have m word lines WL.
1 to WLm are commonly connected to the corresponding one, and the drains of the m memory cells arranged in the same column are commonly connected to the corresponding one of the n data lines DL1 to DLn. There is.

The dummy cell DC has a drain on the dummy data line DDL and a gate on the dummy word line WL.
D are connected to each. Furthermore, the dummy data line D
The DL is connected to the drains of the cells DC1 to DCm whose gates are connected to any of the m word lines WL1 to WLm and whose sources are floating.

The dummy word line WLD has cells CAD1 to CA whose drains are connected to any of the n data lines DL1 to DLn and whose sources are floating.
The gate of Dn is connected. In addition, the main body memory cell CA
Sources 11 to CAmn are used for data read (normal read, program verify, erase verify).
A cell source bias circuit 1 that sets the cell source potential VCS to a low potential, for example, the GND level when writing data, and applies a high voltage, for example, a potential of about 12V during erasing.
9, the source of the dummy cell DC has a low potential to the dummy cell source potential VDCS at the time of data reading,
For example, a dummy cell bias circuit 20 for applying a GND level is connected.

Further, the m word lines WL1 to WLm.
Are selectively driven by the output of the row decoder 11 to which a row address (not shown) is input. At this time, the dummy word line WLD is also driven by the dummy row decoder 15.

Reference numeral 12 is a column decoder to which a column address (not shown) is input, and the n data lines DL are provided.
1 to DLn are column selection transfer gates CT1 to CT1 to which the respective outputs of the column decoder 12 are input to the gates.
It is connected to the data line bias circuit 13 via CTn. The data line bias circuit 13 applies a potential having the above value to the drain of the selected memory cell when reading data from the memory cell and generates a read potential corresponding to the cell current of the selected memory cell. To do. This read potential is input to the current drive type sense amplifier circuit 14 as input potentials VSA0 and VSA1 corresponding to "1" and "0" of cell data.

At this time, the dummy cell bias circuit 16 also outputs the voltage having the above value and applies it to the drain of the dummy cell DC. The cell current flowing through the dummy cell DC generates a reference potential VREF, which is input to the current-driven sense amplifier circuit 14. It is obvious that the verify potential generation circuit 18 can be realized by the circuits as shown in FIGS. Further, it is apparent that the cell having the structure shown in FIG. 7 can be used in the device for forming the dummy cell DC with the peripheral transistor as in the embodiment shown in FIG.

FIG. 9 shows a third embodiment of the present invention. In this embodiment, dummy cells DC and TL1 and TL2 are provided as reference potential setting transistors. The dummy cell DC uses the same memory cell as the main body memory cell CA, and the gate signal WL is connected to the same word line as the main body in order to suppress variations in characteristics with the main body memory cell CA. Further, TL1 and TL2 are outputs EV and PVB of the gate voltage generation circuit 1 and the gate potential generation circuit 1 '(1, 1'may be the same circuit or different circuits) which generate a predetermined potential depending on each read mode. Is controlled by receiving the output of, and a predetermined current flows in the ON state.

FIG. 10 shows signals WL and EV in FIG.
B, PV and reference potential setting transistors DC, TL
1 shows the relationship between TL2. In the erase verify mode, since the word line WL of the selected cell is in the "H" state, the dummy cell DC is in the ON state. Also, EVB and PV are both in the “L” state,
Gate potentials EV and PV of the transistors TL1 and TL2
B is generated by the gate potential generating circuits 1 and 1 ',
It becomes a predetermined potential, becomes an ON state, and a predetermined current flows. In the READ mode, similarly, the word line WL of the selected cell becomes the “H” state, and the Tammy cell DC
Becomes an ON state. Regarding TL2, PV becomes "L" and the gate potential PVB becomes a predetermined potential as in the erase verify mode, so that it becomes the ON state and a predetermined current flows. Since EV of TL1 becomes "H", the gate potential EV becomes "L", which is in the OFF state, and no current flows. In the program verify mode, the word line WL of the selected cell is in the "H" state and the dummy cell DC is in the ON state.
Regarding L2, since the control signals EVB and PV are "H", the gate potentials EV and PVB are in the "L" state, and O
Since it is in the FF state, no current flows.

The gate potential generating circuits 1 and 1'can be realized by a circuit as shown in FIG. 11, for example. When the input signal IN becomes "L", Vcc supply Pch transistor T1
Turns ON and the gate is connected to the output OUT Nc
A predetermined potential is supplied to the output OUT by the action of the resistance components of the hD type transistor T2 and the NchE type transistor T4. At this time, the NchE type transistor T3 is in the OFF state. Further, when the input signal IN becomes “H”, the Vcc supply transistor T1 becomes OF
In the F state, the NchE type transistor T3 is turned on.
As a result, the output OUT becomes "L" level. In each signal of FIG. 9, EVB, PV is IN, EV,
PVB corresponds to OUT. The relationship between the read potential and the reference potential according to this embodiment will be described with reference to FIGS.

In FIG. 12, VSA0 is the read potential of the "0" cell, and VSA1 is the read potential of the "1" cell. VREFP is a reference potential at the time of program verification, and this potential is determined by the cell current of the dummy cell DC. VREFR is a reference potential during normal reading,
This potential is determined by the sum of the currents flowing through the dummy cell DC and the reference potential setting transistor TL2. VREFE
Is a reference potential at the time of erase verify, and this potential is the dummy cell DC and the reference potential setting transistor TL.
1, determined by the sum of the currents flowing through TL2.

FIG. 13 shows the read potential VS after writing.
A0 and the reference potential VREFP at the time of program verify
And the power supply voltage Vcc of the reference potential VREFR at the time of reading
It is a dependency.

Here, VSA0a is a read potential of a cell in which writing is insufficient. In this case, VREFR, which is the same as the reference potential during program verify and during read, is used.
Then, the program verify at the lower limit VccL of the power supply voltage is OK. However, the upper limit of the power supply voltage VccH
If it is read with, the result will be NG.

In this embodiment, since the reference potential during program verify is VREFP, the lower limit of the power supply voltage V
Since it becomes NG in ccL, writing is sufficiently performed until it becomes VSA0b. At this time, even if reading is performed at the upper limit VccH of the power supply voltage, VSA0b is above the reference potential VREFR, data is normally read as "0", and no malfunction occurs.

FIG. 14 shows the read potential VSA1 after erase.
And the reference potential VREFE at the time of erase verify and the reference potential VREFR at the time of reading are dependent on the power supply voltage Vcc.

Here, VSA1a is the read potential of a cell that is not sufficiently erased. In this case, if erase verify is performed at the upper limit VccH of the power supply voltage, VREFR becomes OK, but the reference potential VEFE in the present embodiment. NG
Therefore, it is necessary to erase until VSA1b is reached. In this case, the read potential VSA1b is higher than the reference potential VREFR even at the lower limit VccL of the power supply voltage.
The data is normally read as "1" and no malfunction occurs.

In the present embodiment, by providing a reference potential setting transistor in addition to the dummy cell DC, the value of the reference potential can be changed by changing the sum of the currents flowing in each read mode. Even if reading is performed with a power supply voltage lower than the verify power supply voltage, a malfunction does not occur because the difference between the read potential and the reference potential is large. Further, even when reading is performed with a power supply voltage higher than the erase verify power supply voltage, a large difference between the read potential and the reference potential does not cause a malfunction. Further, the reference potential can be freely changed by appropriately setting the output potential of each gate potential generating circuit.

Further, the reference potential setting transistor TL
It is clear that 1 and TL2 may be made of a non-volatile transistor having the same shape as the main body cell like the dummy cell, and the dummy cell DC having the same shape as the main body cell may be made of a transistor having the same shape as the normal transistor. The good news is clear.

FIG. 15 shows a fourth embodiment of the present invention. The present embodiment is an example of a case where the reference potential setting transistor is realized by one transistor TL3. In this example,
The current flowing through the reference potential setting transistor TL3 changes according to the potential of the output VCG of the gate potential generation circuit 2. Further, the gate potential generation circuit 2 can be realized by a circuit as shown in FIG. 16, for example. In the erase verify mode, the EV input to the transistors T7 and T13
Since B becomes "L", Vcc supply transistor T7
Turns on, and NchD type transistor T8
And a predetermined potential is output to VLG by the action of the NchE type transistor T11. READB, PVB
Becomes the "H" state. Similarly, in the READ mode, READB becomes “L”, EVB, and PVB become “H”, so that the Vcc supply transistor T5 is turned on, and by the action of the NchD type transistor T6 and the NchE type transistor T11, A predetermined potential is output to VLG, and in the program verify mode,
PVB becomes "L", READB, EVB becomes "H",
The Vcc supply transistor T9 is turned on, and Nc
A predetermined potential is output to VLG by the action of the hD type transistor T10 and the NchE type transistor T11. Nch D type transistors T6 and T at this time
By setting the channel widths of T8 and T10 to be the same and the relationship of the channel lengths to be T8 <T6 <T10, the reference potential in each read mode is as follows. VREFP>VREFR> VREFE

As a result, the current flowing through the reference potential setting transistor TL3 of FIG. 15 can be changed, and the relationships shown in FIGS. 12, 13 and 14 can be created as in the third embodiment. According to this embodiment, the same effect as that of the third embodiment can be expected, and part of the effect can be shared, so that the circuit space can be saved.

Further, it is apparent that the same effect can be obtained even if a memory cell having the same structure as the main body memory cell is used as the reference potential setting transistor TL3 in this embodiment.

FIG. 17 shows a fifth embodiment of the present invention. In this embodiment, a transfer gate CT is provided in a data line bias circuit that sets the drain of the main body memory cell to a predetermined potential.
A read potential setting transistor TL4 is added in parallel with the memory cells connected via 1 to DTn.
This embodiment is particularly effective at the time of program verification. The gate potential generation circuit 3 of this embodiment is, for example, as shown in FIG.
This can be realized by using a circuit such as 1, and the input signal IN corresponds to PVB and the output signal OUT corresponds to VLG.
In the program verify of the present embodiment, since the gate potential setting circuit PVB becomes "L", the output VL input to the gate of the read potential setting transistor TL4.
G has a predetermined potential, and current flows through TL4 together with the selected memory cell. Further, in the read mode, PVB becomes "H", so the gate signal V of TL4
LG goes to "L" level, and no current flows through TL4, but only the cell current of the memory cell flows.

FIG. 18 shows the read potential VSA0 of this embodiment.
Shows the dependency of the reference potential VREF on the power supply voltage Vcc. Here, VSA0P is a read potential at the time of program verify, and VSA0R is a read potential at the time of read. The value of the reference potential VREF is constant.

VSA0 at program verify
The level of P is determined by the current flowing through the read potential setting transistor TL4 because no current flows through the main body memory cell. Here, if the program verify is performed at the lower limit VccL of the power supply voltage, VSA0P is higher than the reference potential VREF, so that it is determined that the data has been written and becomes "0". After that, if reading is performed at the level of VSA0P at the upper limit VccH of the power supply voltage, VSA0P becomes lower than VREF and NG
Becomes

However, in the present embodiment, during the normal read, the read potential setting transistor TL4 is turned off.
Therefore, no current flows, and the read potential is determined only by the cell current of the main body memory cell and becomes VSA0R. In this case, even if reading is performed at VccH, VSA0R remains at V
Since the potential is higher than REF, the data becomes "0" and no malfunction occurs.

In this embodiment, the same effect can be obtained without raising the reference potential at the time of program verification, and the voltage stress applied to the drain of the dummy cell can be suppressed. Therefore, the weak program state at the time of reading can be suppressed, and a stable reference potential can be created. Further, the read potential setting transistor TL4 may be made of a nonvolatile transistor having the same shape as the main body memory cell. Further, it is clear that this embodiment may be made at the same time as the third embodiment or the fourth embodiment, and in this case, both effects can be expected. Figure 1
9 is a sixth embodiment of the present invention.

In this embodiment, TL5 is "0" for a long time.
When the cell is read, the read potential may rise due to overcharge, and if the "1" cell is read after that, the read time may be delayed.
In order to avoid this, the leakage transistor TL5 has 0.
To deal with this, a current of about 5 to 1.0 μA is passed. In such a case, if the reference potential VREFP at the time of program verify is raised by the method of the first embodiment,
The difference between the reference potential VREFP and the read potential VSA0 is reduced, and the read speed at the time of program verify becomes slow. Therefore, in the present embodiment, the leak transistor TL5 at the time of program verify is turned off so as not to slow down the reading speed.

The gate potential generating circuit 4 can be realized by a circuit diagram as shown in FIG. 11, for example. The input signal IN at this time corresponds to READB, and the output signal OUT is V
Corresponds to LG. Input READB of gate potential generation circuit
Becomes "L" level in the read mode, supplies a predetermined potential to the output VLG, and leak transistor TL5
A leak current of about 0.5 to 1.0 μA is applied to the device. At the time of program verify, READB becomes "H", VLG becomes "L" level, and no leak current flows.

FIG. 20 shows the read potential VSA0 of this embodiment.
And the reference potential VREF are dependent on the power supply voltage Vcc,
VSA0R is a read potential at the time of read,
0P is a read potential at the time of program verify.
VREFR is a reference potential at the time of reading,
REFP becomes a read potential at the time of program verification.

[0073]

As described in detail above, according to the nonvolatile semiconductor memory device of the present invention, the program verify or the erase verify is more effective than the normal reading.
By reducing the difference between the main body read potential and the reference potential, sufficient write or erase operation can be performed, and normal operation can be performed under a wide power supply voltage. A highly reliable nonvolatile semiconductor memory device can be realized without causing a malfunction of data reading due to a change in power supply voltage.

Further, since sufficient write or erase operation can be performed, the difference between the main body read potential and the reference potential at the time of normal read becomes large, so that high-speed read operation becomes possible.

Further, during normal reading and during program verify and erase verify, the potential of the gate of the dummy cell is kept constant and the potential of the gate of the main cell is changed, thereby changing the cell current in each mode to perform sufficient writing. , Erase operation can be performed. Also,
Even if the power supply voltage in each mode changes, a highly reliable nonvolatile semiconductor memory device can be realized without causing a malfunction in data reading. Furthermore, since the difference between the main body read potential and the reference potential can be increased during normal reading, high-speed reading can be realized.

[Brief description of drawings]

FIG. 1 is a circuit configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a VVFY potential serving as a gate potential, read potentials VSA0 and VSA1 of a main body memory cell, and a reference potential V.
It is a figure which shows the relationship of REF.

FIG. 3 is a diagram showing a configuration of a verify potential generation circuit in FIG.

FIG. 4 is a diagram showing another circuit configuration for realizing a verify potential setting circuit.

FIG. 5 is a diagram showing a configuration of a verify potential generation circuit for realizing the first embodiment with only the power supply voltage Vcc.

FIG. 6 is a circuit configuration diagram showing a second embodiment of the present invention.

FIG. 7 is a diagram showing a cell transistor having a shape to which the present invention is applicable.

8 is a diagram showing a configuration of an actual nonvolatile semiconductor memory device using the cell of FIG.

FIG. 9 is a circuit configuration diagram showing a third embodiment of the present invention.

FIG. 10 is a diagram showing an ON / OFF relationship in each mode of the reference potential setting transistor used in the embodiment of FIG.

11 is a diagram showing an example of a gate potential generation circuit used in the embodiment of FIG.

12 is a diagram showing the power supply voltage dependence of the reference potential and the read potential used in the embodiment of FIG.

13 is a diagram showing the power supply voltage dependency of the reference potential and the read potential used in the embodiment of FIG.

14 is a diagram showing the power supply voltage dependence of the reference potential and the read potential used in the embodiment of FIG.

FIG. 15 is a circuit configuration diagram showing a fourth embodiment of the present invention.

16 is a diagram showing an example of a gate potential generation circuit used in the embodiment of FIG.

FIG. 17 is a circuit configuration diagram showing a fifth embodiment of the present invention.

18 is a diagram showing the power supply voltage dependence of the reference potential and the read potential used in the embodiment of FIG.

FIG. 19 is a circuit configuration diagram showing a sixth embodiment of the present invention.

20 is a diagram showing the power supply voltage dependence of the reference potential and the read potential used in the embodiment of FIG.

FIG. 21 is a diagram showing a structure of a nonvolatile transistor used as a memory cell in an EEPROM.

FIG. 22 is a circuit diagram showing an overall configuration of a conventional nonvolatile semiconductor memory device.

FIG. 23 is a diagram showing cell current dependence of a reference potential and a read potential used in a conventional example.

FIG. 24 is a diagram showing the power supply voltage dependence of the reference potential and the read potential used in the conventional example.

FIG. 25 is a diagram showing the power supply voltage dependence of the reference potential and the read potential used in the conventional example.

[Explanation of symbols]

11 ... Row decoder, 12 ... Column decoder, 13 ... Data line bias circuit, 14 ... Sense amplifier circuit, 15 ... Dummy row decoder, 16 ... Dummy cell bias, 1,
1 '... Gate potential generating circuit, DC, TL1, TL2 ... Dummy cell.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tadashi Miyagawa 580-1 Horikawa-cho, Saiwai-ku, Kawasaki City, Kanagawa Prefecture Toshiba Corporation Semiconductor System Technology Center

Claims (12)

[Claims] 1. A non-volatile semiconductor memory device comprising a memory cell including a non-volatile transistor having a source, a drain, a floating gate and a control gate, and a dummy cell, based on an amount of current flowing through the memory cell and the dummy cell. A memory cell for generating a read potential and a reference potential of the memory cell; and a sense amplifier circuit for determining both "1" and "0" of data by comparing the read potential and the reference potential as inputs. A non-volatile semiconductor characterized in that the read potential and the reference potential are changed by changing the current flowing through at least one of the read potential and the reference potential generation circuit after the data is changed and during the normal read. Storage device. 2. A second dummy cell and a third dummy cell arranged in parallel with the dummy cell for generating the reference potential,
By controlling the gate of each dummy cell, the reference potential is increased by decreasing the current during program verify with respect to the current during read, and
2. The non-volatile semiconductor memory device according to claim 1, wherein the reference potential is reduced by increasing the current during erase verify. 3. The gate potential of a dummy cell for generating the reference potential is changed to increase the reference potential by decreasing the current at the program verify with respect to the current at the read, and at the same time, the erase is performed. 2. The non-volatile semiconductor memory device according to claim 1, wherein the reference potential is decreased by increasing the current during verification. 4. The dummy cell is formed with the same structure in the same cell array as the main body memory cell, the source is floating on the drain of the dummy cell, and the control gate is common to the control gate of the main body memory cell. 4. The nonvolatile semiconductor memory device according to claim 3, wherein cells having the same structure are added in the same cell array as the main body memory cells. 5. The dummy cell is formed by a peripheral transistor, the source is floating on the drain of the dummy cell, the control gate is shared with the control gate of the main body memory cell, and the same main cell is in the same cell array. 4. The non-volatile semiconductor memory device according to claim 3, wherein cells formed by the structure are added. 6. The non-volatile semiconductor memory device according to claim 1, wherein a transistor is added in parallel with said memory cell, and a predetermined current is caused to flow from this transistor at the time of program verify to create said read potential. 7. The nonvolatile semiconductor memory device according to claim 1, wherein a transistor is added in parallel with the memory cell, and a predetermined current is caused to flow from the transistor at the time of reading to create the read potential. 8. A non-volatile semiconductor memory device including a memory cell including a non-volatile transistor having a source, a drain, a floating gate, and a control gate, and a memory based on the amount of current flowing through the memory cell and the dummy cell. A circuit for generating a read potential and a reference potential of the cell, a sense amplifier circuit for comparing the two with the read potential and the reference potential as inputs, and determining "1" or "0" of the data, and when selecting a memory cell It has a circuit for generating a potential to be a control gate potential and a circuit for generating a gate potential of a dummy cell, and makes the control gate potential higher than the potential at the time of normal reading during program verify and lower during erase verify, The gate potential of the dummy cell is read in the control gate potential of the memory cell in each mode. The nonvolatile semiconductor memory device, characterized in that the same as the potential at the time out. 9. The dummy cell is formed with the same structure in the same cell array as the main body memory cell, the source is floating on the drain of the dummy cell, and the control gate is shared with the control gate of the main body memory cell. 9. The non-volatile semiconductor memory device according to claim 8, wherein cells having the same structure are added in the same cell array as the main body memory cells. 10. The dummy cell is formed by a peripheral transistor, the source is floating on the drain of the dummy cell, the control gate is common to the control gate of the main body memory cell, and the same main cell is in the same cell array. 9. The non-volatile semiconductor memory device according to claim 8, wherein a cell formed by the structure is added. 11. In the control gate potential, a potential at the time of program verify and erase verify is made from a second power supply higher than a first power supply, and a gate potential of the dummy cell is made from the first power supply. The nonvolatile semiconductor memory device according to claim 8. 12. In the control gate potential, a potential at the time of program verify is created by boosting the first power supply,
9. The non-volatile semiconductor memory device according to claim 8, wherein the potential at erase verify is created by stepping down the first power supply.