JP3428124B2 - MIS transistor and method of manufacturing the same - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION This invention is applied to MIS (Metal Insu
The present invention relates to a MIS transistor and a method for manufacturing the same, and more particularly to a MIS transistor and a method for manufacturing the same, which enables high integration and high performance.

[0002]

2. Description of the Related Art In recent years, VLSI has come to be used in various electronic devices. Further, there is a demand for higher performance and smaller size of this electronic device. Along with this, VLSI is also required to have higher performance and higher integration. In order to meet such requirements, various transistor structures have been devised conventionally.

The following is a description of a conventional method devised to satisfy the above demands for high performance or high integration.
One example of transistors incorporated in AM, 4
3 and FIG. 44 . Figure 43 shows the SOI (Semico
FIG. 3 is a partial cross-sectional view showing a DRAM (Dynamic Random Access Memory) in which a transistor having an nductor on insulator structure is incorporated. FIG. 44 shows a D having transistors formed three-dimensionally in the vertical direction to achieve high integration.
It is a fragmentary sectional view showing RAM. 43 and FIG.
The DRAM shown in FIG. IEEE IE
DM (1985) P.M. 694-P. 697.

[0004] First, with reference to FIG. 43 described above, it will be explained a conventional method capable of realizing high performance. Referring to FIG. 43, on the main surface of p-type semiconductor substrate 101, p-type semiconductor layer 102 and n-type semiconductor layer 103 are formed, respectively. In addition, on the main surface of the p-type semiconductor substrate 101, p
A trench 105 reaching the type semiconductor layer 102 is formed at a predetermined position. An insulating layer 104 is formed on the inner surface of the trench 105. A cell plate electrode 106 is formed on the surface of the insulating layer 104. An insulating layer 107 is formed so as to cover the surface of the cell plate electrode 106.

An n-type semiconductor layer 1 is formed on the insulating layer 107.
08 and 110 and the p-type semiconductor layer 109 are formed. A gate electrode (word line) 111 is formed on the p-type semiconductor layer 109 with an insulating layer 114 interposed. The gate electrode 111 and the n-type semiconductor layers 108 and 1
10 and the p-type semiconductor layer 109 constitute the transistor having the above SOI structure.

[0006] The SOI structure transistor has been studied for a long time, and it is a well-known fact that high performance such as prevention of latch-up and improvement of subthreshold characteristics can be achieved.

An interlayer insulating layer 112 is formed so as to cover the gate electrode 111, and a contact hole 115 is provided at a predetermined position in the interlayer insulating layer 112. Bit line 113 will be formed in contact hole 115 and on interlayer insulating layer 112.

[0008] Next, the conventional method of realizing the above-mentioned high integration, is described with reference to FIG. 44. Referring to FIG. 44 , in the DRAM shown in this figure, n-type semiconductor layers 108 and 110 and p-type semiconductor layer 109 are vertically stacked. The gate electrode 111 is provided at a position facing the side surface of the p-type semiconductor layer 111. It is similar to the DRAM shown in FIG. 43 with respect to the other structure. With such a structure, the transistor can be three-dimensionally formed in the vertical direction. Therefore, as in the case shown in FIG. 43, as compared to the transverse direction in the case of forming a transistor, the semiconductor substrate 1
It is possible to reduce the area occupied by the transistor on the main surface 01. As a result, high integration of the device can be realized.

[0009]

However, the above-mentioned conventional example has the following problems. The problem will be described again with reference to FIGS. 43 and 44 . First, referring to FIG. 43 , in a conventional SOI structure transistor, n-type semiconductor layers 108 and 110,
The p-type semiconductor layer 109 is provided so as to be laterally adjacent to it.

On the other hand, also in this SOI structure transistor, in order to obtain desired transistor characteristics, the plane width W1 of the n-type semiconductor layer 108, the plane width W2 of the p-type semiconductor layer 109 serving as a channel region, and the n-type semiconductor are obtained. A predetermined size is required as the plane width W3 of the layer 110. Specifically, the plane widths W1 and W3 need to be about 1 μm.
Further, the plane width W2 needs to be about 0.5 μm. As a result, the conventional SOI structure transistor described above requires a plane width W4 of at least about 2.5 μm. Therefore, there arises a problem that it is difficult to further reduce the planar width of the transistor without deteriorating the performance, that is, it is difficult to achieve high integration.

Next, with reference to FIG. 44 , the problem of the transistor highly integrated by the conventional method will be described. As shown in FIG. 44 , the n-type semiconductor layers 108, 1
10, by stacking the p-type semiconductor layer 109 in the vertical direction, it is possible to highly integrated transistors than the case shown in FIG. 43. More specifically, the planar width W6 of the n-type semiconductor layers 108 and 110 and the p-type semiconductor layer 109 can be reduced to about 1 μm or less.
Therefore, even when considering the plane width of the gate electrode 111, it is possible to highly integrated transistors than the case shown in FIG. 43.

However, the n-type semiconductor layers 108 and 110,
By forming the p-type semiconductor layer 109 and the plane width W6 as described above, the following problems occur. That is, in the vertical transistor shown in FIG. 44 , compared to the case of the SOI structure transistor shown in FIG. 43 , when a voltage is applied to the gate electrode 111 in the p-type semiconductor layer 109, the gate electrode 111
A junction is formed between the inversion layer formed in the vicinity and the remaining p-type semiconductor layer 109. Capacitance is generated at this junction. This causes a problem that the characteristics of the transistor such as the subthreshold characteristics are deteriorated.

This is a problem caused by the p-type semiconductor layer 109 having the plane width W6 as described above. However, in the current technology, the bit line 113 and the n-type semiconductor layer 1 are formed.
Contact hole 11 for electrically connecting with 10
Since it is difficult to set the opening width W5 of No. 5 to 0.5 μm or less, the plane width W6 between the n-type semiconductor layers 108 and 110 and the p-type semiconductor layer 111 is necessarily about 1 μm as described above. . Therefore, the problem of deterioration of the characteristics of the transistor as described above is inevitably caused.

As described above, in the conventional method, it has been difficult to achieve high integration when pursuing high performance, and it has been difficult to achieve high performance when pursuing high integration. That is, the conventional method has a problem that it is difficult to simultaneously satisfy the two requirements of high integration and high performance.

The present invention has been made to solve the above problems. An object of the present invention is to provide a MIS transistor and a manufacturing method thereof that can simultaneously satisfy two requirements of high integration and high performance.

[0016]

[0017]

MIS according to the present invention
The type transistor includes a first conductive type semiconductor substrate having a main surface, a second conductive type impurity diffusion layer, a first insulating layer, a second conductive type first semiconductor layer, and a first conductive type semiconductor substrate. The semiconductor device includes a second semiconductor layer, a second conductivity type third semiconductor layer, a second insulating layer, a gate electrode, and a conductive layer. The second conductivity type impurity diffusion layer is formed on the main surface of the semiconductor substrate. The first insulating layer is formed on the main surface of the semiconductor substrate and has an opening reaching part of the surface of the impurity diffusion layer. The first semiconductor layer is formed on a part of the surface of the impurity diffusion layer. The second semiconductor layer is formed on the upper surface of the first semiconductor layer. The third semiconductor layer is formed on the upper surface of the second semiconductor layer. A hole penetrating the second semiconductor layer is provided inside the second semiconductor layer in the depth direction of the opening. The second insulating layer is embedded in this hole. The gate electrode is formed at a position facing the side surface of the second semiconductor layer with a third insulating layer interposed. The conductive layer is connected to the third semiconductor layer. Above Kiana is penetrating in the depth direction of the opening also a third semiconductor layer
The upper surface and a part of the side surface of the third semiconductor layer are the second insulating layer.
The conductive layer projects from the top surface and is flush with the top surface of the third semiconductor layer.
It is formed so as to cover the side surface of the part .

According to the method of manufacturing a MIS transistor according to the present invention, in one aspect, first, a second conductivity type impurity diffusion layer is formed in a predetermined region of the main surface of a first conductivity type semiconductor substrate. A first insulating layer, a first conductive layer patterned into a predetermined shape, and a second insulating layer are sequentially formed on the surface of the impurity diffusion layer. A first opening is formed that partially penetrates the first insulating layer, the first conductive layer, and the second insulating layer to expose a part of the surface of the impurity diffusion layer. A third insulating layer is formed on the surface of the first conductive layer exposed in the first opening. A second conductive type first semiconductor layer and a first conductive type second semiconductor layer are formed on a part of the exposed surface of the impurity diffusion layer.
A semiconductor layer and a second conductivity type third semiconductor layer are sequentially formed. At this time, the third semiconductor layer is formed so that its upper surface is lower than the upper surface of the second insulating layer. A first sidewall insulating layer is formed on the sidewall of the first opening located on the third semiconductor layer. A second opening is formed partially penetrating the second and third semiconductor layers using the first sidewall insulating layer as a mask. A fourth insulating layer is formed so as to fill the inside of the second opening and cover the second insulating layer. By reducing the thickness of the fourth insulating layer and the first sidewall insulating layer, the upper surface of the third semiconductor layer is exposed and the fourth insulating layer is left in the second opening. A second conductive layer is formed on the upper surface of the third semiconductor layer.

According to the method of manufacturing a MIS transistor according to the present invention, in another aspect, first, a first insulating layer patterned into a predetermined shape is formed on the main surface of a semiconductor substrate of the first conductivity type. Using the first insulating layer as a mask, the main surface of the semiconductor substrate is subjected to anisotropic etching to form a first groove. A first sidewall insulating layer is formed on the sidewall of the first groove.
Using the first insulating layer and the first sidewall insulating layer as a mask, the bottom surface of the first groove portion is subjected to anisotropic etching treatment to form a second groove portion continuous with the first groove portion. Using the first insulating layer and the first sidewall insulating layer as a mask, impurities of the second conductivity type are introduced into the surface of the second groove portion to form a first impurity diffusion layer. A second insulating layer is formed so as to cover the second groove portion and the first sidewall insulating layer, and the second insulating layer is etched back to leave the second insulating layer in the second groove portion. At the same time, the first sidewall insulating layer is removed at the same time. First covering the second insulating layer
Forming a fourth insulating layer exposing the upper surface of the insulating layer. By removing the first insulating layer, a third groove portion that selectively exposes the main surface of the semiconductor substrate is formed. A second impurity diffusion layer is formed by introducing an impurity of the second conductivity type into the exposed main surface of the semiconductor substrate. A second sidewall insulating layer is formed on the side wall of the third groove portion, and the main surface of the semiconductor substrate is etched by using the second sidewall insulating layer and the fourth insulating layer as a mask to etch the first impurity. A fourth groove portion reaching the diffusion layer is formed. A fifth insulating layer is formed so as to fill the inside of the fourth groove portion and cover the second sidewall insulating layer. By reducing the thickness of the fifth insulating layer and the second sidewall insulating layer, the upper surface of the third semiconductor layer is exposed and the fifth insulating layer is left in the fourth groove portion. A second conductive layer is formed on the upper surface of the third semiconductor layer.

According to the method of manufacturing a MIS transistor according to the present invention, in yet another aspect, first, a second conductivity type impurity diffusion layer is formed in a predetermined region of the main surface of a first conductivity type semiconductor substrate. A first insulating layer, a first conductive layer patterned into a predetermined shape, and a second insulating layer are sequentially formed on the surface of the impurity diffusion layer. First insulating layer, first
Forming a first opening that partially penetrates the conductive layer and the second insulating layer to expose a part of the surface of the impurity diffusion layer.
Third and fourth insulating layers are sequentially formed on the side wall surface of the first opening. A fifth insulating layer is embedded in the first opening surrounded by the third and fourth insulating layers. By removing the fourth insulating layer, a part of the surface of the impurity diffusion layer is exposed. A second conductivity type first semiconductor layer, a first conductivity type second semiconductor layer, and a second conductivity type third semiconductor layer are sequentially formed on a part of the exposed surface of the impurity diffusion layer. Third
A second conductive layer is formed on the upper surface of the semiconductor layer. Also this
A method of manufacturing a MIS type transistor according to the invention is further provided.
In another aspect, the following steps are provided. Half of the first conductivity type
Impurity diffusion of the second conductivity type in a predetermined area on the main surface of the conductor substrate
Form the layers. Metal silicide layer on the surface of impurity diffusion layer
To form. A first insulating layer on the metal silicide layer, a predetermined
A first conductive layer patterned into a shape and a second insulating layer
Edge layers are sequentially formed. A first insulating layer, a first conductive layer and
And part of the impurity diffusion layer partially penetrating the second insulating layer.
A first opening is formed that exposes the surface. First opening
A third insulating layer is formed on the surface of the first conductive layer exposed inside.
To achieve. A second conductive layer is formed on a part of the exposed surface of the impurity diffusion layer.
An electrically conductive first semiconductor layer, a first conductive type second semiconductor layer, and
The upper surface of the third semiconductor layer is in front of the third semiconductor layer of the second conductivity type.
Sequentially formed so as to be lower than the upper surface of the second insulating layer
To do. On the sidewall of the first opening located on the third semiconductor layer,
A first sidewall insulating layer is formed. First side
The second and third layers are formed by using the wall insulating layer as a mask.
A second opening is formed that partially penetrates the semiconductor layer.
So as to fill the second opening and cover the second insulating layer.
A fourth insulating layer is formed. The fourth insulating layer and the first support
By reducing the thickness of the sidewall insulation layer, the third
The upper surface of the semiconductor layer is exposed and the fourth opening is formed in the second opening.
Retain the insulating layer. A second conductive layer is formed on the upper surface of the third semiconductor layer.
Forming an electrode layer.

[0021]

According to the MIS transistor of the present invention, the insulating layer is formed inside the second semiconductor layer. As a result, the second narrowed by the insulating layer and the gate insulating layer
The thickness of the semiconductor layer, that is, the thickness of the channel formation region of the MIS transistor in the depth direction can be adjusted. Specifically, the thickness of the second semiconductor layer can be adjusted to about 200 nm or less. Thereby, by applying a predetermined potential to the gate electrode, it becomes possible to invert the entire region in the second semiconductor layer. Therefore, it is possible to prevent the generation of capacitance due to the formation of a junction under the channel region. As a result, a MIS transistor having improved transistor characteristics such as subthreshold characteristics can be obtained. In addition, the first to the vertical directions of the main surface of the semiconductor substrate
Since the MIS type transistor is formed by stacking the third semiconductor layers, the area occupied by one MIS type transistor on the main surface of the semiconductor substrate can be reduced. Thereby, high integration of the MIS type transistor is possible.

According to the method for manufacturing a MIS transistor according to the present invention, it is possible to form a MIS transistor having an insulating layer buried in at least a hole penetrating the second semiconductor layer. This makes it possible to form a highly integrated MIS transistor with improved transistor characteristics.

[0023]

EXAMPLES Hereinafter, the embodiment according to the present invention will be described with reference to FIGS. 1 to 42.

[0024] (First Embodiment) First, with reference to FIGS. 1 to 11, a description will be given of a first embodiment according to the present invention. 1 is a sectional view showing a MIS type transistor manufactured by a manufacturing method of a first embodiment according to the present invention .

Referring to FIG. 1, an n-type impurity diffusion layer 3 is formed on the main surface of a p-type semiconductor substrate (p-type silicon substrate) 1. Further, on the main surface of p type semiconductor substrate 1, element isolation insulating layer 2 made of a silicon oxide film or the like partially overlapping n type impurity diffusion layer 3 is formed. A first interlayer insulating layer 4 made of a silicon oxide film or the like is formed so as to cover the element isolation insulating layer 2. This first
A gate electrode 5 made of polycrystalline silicon or the like patterned into a predetermined shape is formed on the interlayer insulating layer 4.
A second interlayer insulating layer 6 made of a silicon oxide film or the like is formed so as to cover the gate electrode 5 and the first interlayer insulating layer 4.

The above-mentioned first and second interlayer insulating layers 4, 6
And a first opening 7 is formed so as to partially penetrate the gate electrode 5 and reach the surface of the n-type impurity diffusion layer 3. An insulating layer 8 is formed on the side wall of the first opening 7. On the surface of this insulating layer 8, n-type silicon epitaxial layers 9 and 11 and a p-type silicon epitaxial layer 10 are formed.

The above n-type silicon epitaxial layer 11
And the p-type silicon epitaxial layer 10 are partially penetrated, and the second opening 16 is formed so as to reach the inside of the n-type silicon epitaxial layer 9. The buried insulating layer 1 made of a silicon oxide film or the like is formed in the second opening 16.
4 is formed. A wiring layer 15 is formed on the buried insulating layer 14 and the n-type silicon epitaxial layer 11.

In the above structure, the MIS transistor has the gate electrode 5, the insulating layer 8 functioning as a gate insulating layer, the n-type silicon epitaxial layers 9 and 11 serving as the source / drain regions, and the p region serving as the channel region. Type silicon epitaxial layer 10. At this time, as shown in FIG. 1, by providing the buried insulating layer 14 at least inside the p-type silicon epitaxial layer 10, it is possible to effectively prevent a pn junction from being formed at a position away from the gate electrode 5. It becomes possible to do. As a result, it is possible to effectively prevent the occurrence of parasitic capacitance due to the formation of the pn junction at a position away from the gate electrode 5. As a result, a MIS transistor having improved transistor characteristics such as subthreshold characteristics can be obtained.

Therefore, the buried insulating layer 14 is preferably provided so as to penetrate at least in the vicinity of the central portion of the upper surface of the p-type silicon epitaxial layer 10.
As a result, p existing at a position away from the gate electrode 5
It is possible to effectively prevent the formation of the n-junction.

Although the buried insulating layer 14 is provided so as to partially penetrate the n-type silicon epitaxial layer 11 and the p-type silicon epitaxial layer 10 in the embodiment shown in FIG. The embedded insulating layer 14 is provided inside the p-type silicon epitaxial layer 10 at a position away from the gate electrode 5 as long as the thickness of the p-type silicon epitaxial layer 10 can be substantially reduced. As a result, it is possible to effectively prevent the generation of capacitance due to the formation of the pn junction at a position away from the gate electrode 5.

Further, by appropriately adjusting the plane width W'of the buried insulating layer 14, the n-type silicon epitaxial layers 9 and 11 functioning as a MIS transistor and p.
The plane width W with respect to the type silicon epitaxial layer 10 can be adjusted to a desired value. More specifically, FIG. 4
Even when the planar structure of the laminated structure of the n-type silicon epitaxial layers 9 and 11 and the p-type silicon epitaxial layer 10 needs to be about 1 μm as in the conventional example shown in FIG. By setting the plane width W ′ to 0.8 μm, the plane width W can be set to about 0.1 μm. This makes it possible to improve the performance of the MIS transistor.

As shown in FIG. 1, the n-type silicon epitaxial layer 9, the p-type silicon epitaxial layer 10, and the n-type silicon epitaxial layer 11 are connected to p
Major surface and vertical type semiconductor substrate 1, i.e., by vertically stacked, as in the conventional example shown in FIG. 44, MIS than the conventional case shown in FIG. 43
It becomes possible to highly integrate the type transistor. As described above, it is possible to obtain a MIS transistor that can be highly integrated and has improved transistor characteristics.

Next, a method of manufacturing the MIS type transistor according to this embodiment will be described with reference to FIGS. 2 to 10 are sectional views showing the first to ninth steps of the manufacturing process of the MIS transistor according to the first embodiment of the present invention.

First, referring to FIG. 2, a silicon oxide film having a thickness of about 100 nm is formed on the main surface of p type semiconductor substrate 1 by a CVD (Chemical Vapor Deposition) method or a thermal oxidation method. Then, this silicon oxide film is patterned by using the photoengraving technique and the etching technique. Thereby, the element isolation insulating layer 2 is formed. Next, an n-type impurity such as As is ion-implanted into the main surface of the p-type semiconductor substrate 1. Then, a thermal diffusion process is performed to form the impurity diffusion layer 3. The concentration of the impurity diffusion layer 3 is preferably 10 ¹⁹ to 10 ²⁰ cm
^{-It is} about ^-3 . The specific resistance of the p-type semiconductor substrate 1 is 8
It is about 11 Ωcm.

Next, referring to FIG. 3, p-type semiconductor substrate 1
Of the entire main surface of the
First made of a silicon oxide film having a thickness of about 00 nm
The inter-layer insulating layer 4 is formed. A polycrystalline silicon layer having a thickness of, for example, about 400 nm is formed on this first interlayer insulating layer 4 by the CVD method or the like. Then, the polycrystalline silicon layer is patterned into a predetermined shape to form the gate electrode 5.

At this time, the thickness of the gate electrode 5 is M
Determine the gate length of the IS transistor. Sunachiwa,
In this case, the gate length of the MIS type transistor is about 400 nm. The material of the gate electrode 5 has a single layer structure as long as it is made of at least one material selected from a silicide layer of transition metal, a metal nitride layer, a refractory metal layer and a polycrystalline silicon layer. Alternatively, it may have a multilayer structure. Next, the second interlayer insulating layer 6 made of, for example, a silicon oxide film having a thickness of about 400 nm is formed by using the CVD method or the like.

Next, referring to FIG. 4, the first and second interlayer insulating layers 4 and 6 and the gate electrode 5 are partially formed in a region where a transistor is to be formed by using a photolithography technique and an etching technique. First opening 7 is formed that penetrates through and reaches the surface of n-type impurity diffusion layer 3. The planar shape of the first opening 7 is preferably a circle having a diameter of about 1 μm. However, the plane shape of the first opening 7 is an ellipse,
Any shape such as a polygon (triangle, quadrangle, pentagon, hexagon, etc.) or a shape in which the corners of the polygon are rounded may be used.

Then, referring to FIG. 5, a silicon oxide film having a thickness of, for example, about 20 nm is formed on the entire surface by CVD or the like. Anisotropic etching is applied to the silicon oxide film by using the RIE (Reactive Ion Etching) method or the like. Thereby, the insulating layer 8 is formed. The material of the insulating layer 8 may be a silicon oxide film, a silicon nitride film, a multilayer film of a silicon oxide film and a silicon nitride film, or the like.

Next, referring to FIG. 6, the n-type silicon epitaxial layer 9 is formed by the selective epitaxial growth method.
The p-type silicon epitaxial layer 10 and the n-type silicon epitaxial layer 11 are sequentially formed. Regarding the selective epitaxial growth method, JO Borland & I. Beinglass, Sol
Since it is disclosed in id State Technology, January, 1990, P.73, etc., detailed description will be omitted.
iH ₂ Cl ₂ , H ₂ , HCl, AsH ₃ for doping
Silicon can be epitaxially grown by a thermal CVD method using a gas such as B ₂ H ₆ or B ₂ .

More specifically, in the case of this embodiment, As
Alternatively, n doped with P of about 10 ¹⁹ to 10 ²⁰ cm ^-3
The type silicon epitaxial layer 9 is formed to the same thickness as the first interlayer insulating layer 4. Then, p-type impurities such as B are 1
A p-type silicon epitaxial layer 10 doped with about 0 ¹⁶ to 10 ¹⁷ cm ⁻³ is formed in the same thickness as the gate electrode 5. Next, an n-type impurity such as As or P is added to 10 ^19-
The n-type silicon epitaxial layer 11 doped with about 10 ²⁰ cm ⁻³ is formed so that its upper surface is located at a position lower than the upper surface of the second interlayer insulating layer 6.

An n-type impurity such as As is contained between at least one of the n-type silicon epitaxial layers 9 and 11 and the p-type silicon epitaxial layer 10.
^An LDD (Lightly Doped Drain) structure may be formed by forming a low-concentration layer doped at about ¹⁷ to 10 ¹⁸ cm ^-3 .
Further, by appropriately adjusting the thicknesses of the n-type silicon epitaxial layers 8 and 11 and the p-type silicon epitaxial layer 10, the above-mentioned low concentration layer and the gate electrode 5 may be overlapped. In this case, a transistor having a so-called GOLD (Gate-Drain overlapped Device) structure is formed. Regarding this GOLD structure transistor, R. IZAWA et al. IEEE Transactions
On Electron Devices, Vol. 35, 1988, P. 2088.

Further, the thickness of the first interlayer insulating layer 4 may be as thin as 20 nm as long as the insulating property between the gate electrode 5 and the p-type semiconductor substrate 1 is maintained. In this case, the thickness of the silicon epitaxial layer 9 can be reduced accordingly.

Then, referring to FIG. 7, a silicon oxide film having a thickness of, for example, about 100 nm is formed on the entire surface by CVD or the like. Then, an anisotropic etching process is applied to the silicon oxide film by using the RIE method or the like. Thereby, the sidewall insulating layer 12 is formed. Therefore, the plane width W of the sidewall insulating layer 12 is about 100 nm in this case. A silicon nitride film may be used as the material of the sidewall insulating layer 12.

Next, referring to FIG. 8, using the sidewall insulating layer 12 as a mask, the n-type silicon epitaxial layer 11 and the p-type silicon epitaxial layer 1 are formed.
Anisotropic etching is sequentially performed on the 0, n-type silicon epitaxial layer 9 by the RIE method. Thereby, the second opening 16 is formed so as to partially penetrate the n-type silicon epitaxial layer 11 and the p-type silicon epitaxial layer 10 and have the bottom surface in the n-type silicon epitaxial layer 9.

At this time, M remaining in the first opening 7
The plane widths of the n-type silicon epitaxial layers 9 and 11 and the p-type silicon epitaxial layer 10 functioning as the source / drain regions of the IS-type transistor are substantially equal to the plane width W of the sidewall insulating layer 12. More specifically, the plane width W is, in this case,
It becomes as thin as about 100 nm. As a result, a MIS transistor having excellent transistor characteristics can be obtained. In addition,
The plane width W of the n-type silicon epitaxial layer 11 and the p-type silicon epitaxial layer 10 is appropriately determined by the plane width W of the sidewall insulating layer 12.

Next, referring to FIG. 9, insulating layer 13 made of, for example, a silicon oxide film is formed by the CVD method or the like.
Are formed on the entire surface. At this time, the inside of the second opening 16 is filled with the insulating layer 13.

Next, a resist etch back method or a polishing method (CMP (Chemical Mechanical Polishing) method)
And the like, the insulating layer 13, the sidewall insulating layer 12
And the thickness of the second interlayer insulating layer 6 is reduced. Thereby, as shown in FIG. 10, the buried insulating layer 14 is formed in the second opening 16 and the upper surface of the n-type silicon epitaxial layer 11 is exposed. Regarding the above polishing method, see D. Webb et al., VMIC Conference, 1992, P.
141 and the like.

Next, a conductive layer made of a WSi ₂ layer, a polycrystalline silicon layer or the like is formed on the n-type silicon epitaxial layer 11 and the buried insulating layer 14 by using a sputtering method or a CVD method. Then, the conductive layer is patterned by using the photolithography technique and the etching technique. Thereby, the wiring layer 15 is formed.

The second interlayer insulating layer 6 may have a thickness as long as the insulating property between the wiring layer 15 and the gate electrode 5 is maintained, and may be as thin as about 20 nm. . In this case, the thickness of the n-type silicon epitaxial layer 11 can be reduced to about 20 nm. Through the above steps, the MIS transistor according to the first embodiment shown in FIG. 1 is formed.

Thereafter, various VLSI chips (such as formation of further interlayer insulating layers, formation of metal wirings, connection with elements such as other transistors and capacitors, formation of passivation films, and assembly process) are carried out as necessary. (Not shown) is completed.

In the above manufacturing method, the sidewall insulating layer 12 is formed in a self-aligned manner, and the
Was used as a mask for forming the opening 16 of the second opening. Instead of the sidewall insulating layer 12, a resist pattern was formed by a photolithography technique, and the resist pattern was used as a mask to perform an etching process to form the second opening. The part 16 may be formed.

The material of the wiring layer 15 is metal (W, T
i, Mo, Co, Ni, Fe, Al, Cu, Ag, T
a, Au, etc.) or a conductive material such as metal nitride. Further, as a method of doping the silicon epitaxial layer, ion doping may be used after forming each silicon epitaxial layer.

Further, instead of the silicon epitaxial layer, Si _1-x Ge _x (0 ≦ x ≦ 1) may be epitaxially grown by the CVD method. In particular, by using Si _1-x Ge _x instead of the above-mentioned p-type silicon epitaxial layer 10 (channel forming region), a device faster than PMOS can be obtained. Regarding this, S. Subbanna et al., Symposium on VLSI Technology,
1991, P.103, etc.

Further, although the example of the enhancement type NMOS is shown in this embodiment, it is also possible to form a depletion type NMOS. In that case, p
The type silicon epitaxial layer 10 may be an n type silicon epitaxial layer. Furthermore, in the above-described first embodiment, the case of forming the NMOS has been described, but the PMOS can also be formed by changing the conductivity type.

Next, referring to FIG. 11, the manufacturing method of this embodiment will be described.
A modified example of the MIS transistor obtained by the method will be described . Referring to FIG. 11, the difference from the MIS transistor shown in FIG.
It is whether or not it is formed so as to surround the entire side surface of the type silicon epitaxial layer 10.

More specifically, in the MIS transistor shown in FIG. 1, the insulating layer 8 is formed on the side surface of the p-type silicon epitaxial layer 10 so that the gate electrode 5 surrounds the side surface of the p-type silicon epitaxial layer 10. Are formed by interposing. On the other hand, M in this modification
In the IS transistor, the gate electrode 5 is formed so as to face only part of the side surface of the p-type silicon epitaxial layer 10. Specifically, for example, the first
When the planar shape of the opening 7 is circular, only the semicircular portion is surrounded by the gate electrode 5. The other structure is the same as that of the MIS type transistor shown in FIG.

[0057]

[0058]

[0059]

[0060]

[0061]

(Second Embodiment) Next, referring to FIGS. 12 to 16 , a second embodiment of the present invention will be described.
An example will be described. FIG. 12 is a sectional view showing a MIS type transistor manufactured by the manufacturing method of the second embodiment according to the present invention.

[0063] With reference to FIG. 12, the first embodiment of the
Whether differences in structure between the MIS transistor manufactured by the manufacturing method of the MIS-type transistor and the present embodiment produced by the production method, the metal silicide layer 17a is formed on part of the surface of the n-type impurity diffusion layer 3 It is. The other structures are the same as those in the first embodiment.
This is similar to the MIS type transistor manufactured by the manufacturing method of 1 .

By forming the metal silicide layer 17a on the surface of the n-type impurity diffusion layer 3 as described above,
The sheet resistance of the n-type impurity diffusion layer 3 can be reduced. In the structure shown in FIG. 12 , the n-type impurity diffusion layer 3 is used as it is as a wiring layer. Therefore, the sheet resistance of the n-type impurity diffusion layer 3 is reduced, so that the wiring resistance is reduced. As a result, it becomes possible to improve the performance of the device in which the MIS transistor according to the present embodiment is incorporated.

Next, with reference to FIGS. 13 to 15, a method for producing the M IS transistors Ru shown in FIG. 13 to 15 are cross-sectional views showing characteristic first to third steps of the manufacturing process of the MIS type transistor according to the present embodiment.

First, referring to FIG. 13 , the element isolation insulating layer 2 and the n-type impurity diffusion layer 3 are formed through the same steps as those in the first embodiment. Next, a metal layer 17 such as Ti is formed on the entire surface by using a sputtering method or the like. The thickness of this metal layer 17 is preferably about 30 nm. Next, heat treatment is performed in an N ₂ atmosphere at 800 ° C. for about 30 seconds. Then, the unreacted Ti (metal) layer 17 is removed by a chemical such as H ₂ SO ₄ / H ₂ O ₂ . afterwards,
Further, heat treatment is performed in an N ₂ atmosphere at 850 ° C. for about 30 seconds. Thereby, the metal silicide layer (TiSi ₂ layer in this case) 17a is formed on the surface of the n-type impurity diffusion layer 3.

Next, referring to FIG. 15 , the first interlayer insulating layer 4, the gate electrode 5, and the second interlayer insulating layer 6 are sequentially formed by the same method as in the case of the first embodiment. To do. After that, using photoengraving technology and etching technology, the first
The opening 7 is formed. At this time, the metal silicide layer 17a located under the first opening 7 is also removed to expose a part of the surface of the n-type impurity diffusion layer 3. M Then, through the same steps as the first embodiment described above, as shown in FIG. 12
An IS type transistor is formed. The reason why the metal silicide layer 7a is removed and a part of the surface of the impurity diffusion layer 3 is exposed is that silicon cannot be epitaxially grown on the metal silicide layers having different crystal structures. In the case of a metal silicide such as CoSi ₂ having a crystal structure similar to silicon, it is theoretically possible to epitaxially grow silicon on the metal silicide. However, in order to obtain a better crystal, it is better to expose silicon and perform epitaxial growth as in this example.

Next, with reference to FIG. 16, a description will be given of modifications of the above-described manufacturing method. This modification was devised to solve the first problem of concern during the formation of the opening 7 shown in FIG. 15.

In forming the first opening 7 in FIG. 15 , it is conceivable that the junction between the n-type impurity diffusion layer 3 and the p-type semiconductor substrate 1 may be destroyed by overetching. In this case, as shown in FIG. 16 , after forming the first opening 7, an n-type impurity such as As is added to the p-type again.
By implanting into the main surface of type semiconductor substrate 1, n type impurity diffusion layer 3c is formed. Thereby, even if the junction between the n-type impurity diffusion layer 3 and the p-type semiconductor substrate 1 is destroyed by the above-described overetching, the junction between the N-type impurity diffusion layer 3c and the p-type semiconductor substrate 1 is formed again. Is possible. This makes it possible to ensure the reliability of the MIS transistor.

Although the n-type impurity diffusion layer 3 is formed before the formation of the metal silicide layer 17a in the present embodiment, the ion implantation method and the thermal diffusion method are used after the formation of the metal silicide layer 17a. The n-type impurity diffusion layer 3 may be formed.

Further, in the above-mentioned embodiment, the metal silicide layer 17a is formed by the salicide method.
The metal silicide layer 17a may be formed by forming the metal silicide layer itself on the entire surface by a sputtering method or the like and patterning it into a predetermined shape by using a photoengraving technique and an etching technique. In this case, the metal silicide layer 17a can be formed also on the element isolation insulating layer 2. Thereby, the metal silicide layer 1
The planar shape of 7a can be made various shapes.

Further, in the process shown in FIG. 15 , the metal silicide layer 17a is n-typed when the first opening 7 is formed.
The metal silicide layer 17a is left on the entire surface of the type impurity diffusion layer 3, and after the insulating layer 8 formed in a later step is formed, the insulating layer 8 and the second interlayer insulating layer 6 are used as a mask. May be patterned.

(Third Embodiment) Next, the figure17And figure18Based on this invention
A third embodiment will be described. Figure17And figure18
Is a manufacturing process of the MIS transistor in this embodiment.
FIG. 6 is a sectional view showing a characteristic first step and a second step of FIG.
It

In the above-mentioned first embodiment, the insulating layer 8 functioning as the gate insulating layer is formed by the CVD method. However, the gate insulating layer may be formed by a thermal oxidation method. Referring to FIG. 17 , the steps up to the first opening 7 are formed through the same steps as those in the first embodiment. Next, heat treatment at about 900 ° C. is applied to the inner surface of the first opening 7 in an O ₂ atmosphere. As a result, the thermal oxide film 18 is formed on the surface of the gate electrode 5 exposed in the first opening 7.
At this time, at the same time, the thermal oxide film 19 is also formed on the surface of the n-type impurity diffusion layer 3 exposed in the first opening 7.

Then, referring to FIG. 18 , the thermal oxide film 19 formed on the surface of the n-type impurity diffusion layer 3 is removed by performing anisotropic etching treatment using the RIE method.
At this time, since the etching by the RIE method is anisotropic etching, the thermal oxide film 18 formed on the side wall of the first opening 7 is not etched. After that, the above 1st
The MIS transistor of this embodiment is formed through the same steps as those of the above embodiment.

In this embodiment, the gate electrode 5
It is preferable to select a material containing excessive silicon as the material. For example, the material of the gate electrode 5 may be a silicide layer containing excess silicon such as TiSi _2.3 or a laminated structure of such a silicide layer and a polycrystalline silicon layer. In this case, excess silicon contained in the metal silicide layer or silicon supplied from polycrystalline silicon is oxidized to form a high-quality silicon oxide film. As a result, the characteristics of the transistor can be improved.

(Fourth Embodiment) Next, referring to FIGS. 19 to 23 , a fourth embodiment of the present invention will be described.
An example will be described. FIG. 19 is a sectional view showing a MIS transistor manufactured by the manufacturing method according to the fourth embodiment of the present invention.

With reference to FIG. 19 , the manufacturing method of this embodiment will be described.
Therefore, in the manufactured MIS type transistor , n
A buried insulating layer 14 is formed so as to penetrate through the silicon epitaxial layer 9. The other structure is similar to that of the first embodiment shown in FIG.

Next, with reference to FIGS. 20 to 23 , a method of manufacturing the MIS type transistor in this embodiment will be described. 20 to 23 are cross-sectional views showing characteristic first to fourth steps of the manufacturing process of the MIS transistor according to the present embodiment.

First, referring to FIG. 20 , the insulating layer 8 is formed through the same steps as those in the first embodiment. Next, the silicon nitride film 37 is formed on the entire surface by using the CVD method or the like.
To form. This silicon nitride film 37 is subjected to anisotropic etching treatment using the RIE method or the like. As a result, the silicon nitride film 37 is left on the sidewall of the first opening 7.

Next, a silicon oxide film is formed on the entire surface by using the CVD method or the like. Then, the surface is flattened by the above-mentioned polishing method or the like. Thereby, as shown in FIG. 21, to form the buried insulating layer 14.

Then, referring to FIG. 22 , the silicon nitride film 37 is removed using hot phosphoric acid or the like. Thereby,
A second opening 38 that exposes a part of the surface of the n-type impurity diffusion layer 3 is formed.

Next, referring to FIG. 23 , in the same manner as in the above-mentioned first embodiment, on the surface of n-type impurity diffusion layer 3,
Selectively, the n-type silicon epitaxial layer 9, the p-type silicon epitaxial layer 10, and the n-type silicon epitaxial layer 11 are sequentially formed. After that, the MIS transistor shown in FIG. 19 is formed through the same steps as those in the first embodiment.

In this embodiment, the insulating layer 8 may be formed by the thermal oxidation method as in the case of the third embodiment.

(Fifth Embodiment) Next, referring to FIGS. 24 to 34 , a fifth embodiment of the present invention will be described.
An example will be described. FIG. 24 is a cross-sectional view showing a MIS type transistor manufactured by the manufacturing method of the fifth embodiment according to the present invention.

Referring to FIG. 24 , a groove is formed in the main surface of p type semiconductor substrate 1, and the first and second grooves are formed in the groove.
Are filled with the interlayer insulating layers 21 and 22. A second opening 36 is provided on the main surface of the p-type semiconductor substrate 1,
A buried insulating layer 27 is formed in the second opening 36. Then, on the main surface of the p-type semiconductor substrate 1 along the buried insulating layer 27, the n-type impurity diffusion layers 26 and 20 to be the source / drain regions of the MIS transistor and the p-type impurities to be the channel region of the MIS transistor are formed. Diffusion layer 25
And are formed. Then, the gate electrode 24 is formed at a position facing the side surface of the p-type impurity diffusion layer 25 so as to surround the p-type impurity diffusion layer 25. n-type impurity diffusion layer 2
A wiring layer 28 is formed on 6 and the embedded insulating layer 27. Also in the structure of this embodiment, the same effect as in the case of the first embodiment can be obtained.

Next, with reference to FIGS. 25 to 34 , a method of manufacturing the MIS transistor of this embodiment will be described. 25 to 34 are cross-sectional views showing the first to tenth steps of the manufacturing process of the MIS transistor in this example.

First, referring to FIG. 25 , a p-type semiconductor substrate 1 having a main surface doped with about 10 ¹⁶ to 10 ¹⁷ cm ⁻³ of p-type impurities such as boron (B) is prepared. And this p
A silicon nitride film 30 patterned into a predetermined shape is formed on the main surface of mold semiconductor substrate 1 by using a CVD method and an etching technique. Using silicon nitride film 30 as a mask, the main surface of p-type semiconductor substrate 1 is etched by about 0.6 μm, for example. Thereby, the first groove portion 31 is formed on the main surface of the p-type semiconductor substrate 1.

Then, referring to FIG. 26 , a silicon oxide film having a thickness of about 0.1 μm is formed on the entire surface by CVD or the like. This silicon oxide film is anisotropically etched by the RIE method or the like. Thereby, the sidewall insulating layer 32 is formed on the sidewall of the first groove portion 31.

Then, referring to FIG. 27 , main surface of p type semiconductor substrate 1 is further etched by about 0.3 μm using silicon nitride film 30 and sidewall insulating layer 32 as a mask. Thereby, the second groove portion 33 that is continuous with the first groove portion 30 is formed. Next, the n-type impurity diffusion layer 20 is formed on the surface of the second groove 33 in the main surface of the p-type semiconductor substrate 1 by using the ion implantation method and the thermal diffusion method. The concentration of the n-type impurity diffusion layer 20 is preferably
It is about 10 ¹⁹ to 10 ²⁰ cm ^-3 . At this time, the impurity diffusion layer is not formed in the portion covered with the silicon nitride film 30 and the silicon oxide film 32.

Then, referring to FIG. 28 , a silicon oxide film is formed on the entire main surface of p type semiconductor substrate 1 by the CVD method or the like. By etching back the silicon oxide film, the first interlayer insulating layer 21 filling the second groove 33 is formed.

Next, referring to FIG. 29 , a heat treatment is performed at 900 ° C. in an O ₂ atmosphere to form first groove 31.
An insulating layer (thermal oxide film) 23 is formed on the side wall of the. This thermal oxide film 23 becomes a gate insulating layer. Next, a conductive layer made of, for example, polycrystalline silicon doped with impurities is formed on the entire surface by using the CVD method or the like. Then, the conductive layer 24 is subjected to anisotropic etching treatment by using the RIE method or the like. As a result, the gate electrode 24 is formed on the surface of the insulating layer 23.
To form.

At this time, the height of the upper surface of the gate electrode 24 is appropriately adjusted by appropriately adjusting the above RIE conditions. This ensures the insulation between the wiring layer 28 and the gate electrode 24 which will be formed in a later step.

Then, referring to FIG. 30 , a silicon oxide film 22 is formed on the entire surface by the CVD method or the like. Then, the thickness of the silicon oxide film 22 is reduced by an etch back method or a polishing method. Thereby, the surface of the silicon nitride film 30 is exposed.

Next, the silicon nitride film 30 is removed by etching using hot phosphoric acid or the like. Thereby, as shown in FIG. 31 , a third groove 34 is formed to partially expose the main surface of the p-type semiconductor substrate. Then, an n-type impurity such as As is ion-implanted into the main surface of the p-type semiconductor substrate 1 exposed at the bottom of the third groove 34. Then, a thermal diffusion process is performed to obtain 10 ¹⁹
An n-type impurity diffusion layer 26 having a concentration of about 10 ²⁰ cm ^-3 is formed.

Then, referring to FIG. 32 , the sidewall insulating layer 35 is formed on the sidewall of the third groove 34 by the CVD method and the RIE method. The material of the sidewall insulating layer 35 is preferably a silicon oxide film. The plane width of the side wall insulating layer 35 is preferably the side wall 12 in the first embodiment.
Is equal to the width of the plane.

Then, referring to FIG. 33 , main surface of p type semiconductor substrate 1 is etched using sidewall insulating layer 35 and second interlayer insulating layer 22 as a mask. Thereby, a fourth groove portion 36 reaching the n-type impurity diffusion layer 20 is formed on the main surface of the p-type semiconductor substrate 1.

Referring to FIG. 34 , the upper surface of n-type impurity diffusion layer 26 is exposed and the buried insulating layer is buried in fourth groove 36 in the same manner as in the first embodiment. 27 is formed. The material of the buried insulating layer 27 is preferably a silicon oxide film.

After that, the wiring layer 28 made of WSi ₂ or the like is formed by the same method as in the first embodiment. Thereby, so that the M IS transistors Ru shown in Figure 24 is formed.

In the step shown in FIG. 33 ,
The fourth groove 36 was formed by using the sidewall insulating layer 35 as a mask. However, as in the case of the first embodiment described above, a resist pattern may be formed and the fourth groove 36 may be formed using this resist pattern as a mask. Also, manufactured by the manufacturing method of this embodiment.
As for the material of each constituent element of the MIS transistor, the material corresponding to that of the above-described first embodiment can be the same as that of the above-described first embodiment.

(Sixth Embodiment) Next, referring to FIGS. 35 to 37 , a sixth embodiment of the present invention will be described.
An example will be described. FIG. 35 is a sectional view showing a MIS type transistor according to the sixth embodiment of the present invention.

Referring to FIG. 35 , in the present embodiment,
A third interlayer insulating layer 39 is formed on the second interlayer insulating layer 6, and a via hole 40 is provided in a portion of the third interlayer insulating layer 39 located on the first opening 7. . The opening width of the via hole 40 is preferably larger than the opening width of the first opening 7.

In addition, the n-type silicon epitaxial layer 11
It is preferable that the via hole 40 be provided so that the upper surface and a part of the side surface thereof protrude from the bottom surface of the via hole 40.
That is, the bottom surface of the via hole 40 is preferably located below the top surface of the n-type silicon epitaxial layer 11. Then, the wiring layer 15 is formed so as to cover the surface of the n-type silicon epitaxial layer 11 protruding on the bottom surface of the via hole 40 in this manner. Thereby, the wiring layer 15
It is possible to increase the contact area between the n-type silicon epitaxial layer 11 and. As a result, the contact resistance between the wiring layer 15 and the silicon epitaxial layer 11 can be reduced. Figure 1 for other structures
It is the same as the M IS-type transistor is Ru shown.

[0104] Next, with reference to FIGS. 36 and 37, FIG. 3
A method of manufacturing the MIS type transistor shown in 5 will be described. 36 and 37 show M in this embodiment.
It is sectional drawing which shows the characteristic 1st process and 2nd process of the manufacturing process of IS type transistor.

First, referring to FIG. 36 , the buried insulating layer 14 is formed through the same steps as those in the first embodiment. Then, a third interlayer insulating layer 39 made of a silicon oxide film or the like is formed on the entire surface by using the CVD method or the like.

Next, referring to FIG. 37 , the first opening 7
A via hole 40 is formed by etching the third interlayer insulating layer 39 located above. At this time, the formation position of the via hole 40, as shown in FIG. 37, may be slightly shifted with the formation position of the first opening 7. As described above, the bottom surface of the via hole 40 is n
Since it is formed so as to be located below the upper surface of the n-type silicon epitaxial layer 11, a large contact area can be secured between the wiring layer 15 formed in a later step and the surface of the n-type silicon epitaxial layer 11. . The opening width of the via hole 40 may be larger than the opening width of the first opening 7. From the above, via hole 4
The formation of 0 becomes easy.

After that, the wiring layer 15 made of a conductive material such as WSi _{2 is formed by} the same method as in the first embodiment.
To form. Through the above steps, MI shown in FIG. 35
An S-type transistor will be formed.

(Seventh Embodiment) Next, referring to FIGS. 38 to 42 , a seventh embodiment of the present invention will be described.
An example will be described. FIG. 38 is a cross-sectional view showing a MIS type transistor manufactured by the manufacturing method according to the seventh embodiment of the present invention.

First, with reference to FIG. 38 , a manufacturing method of this embodiment.
In the MIS type transistor manufactured by the method , the n-type silicon epitaxial layers 9 and 11, the p-type silicon epitaxial layer 10 and the wiring layer 15 are formed in one first opening 7c. Thereby,
As a result, the thickness of the n-type silicon epitaxial layer 11 becomes smaller than the thickness of the second interlayer insulating layer 6 located on the gate electrode 5. The specific resistance of the n-type silicon epitaxial layer 11 is significantly higher than the specific resistance of the metal silicide layer or the metal layer. Therefore, by reducing the thickness of the n-type silicon epitaxial layer 11,
It is possible to reduce the parasitic resistance of the MIS transistor. That is, a high-performance MIS type transistor can be obtained. Preferably, the n-type silicon epitaxial layer 11 has a thickness of about 0.2 μm. The other structure is the same as that of the MIS type transistor in the first embodiment shown in FIG.

Next, with reference to FIGS. 39 to 42 , a method of manufacturing the MIS transistor of this embodiment will be described. 39 to 42 are cross-sectional views showing characteristic first to fourth steps of the method of manufacturing the MIS transistor in this example.

First, referring to FIG. 39 , the steps up to the second interlayer insulating layer 6 are formed through the same steps as those in the first embodiment. Then, a silicon nitride film 41 is formed on the second interlayer insulating layer 6 by using the CVD method or the like.

Then, referring to FIG. 40 , the first opening 7c reaching the surface of the n-type impurity diffusion layer 3 is formed by using the etching technique as in the first embodiment.
Next, the insulating layer 8 is formed on the side wall of the first opening 7c by the same method as in the first embodiment, and the n-type impurity diffusion layer 3 is formed.
An n-type silicon epitaxial layer 9, a p-type silicon epitaxial layer 10, and an n-type silicon epitaxial layer 11 are sequentially formed on the surface.

At this time, the upper surface of the n-type silicon epitaxial layer 11 is made sufficiently lower than the surface of the second interlayer insulating layer 6. For example, the thicknesses of the second interlayer insulating layer 6 and the n-type silicon epitaxial layer 11 are determined such that the upper surface of the n-type silicon epitaxial layer 11 is lower than the upper surface of the second interlayer insulating layer 6 by about 1 μm. It is preferable.

Then, the sidewall insulating layer 12 is formed on the upper surface of the n-type silicon epitaxial layer 11 by the same method as in the first embodiment. Then, so as to fill the inside of the first opening 7c and cover the silicon nitride film 41,
The insulating layer 42 made of a silicon oxide film or the like is formed by using the CVD method or the like.

Then, referring to FIG. 41 , the insulating layer 44 is subjected to an etch back process to form the silicon nitride film 4
Exposing the surface of 1. At this time, the first opening 7c is filled with the insulating layer 42.

Next, referring to FIG. 42 , the insulating layer 42 is further subjected to etching treatment using the silicon nitride film 41 as a mask. Thereby, the upper surface of the n-type silicon epitaxial layer 11 is exposed. As a result, the buried insulating layer 14 is formed. At this time, by having the silicon nitride film 41, the thickness of the second interlayer insulating layer 6 cannot be reduced. As a result, the wiring layer 15 formed in a later step
It is possible to reliably ensure the insulation between the gate electrode 5 and the gate electrode 5.

After that, the silicon nitride film 41 is removed by using hot phosphoric acid or the like. Then, the wiring layer 15 made of the same material as in the case of the first embodiment is formed by using the CVD method or the sputtering method, the photoengraving technique, and the etching technique. So that the M IS-type transistor is Ru shown in Figure 38 is formed through the above steps.

[0118]

As described above, according to the present invention, the first and third semiconductor layers serving as the source / drain regions of the MIS transistor and the second semiconductor layer serving as the channel region of the MIS transistor are provided. Are stacked in a direction perpendicular to the main surface of the semiconductor substrate, that is, in the vertical direction. Thereby, high integration of the MIS type transistor is possible. In addition, an insulating layer is formed inside the second semiconductor layer at a position spaced apart from the gate electrode by a predetermined distance. As a result, it is possible to effectively prevent a pn junction from being formed at a position apart from the gate electrode of the MIS type transistor and generating a capacitance. As a result, a high-performance MIS transistor with improved transistor characteristics such as subthreshold characteristics can be obtained. From the above,
According to the present invention, it is possible to obtain a MIS transistor which can be highly integrated and have high performance.

[Brief description of drawings]

[1] manufactured by the manufacturing method of the first embodiment of the inventions
It is sectional drawing which shows the produced MIS type transistor.

2 is a sectional view showing the first embodiment first step that you <br/> only to the production method of which is based on the present invention.

3 is a cross-sectional view showing a contact <br/> only that second step in the production method of the first embodiment according to the present invention.

4 is a cross-sectional view showing a third step that you <br/> only to the manufacturing method of the first embodiment according to the present invention.

5 is a sectional view showing a fourth step that you <br/> only to the manufacturing method of the first embodiment according to the present invention.

6 is a sectional view showing a first embodiment fifth step that you <br/> only to the production method of which is based on the present invention.

7 is a sectional view showing a sixth step that you <br/> only to the manufacturing method of the first embodiment according to the present invention.

8 is a sectional view showing a seventh step that you <br/> only to the manufacturing method of the first embodiment according to the present invention.

9 is a sectional view showing an eighth step that you <br/> only to the manufacturing method of the first embodiment according to the present invention.

10 is a cross-sectional view showing a ninth step that put <br/> to the manufacturing method of the first embodiment according to the present invention.

11 is a sectional view showing a modification of the M IS transistors Ru shown in Figure 1.

FIG. 12 shows a manufacturing method of a second embodiment according to the present invention .
Therefore, it is a cross-sectional view showing the MIS type transistor manufactured.
is there.

FIG. 13 is a view showing a manufacturing method according to a second embodiment of the present invention .
It is sectional drawing which shows the characteristic 1st process.

FIG. 14 is a view showing a manufacturing method according to a second embodiment of the present invention .
It is sectional drawing which shows the characteristic 2nd process.

FIG. 15 is a view showing a manufacturing method according to a second embodiment of the present invention .
It is sectional drawing which shows the characteristic 3rd process.

FIG. 16 shows a manufacturing method of a second embodiment according to the present invention .
It is sectional drawing which shows a modification.

FIG. 17 shows a manufacturing method of a third embodiment according to the present invention .
It is sectional drawing which shows the characteristic 1st process in.

FIG. 18 shows a method for manufacturing a third embodiment according to the present invention .
It is sectional drawing which shows the characteristic 2nd process in.

FIG. 19 shows a manufacturing method according to a fourth embodiment of the present invention .
Therefore, it is a cross-sectional view showing the MIS type transistor manufactured.
is there.

FIG. 20 shows a manufacturing method of a fourth embodiment according to the present invention .
It is sectional drawing which shows the characteristic 1st process in.

FIG. 21 shows a manufacturing method according to a fourth embodiment of the present invention .
It is sectional drawing which shows the characteristic 2nd process in.

FIG. 22 shows a fourth embodiment of the manufacturing method according to the present invention .
It is sectional drawing which shows the characteristic 3rd process in.

FIG. 23 shows a manufacturing method according to a fourth embodiment of the present invention .
It is sectional drawing which shows the characteristic 4th process in.

FIG. 24 shows a manufacturing method of a fifth embodiment according to the present invention .
Therefore, it is a cross-sectional view showing the MIS type transistor manufactured.
is there.

FIG. 25 shows a manufacturing method of a fifth embodiment according to the present invention .
It is sectional drawing which shows a 1st process.

FIG. 26 shows a manufacturing method according to a fifth embodiment of the present invention .
It is sectional drawing which shows a 2nd process.

FIG. 27 shows a manufacturing method according to a fifth embodiment of the present invention .
It is sectional drawing which shows a 3rd process.

FIG. 28 shows a manufacturing method according to a fifth embodiment of the present invention .
It is sectional drawing which shows a 4th process.

FIG. 29 shows a manufacturing method of a fifth embodiment according to the present invention .
It is sectional drawing which shows a 5th process.

FIG. 30 shows a manufacturing method of a fifth embodiment according to the present invention .
It is sectional drawing which shows a 6th process.

FIG. 31 shows a manufacturing method of a fifth embodiment according to the present invention .
It is sectional drawing which shows a 7th process.

FIG. 32 shows a fifth embodiment of the manufacturing method according to the present invention .
It is sectional drawing which shows the 8th process.

FIG. 33 shows a manufacturing method according to a fifth embodiment of the present invention .
It is sectional drawing which shows a 9th process.

FIG. 34 shows a manufacturing method of a fifth embodiment according to the present invention .
It is sectional drawing which shows 10th process.

FIG. 35: MI in the sixth embodiment according to the present invention
It is sectional drawing which shows an S-type transistor.

FIG. 36 shows an MI in the sixth embodiment according to the present invention .
The characteristic first step of the manufacturing method of the S-type transistor is shown.
FIG.

FIG. 37 shows an MI in the sixth embodiment according to the present invention .
The characteristic second step of the manufacturing method of the S-type transistor is shown.
FIG.

FIG. 38 shows a seventh embodiment of the manufacturing method according to the present invention .
Therefore, it is a cross-sectional view showing the MIS type transistor manufactured.
is there.

FIG. 39 is a view showing a seventh embodiment of the manufacturing method according to the present invention .
It is sectional drawing which shows the characteristic 1st process.

FIG. 40 shows a seventh embodiment of the manufacturing method according to the present invention .
It is sectional drawing which shows the characteristic 2nd process.

FIG. 41 shows a seventh embodiment of a manufacturing method according to the present invention .
It is sectional drawing which shows the characteristic 3rd process.

FIG. 42 shows a seventh embodiment of manufacturing method according to the present invention .
It is sectional drawing which shows the characteristic 4th process.

FIG. 43 is a conventional example for improving the performance of a transistor .
It is sectional drawing which shows a method.

FIG. 44 is a conventional example for highly integrating transistors .
It is sectional drawing which shows a method.

[Explanation of symbols]

1 p-type semiconductor substrate 2 element isolation insulation layer 3,20,26 n-type impurity diffusion layer 4,21 First interlayer insulating layer 5,24 Gate electrode 6,22 Second interlayer insulating layer 7, 7a, 7b, 7c First opening 8,13,23,42 Insulation layer 9,11 n-type silicon epitaxial layer 10 p-type silicon epitaxial layer 12, 32, 35 Sidewall insulation layer 14,27 Embedded insulation layer 15,28 Wiring layer 16 Second opening

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-63-88860 (JP, A) JP-A-62-45058 (JP, A) JP-A-61-292371 (JP, A) JP-A-59- 218776 (JP, A) JP 55-148438 (JP, A) JP 6-77432 (JP, A) JP 5-259449 (JP, A) JP 3-280437 (JP, A) JP-A-3-274762 (JP, A) JP-A-2-100358 (JP, A) JP-A-2-94477 (JP, A) JP-A-2-26066 (JP, A) JP-A-1-298760 (JP, A) JP-A-1-241171 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/78 H01L 21/336 H01L 27/108

Claims (10)

(57) [Claims] 1. A semiconductor substrate of a first conductivity type having a main surface.
And a second conductivity type impurity formed on the main surface of the semiconductor substrate.
A substance diffusion layer and the impurity diffusion layer formed on the main surface of the semiconductor substrate.
First insulating layer having an opening reaching part of the surface of the layer
And a second conductivity type formed on a part of the surface of the impurity diffusion layer
First semiconductor layer and a second conductive type second layer formed on the upper surface of the first semiconductor layer.
A semiconductor layer, and a second conductive type third formed on the upper surface of the second semiconductor layer.
A semiconductor layer, and the semiconductor layer is provided inside the second semiconductor layer in the depth direction of the opening.
A hole penetrating the second semiconductor layer is provided, and a second insulating layer embedded in the hole and a third insulating layer at a position facing the side surface of the second semiconductor layer.
The semiconductor device further includes an intervening gate electrode and a conductive layer connected to the third semiconductor layer, and the hole includes the third semiconductor layer in the depth direction of the opening.
The second upper surface and a part of the side surface of the third semiconductor layer penetrate through the second insulating layer.
The conductive layer protrudes from an upper surface of the edge layer, and the conductive layer has an upper surface and a partial side surface of the third semiconductor layer.
A MIS transistor formed so as to cover the MIS transistor. 2. The second semiconductor layer comprises Si _1-x Ge _x (0
The MIS transistor according to claim 1, wherein ≦ x ≦ 1). 3. The MIS transistor according to claim 1 , wherein a metal silicide layer is formed on a surface of the impurity diffusion layer excluding a contact portion between the first semiconductor layer and the impurity diffusion layer. 4. A step of forming a second conductivity type impurity diffusion layer in a predetermined region of a main surface of a first conductivity type semiconductor substrate, and a first insulating layer on the surface of the impurity diffusion layer, and patterning into a predetermined shape. Sequentially forming the first conductive layer and the second insulating layer, and the impurity diffusion layer partially penetrating the first insulating layer, the first conductive layer and the second insulating layer Forming a first opening exposing a part of the surface of the first conductive layer, and forming a third insulating layer on the surface of the first conductive layer exposed in the first opening. A second conductivity type first semiconductor layer, a first conductivity type second semiconductor layer, and a second conductivity type second semiconductor layer on a part of the surface of the impurity diffusion layer.
A step of sequentially forming a conductive-type third semiconductor layer such that an upper surface of the third semiconductor layer is lower than an upper surface of the second insulating layer; and the first semiconductor layer located on the third semiconductor layer. Forming a first side wall insulating layer on the side wall of the opening of the first side wall insulating layer, and a second step of partially penetrating the second and third semiconductor layers using the first side wall insulating layer as a mask.
Forming an opening of the second insulating layer, forming a fourth insulating layer so as to fill the inside of the second opening and cover the second insulating layer, the fourth insulating layer and the first insulating layer. Exposing the upper surface of the third semiconductor layer and leaving the fourth insulating layer in the second opening by reducing the thickness of the sidewall insulating layer on the upper surface of the third semiconductor layer. And a step of forming a second conductive layer on the MIS transistor. 5. The step of forming the third insulating layer, the step of forming an oxide film on the surface of the first conductive layer by thermally oxidizing the inner surface of the first opening, and the step of forming the third insulating layer by the thermal oxidation. The step of removing an oxide film formed on the surface of the impurity diffusion layer, the M according to claim 4.
Method for manufacturing IS type transistor. 6. The step of forming the second conductive layer, the step of forming a fifth insulating layer so as to cover the third semiconductor layer, the fourth insulating layer and the second insulating layer, Forming a via hole in the fifth insulating layer located on the first opening and exposing the upper surface and a part of the side surface of the third semiconductor layer in the via hole; and exposing the via hole in the via hole. Forming the second conductive layer so as to cover the upper surface and a part of the side surface of the third semiconductor layer, the method for manufacturing the MIS transistor according to claim 4 . 7. A fifth insulating layer made of a material different from that of the fourth insulating layer is formed between the second insulating layer and the fourth insulating layer, and the first insulating layer, The step of forming the first conductive layer and the second insulating layer includes the step of forming the fifth insulating layer on the second insulating layer, and the step of forming the first opening includes the step of forming the first opening. No. 5, including the step of forming the first opening so as to partially penetrate the insulating layer as well, and the step of reducing the thickness of the fourth insulating layer and the first sidewall insulating layer includes: The step of exposing the surface of the fifth insulating layer by performing an etching process on the fourth insulating layer; and performing the etching process on the fourth insulating layer by using the fifth insulating layer as a mask, The top surface of the third semiconductor layer is exposed and the fourth opening is formed in the second opening. Comprising a step of residual insulating layer, a method for producing a MIS transistor according to claim 4. 8. A step of forming a first insulating layer patterned in a predetermined shape on a main surface of a semiconductor substrate of the first conductivity type, and a main surface of the semiconductor substrate using the first insulating layer as a mask. By subjecting the surface to anisotropic etching,
Forming a first groove, forming a first sidewall insulating layer on a side wall of the first groove, using the first insulating layer and the first sidewall insulating layer as a mask Anisotropically etching the bottom surface of the first groove to form a second groove connected to the first groove, and the first insulating layer and the first sidewall insulating layer. Forming a first impurity diffusion layer by introducing impurities of the second conductivity type into the surface of the second groove portion by using as a mask, and the second groove portion and the first sidewall insulating layer. A second insulating layer is formed so as to cover the second insulating layer, and the second insulating layer is etched back to remove the first sidewall insulating layer as well, and the second insulating layer is formed in the second groove portion. Leave layers A step of leaving it, a step of sequentially forming a third insulating layer and a first conductive layer on the surface of the side wall of the first groove, and a step of covering the second insulating layer and exposing the upper surface of the first insulating layer. Forming a fourth insulating layer, and removing the first insulating layer to form a third groove that selectively exposes the main surface of the semiconductor substrate. Forming a second impurity diffusion layer by introducing an impurity of the second conductivity type into the main surface of the semiconductor substrate; forming a second sidewall insulating layer on the side wall of the third groove; 2 side wall insulating layers and the fourth
Forming a fourth groove portion reaching the first impurity diffusion layer by etching the main surface of the semiconductor substrate using the insulating layer as a mask, and filling the inside of the fourth groove portion with the fourth groove portion. Forming a fifth insulating layer so as to cover the second sidewall insulating layer, and reducing the thicknesses of the fifth insulating layer and the second sidewall insulating layer so that the upper surface of the third semiconductor layer is formed. Manufacture of a MIS transistor including: exposing and leaving the fifth insulating layer in the fourth groove; and forming a second conductive layer on the upper surface of the third semiconductor layer. Method. 9. A step of forming a second conductivity type impurity diffusion layer in a predetermined region of a main surface of a first conductivity type semiconductor substrate, and a first insulating layer on the surface of the impurity diffusion layer, and patterning into a predetermined shape. Sequentially forming the first conductive layer and the second insulating layer, and the impurity diffusion layer partially penetrating the first insulating layer, the first conductive layer and the second insulating layer Forming a first opening that exposes a partial surface of the first opening, forming a third and a fourth insulating layer sequentially on the side wall surface of the first opening, and the third and the fourth Embedding a fifth insulating layer in the first opening surrounded by the insulating layer, and exposing a part of the surface of the impurity diffusion layer by removing the fourth insulating layer. A second conductive type first semiconductor layer on the exposed partial surface of the impurity diffusion layer, Second semiconductor layer of first conductivity type and second
And a step of forming a second conductive layer on the upper surface of the third semiconductor layer, and a method of manufacturing a MIS-type transistor. 10. A main surface of a semiconductor substrate of the first conductivity type.
Forming a second conductivity type impurity diffusion layer in a constant region, and forming a metal silicide layer on the surface of the impurity diffusion layer
A step of forming a first insulating layer on the metal silicide layer, and
Turn the first conductive layer and the second insulating layer in order
The step of forming next, the first insulating layer, the first conductive layer and the second
Partially penetrate the insulating layer and partially cover the surface of the impurity diffusion layer.
Forming a first opening to be exposed, and the surface of the first conductive layer exposed in the first opening
A step of forming a third insulating layer on the upper surface, and a second conductivity type on the exposed partial surface of the impurity diffusion layer.
First semiconductor layer, second semiconductor layer of first conductivity type and second
The upper surface of the third semiconductor layer is in front of the conductive third semiconductor layer.
Sequentially formed so as to be lower than the upper surface of the second insulating layer
And a sidewall of the first opening located on the third semiconductor layer
Forming a first sidewall insulating layer on the substrate, and using the first sidewall insulating layer as a mask
A second portion partially penetrating the second and third semiconductor layers
Forming an opening of the second insulating layer, filling the inside of the second opening and covering the second insulating layer.
Forming a fourth insulating layer, and the fourth insulating layer and the first sidewall insulation.
On the third semiconductor layer by reducing the layer thickness.
And exposing the surface and within the second opening, the fourth insulation.
And a step of forming a second conductive layer on the upper surface of the third semiconductor layer.
And a method of manufacturing a MIS transistor including: