JP3402112B2 - Active matrix type liquid crystal display device substrate, active matrix type liquid crystal display device using the same, and projection type display device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for adjusting a time constant of a signal wiring in an electronic circuit, for example, a peripheral drive circuit for driving a pixel electrode having a thin film transistor (hereinafter referred to as TFT) or a peripheral drive circuit. The present invention relates to an active matrix type liquid crystal display device provided or a projection type display device using the active matrix type liquid crystal display device.

[0002]

2. Description of the Related Art Conventionally, as an active matrix type liquid crystal display device, pixel electrodes are formed in a matrix on a glass substrate, and TFTs using amorphous silicon or polysilicon are formed corresponding to each pixel electrode. An active matrix liquid crystal display device having a structure in which a voltage is applied to each pixel electrode by a TFT to drive a liquid crystal has been put into practical use. Among them, an active matrix type liquid crystal display device using a polysilicon TFT is a TFT for sampling an image signal input from the outside and transmitting it to a data line, a shift register circuit for sequentially turning on and off the TFT, and the like. Since complementary TFTs (hereinafter referred to as CMOS type TFTs) that form the peripheral drive circuit can be integrated with the pixel driving TFTs on the same substrate in the same process, they have been widely used in recent years. It has become to.

Further, since the image signal supplied to the active matrix type liquid crystal display device is an analog signal, when the frequency band of the image signal becomes narrow, the sample hold circuit is turned on by the sampling signal to supply the image signal to the data line. In doing so, sampling may occur at a portion where the image signal is changing. In this case, since the image signal immediately before the sample-hold TFT constituting the sample-hold circuit is turned off is sampled, a high voltage is applied when the voltage of the image signal is changing, not the average voltage. Also, when the voltage of the image signal is changing in the decreasing direction, a lower voltage is sampled. Further, there is a problem that the sampling voltage changes even if the timing of the sampling signal is slightly deviated.

Therefore, for example, as shown in FIG. 14, an image signal is phase-developed into a plurality of sequences to expand the frequency band,
The image signal VID being sampled at the timing of each sampling signal X1, X2, ..., Xn.
Processing is performed so that the voltage levels of 1 to VID6 do not change (for example, processing is performed so that the average voltage of the image signal appears during the sampling period, as shown by the dotted ellipse in FIG. 14).
Then, there is a technique of supplying them to an active matrix type liquid crystal display device.

In the active matrix type liquid crystal display device configured to be driven by a plurality of phase-developed image signals as described above, generally, as shown in FIG. 15, input is made from input terminals T1 to T6. The plurality of image signals VID1 to VID6 formed externally include the image signal lines V1 to VID1.
It is transmitted to V6 and is supplied to the sample hold circuit 16 switched by the data line drive circuit 15 via the relay wirings H1 to H6.

[0006]

However, an image signal line V1 for supplying the image signals VID1 to VID6 from the input terminals T1 to T6 to the sample and hold circuit 16 is provided.
To V6 intersect the sampling signal lines X1, X2, ..., Xn output from the data line driving circuit 15, and therefore the same conductive film (for example, low resistance metal) from the input terminals T1 to T6 to the sample hold circuit 16 is used. Aluminum film, etc.). Therefore, conventionally, the image signals VID1 to VID6 are first made of aluminum films and are substantially parallel to each other and have substantially the same wiring width.
The signal is transmitted to the vicinity of the sample and hold circuit 16 by V6, and is transferred to the connection wirings H1 to H6 for relay made of another conductive film (for example, a polysilicon film or the like) that intersects through the insulating film, and then the sample and hold circuit. It was configured to be transmitted to 16 source electrodes (or drain electrodes). In this case, when the sample hold circuits 16 are arranged in a line as shown in FIG. 16 according to a general layout method, the wiring lengths (distances from the contact holes 45 to 46) L of the relay wirings H1 to H6 are different. Becomes In FIG. 16, the sampling signal line X1,
, Xn are formed of a polysilicon film or the like made of the same material as the relay wirings H1 to H6.

However, if the relay wirings H1 to H6 are made of a polysilicon film, the polysilicon film has a resistivity higher than that of the aluminum film by two digits or more. When the width W and the wiring film thickness are formed to be substantially constant, the wiring length L is different for each of the relay wirings H1 to H6, and thus the resistance between the relay wirings H1 to H6 is different.
In other words, the image signal sampled by the sample hold circuit 16 has a different time constant for each of VID1 to VID6, and this causes the display unevenness of the active matrix liquid crystal display device. Therefore, the line width W is changed for each of the relay wirings H1 to H6 (from the image signal lines V1 to V6 to the sample hold circuit 16).
If the distance is short, the line width W of the relay wirings H1 to H6 is made thin, and if the distance is long, the line width W is made thick) to make the resistance constant. However, the method of changing the width of the wiring to keep the resistance constant (see FIG.
In 6), the overlapping capacitance with other image signal lines cannot be made constant, and when the wiring width changes due to process variations, the change in resistance value with respect to the wiring width variations differs depending on the wiring width W. It has been clarified that the narrower the wiring width W is, the more significantly it is affected by the process variation, and thus the problem that the variation of the time constant becomes large occurs.

It is an object of the present invention that even if the wiring width W of a relay wiring for transmitting a signal from a plurality of signal wirings to a drive circuit varies, the resistance value and the capacitance value have a small variation. The constant can be made almost uniform. Accordingly, it is an object of the present invention to provide an active matrix type liquid crystal display device capable of suppressing display unevenness of the active matrix type liquid crystal display device and performing high quality display.

[0009]

In order to achieve the above object, the present invention corresponds to a plurality of signal wirings on a substrate and each of the plurality of signal wirings formed on the signal wirings via an insulating film. The relay wiring having a resistance higher than that of the signal wiring and the auxiliary wiring connected to the relay wiring and the transistor and having a resistance lower than that of the relay wiring. The wiring for wiring has a wiring width, a length and a film thickness which are substantially equal to those of other relay wiring connected to other signal wiring, and the plurality of auxiliary relay wirings are auxiliary relay wirings of different lengths. Is characterized by. As a result, the resistance value of the relay wiring becomes substantially uniform. Therefore, by wiring the plurality of signal wirings substantially in parallel with each other in a region intersecting with the relay wirings and making the wiring widths substantially equal to each other, the overlapping capacitance with other signal wirings becomes substantially uniform, and a signal to be transmitted is transmitted. The time constants for are almost equal among the signal wiring paths. Furthermore, since the length, width, and film thickness of the relay wiring are almost the same, even if the wiring width deviates from the target value due to process variations, the variation in resistance value and capacitance value between the signal wiring paths becomes almost constant, and the time constant There is an advantage that it is possible to suppress the display unevenness of the active matrix type liquid crystal display device due to the variation of

Further, the signal wiring to which the present invention is applied is not only an image signal line for transmitting a phase expanded image signal, but also a clock signal line for transmitting a clock signal input from the outside to the shift register circuit. Alternatively, it can be applied to an image auxiliary input signal line for transmitting an image auxiliary input signal for assisting the image signal.

Further, there is an advantage that it is not necessary to increase the number of steps because the relay wiring can be formed by the same process and the same material as the data line by the scanning line and the auxiliary relay wiring.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) FIG. 1 shows a structural example of a substrate for an active matrix type liquid crystal display device of an active matrix type liquid crystal display device to which the present invention is applied. In FIG. 1, 10 is a substrate such as one glass substrate or quartz substrate that constitutes an active matrix type liquid crystal display device, 11 and 12 are scanning lines and data lines arranged in directions intersecting with each other, and 13 is the scanning line. In each pixel connected to the data line 11 and the data line 12, each pixel 13 includes a pixel electrode made of ITO or the like and a TFT for sequentially applying a voltage according to an image signal to the pixel electrode. The gate electrodes of the TFTs in the same row are connected to the same scanning line 11, and the drain electrodes are connected to the corresponding pixel electrodes. The source electrodes of the TFTs in the same column are connected to the same data line 12. In this embodiment, the TFT for driving the pixel is composed of a so-called polysilicon TFT having a polysilicon film as a channel layer, and a peripheral drive circuit (data line drive circuit 15 or scanning line drive circuits 14A, 14B, etc.) is formed. It is formed on the same substrate by the same process as the constituent CMOS type TFTs.

In this embodiment, the scanning line driving circuits 14A and 1A including Y shift register circuits and buffer circuits for sequentially selectively driving the scanning lines 11 at both ends of the scanning line 11 are provided.
4B is provided. Scan line drive circuits 14A and 14B
Applies the same voltage to each scanning line 11 at the same timing. That is, one scanning line 11 is simultaneously driven from both sides thereof. As a result, it is possible to reduce voltage drop and signal delay due to the parasitic resistance of the scanning line 11.

On the other hand, in this embodiment, a data line drive circuit 15 including an X shift register circuit and a buffer circuit for selectively driving the data line 12 is provided. Further, a circuit 16 for sampling the image signal is provided at both ends of the data line 12,
17 are provided. Of these, 17 are each data line 12
Is a pre-charge circuit for applying a pre-charge level, and the other 16 is a sample hold circuit for applying a voltage according to an image signal to each data line 12. The sample hold circuit 16 and the precharge circuit 17 belong to one of the three types shown in FIG. 20 when shown in a basic equivalent circuit diagram. That is, the sample-hold TFT 160
20A and 20B. The precharge TFT 170 includes an N-channel TFT, a (B) P-channel TFT, and a (C) C shown in FIG.
It takes either form of a MOS type TFT. In FIG. 20, the sampling signal SB of the P-channel TFT is an inverted signal of the sampling signal S with respect to the sampling signal S of the N-channel TFT. Image auxiliary input signals NRS1 and NRS2 supplied from the outside are applied to the source (the electrode on the side opposite to the connection electrode on the data line 12 side) of the precharge circuit 17 every other line on the data line 12, and the image auxiliary is supplied. The timing signal NRG supplied from the outside is commonly applied to the gate electrode of the precharge circuit 17 via the signal wiring 18 while being supplied to the precharge circuit 17 by the input signal lines 19A and 19B. This allows all data lines 1
2 is the image auxiliary input signal NRS before the image signal level is applied from the sample hold circuit 16 in one horizontal blanking period.
1 and NRS2 levels are simultaneously precharged. Further, when driving is performed to change the polarity of the image signal for each adjacent data line 12, the image auxiliary input signal NRS is used.
1 and NRS2 are effective when they have opposite polarities.

To the source electrode of the sample hold circuit 16 provided at the other end of each data line 12, the phase expanded image signals VID1 to VID6 supplied from the outside are input via the image signal line group 20. Sample and hold circuit 1
A sampling signal output from a data line driving circuit 15 including a shift register circuit and a buffer circuit for sequentially selecting the data lines 12 is applied to the gate electrode of 6. In the present embodiment, the image signal is expanded into 6 phases, but the number of phase expansions can be reduced if the writing characteristics of the sample-hold TFT 160 is high, and the number of phase expansions can be increased if the writing characteristics are low. Is also good. Also, NTSC signal and PA
It goes without saying that an RGB parallel signal corresponding to the L signal may be used. The data line drive circuit 15 has a start signal SPX and eight clock signals CLX supplied from the outside.
1 to 4 and CLXB1 to 4 are used to form sampling signals X1, X2, X3, ... Xn for sequentially selecting all the data lines 12 once in one horizontal scanning period. Supply to 16 gate electrodes. The clock signals CLX1 to CLX4 (or the opposite phase clock signals CLXB1 to CLX4) are clock signals of the same cycle, whose phases are sequentially shifted by 45 °. By the way, the anti-phase clock signals CLXB1 to 4 can be generated inside the active matrix type liquid crystal display device substrate by the signal generation circuit provided in the peripheral drive circuit based on the clock signals CLX1 to 4 input from the outside. Is.

Although not particularly limited, in this embodiment, as shown in FIG. 8, the data line drive circuit 15 is composed of four shift register circuits, and the shift register circuits of each system are reverse to each other. It is operated by a pair of phase clock signals CLXi, CLXBi and is configured to provide a timing signal for selecting a signal wiring every four lines. Since there are eight clock signals in this way, clock signals CLX1 to CLX4, C input from the outside are provided.
The drive frequency of each of the LXBs 1 to 4 can be reduced, and the load on the peripheral drive circuit of the active matrix liquid crystal display device is reduced.

In this embodiment, the method of sequentially driving the data lines 12 line by line at a fixed timing has been described, but a large number of adjacent data lines 12 such as 3 lines, 6 lines and 12 lines are formed. This embodiment can also be used by a method of simultaneously selecting with one data sampling signal and changing the timing of the image signal input from the outside.

Further, in the present embodiment, the data line driving circuit 15
And peripheral drive circuits including the scan line drive circuits 14A and 14B, a plurality of data lines 12 connected to the data line drive circuit 15, and the scan lines 11 connected to the scan line drive circuits 14A and 14B intersect in a matrix. The active matrix type liquid crystal display device in which the pixel transistor connected to the data line 12 and the scanning line 11 and the pixel electrode connected to the pixel transistor are formed on the same substrate has been described. Is formed by a high temperature polysilicon TFT on an expensive substrate such as a quartz substrate, and a region 130 including the data line 12, the scanning line 11 and the pixel 13 is formed.
A substrate for an active matrix type liquid crystal display device (indicated by a dotted line in FIG. 1) is formed by an amorphous silicon TFT or a low temperature polysilicon TFT having a process temperature of 600 ° C. or less on an inexpensive substrate such as a glass substrate and connecting these substrates. Can also be configured.

FIG. 2 shows an embodiment in which the present invention is applied to a connecting portion between the image signal line group 20 and the sample hold circuit 16. V1 to V6 are inputted from external input terminals and the phase expansion is carried out. Image signal lines as signal lines for transmitting the generated image signals VID1 to VID6. These image signal lines V1 to V6 are formed of a low resistance aluminum film made of the same material as the data line 12, although not particularly limited thereto. . , Xn are wirings for supplying the sampling signal output from the data line drive circuit 15 to the gate electrode of the sample hold circuit 16, and the sampling signal lines X1, X2, ..., Xn are the wirings. Arranged in a direction intersecting with the image signal lines V1 to V6,
It is made of a polysilicon film made of the same material as the scanning line, and is formed so as to be continuous with the gate electrode of the sample hold circuit 16.

Reference numerals 41 and 42 respectively denote source / drain regions of a sample-hold TFT 160 which constitutes a sample-hold circuit 16 made of a polysilicon film provided on both sides of the sampling signal lines X1, X2, ..., Xn. Source region 41 of hold TFT 160
In the contact holes 43, lead lines S1 to S6 as auxiliary relay wirings made of a low-resistance aluminum film or the like are provided.
It is connected with. In addition, each sample hold circuit 1
The data line 12 connected to the pixel driving TFT is connected to the drain region 42 of No. 6 through a contact hole 44. In this embodiment, although not particularly limited, the data line 12, the auxiliary relay wirings S1 to S6, and the image signal lines V1 to V6 are made of an aluminum film formed in the same process.

Further, in this embodiment, the image signal line V
1 and the auxiliary relay wiring S1 in a direction intersecting with the image signal lines V1 to V6 in a different layer from the image signal lines V2 to V6 via an interlayer insulating film and in the same layer as the scanning line 11. A relay wiring H1 made of a conductive film such as a polysilicon film is provided. The relay wiring H1 has the image signal line V at the wiring end.
1 is the contact hole 45, and the auxiliary relay wiring S1
And are connected to each other through contact holes 46. Similarly, the other image signal lines V2 to V6 and the image signal line V
The auxiliary wirings S2 to S6 corresponding to 2 to V6 are also connected to the relay wirings H2 to H6 in the contact holes 45 and 46, respectively. The image signals VID1 to VID6 are transmitted via the relay wirings H1 to H6 to the source electrode of the sample and hold TFT 160 that constitutes the sample and hold circuit 16. The relay wirings H1 to H6 are designed so that the line width W and the length (distance from the contact holes 45 to 46) L and the wiring film thickness are all substantially equal, and the relay wiring H1 is also used. About the signal path between ~ H6 and the sample hold circuit 16, the difference in length is absorbed by extending the auxiliary relay wirings S1 to S6. In addition, the image signal line V
1 to V6 are wired at least substantially in parallel with each other in a region intersecting with the relay wirings H1 to H6, and the image signal lines V1
The line widths of ~ V6 are designed to be substantially equal to each other.

When the relay wirings H1 to H6 are made of a polysilicon film which forms the gate electrode of the TFT and the auxiliary relay wirings S1 to S6 are made of an aluminum film, the resistivity of the aluminum film is higher than that of the aluminum film. Since it is smaller by about two digits than the silicon film, the difference in resistance value due to the difference in length of the auxiliary relay wirings S1 to S6 can be extremely small. In addition, since the overlapping areas with other image signal lines become equal, the overlapping capacitance becomes uniform, and the capacitance of each image signal line becomes uniform. Therefore, the time constant for the image signal to be transmitted becomes equal between the signal paths, and the image signal line V1
To V6 have almost the same line width, and the relay wirings H1 to H
Since the line widths W between 6 are also almost equal to each other, even if the line width deviates from the design target value due to process variations, the variations in the capacitance value and the resistance value between the image signals are almost the same, and the variation in the time constant is accompanied. Display unevenness can be suppressed.

The length L of the relay wirings H1 to H6
Is most efficiently set within the line width L1 + 30 μm of the signal wiring group 20 (image signal lines V1 to V6).
Since the length L of the relay wirings H1 to H6 having a high resistance value is the shortest to reduce the wiring resistance and the occupation area is small, it is possible to perform efficient design in which the peripheral drive circuit area can be finely integrated.

In the present embodiment, the data line 12 and the auxiliary relay wirings S1 to S6 and the image signal lines V1 to V6 are made of an aluminum film formed in the same process. However, a metal film of Cr, Ta or the like is used. It is also possible to use different conductive films such as a metal silicide film. Moreover, not only the polysilicon films but also Mo,
If a metal film of Ta, W, Cr or the like or a metal silicide film of Mo-Si, W-Si or the like is used, the resistance can be reduced, and the effect of making the time constant between the wirings even more effective.

FIG. 3 shows a modification of the first embodiment. In this modified example, the contact holes 43 to the source region 41 and the contact holes 44 to the drain region 42 of the sample and hold TFT 160 constituting the sample and hold circuit 16 are alternately arranged, and the sampling signal wirings X1 and X2, , Xn, the gate electrode portion of the sample-hold TFT 160 is meandered so as to avoid the contact holes 43 and 44. If the opening of the contact hole is too small, the contact resistance is high and the size of the contact hole is limited, and it cannot be larger than the minimum width of the connection wiring. Therefore, it is possible to reduce the pitch L2 of the adjacent sample and hold circuits 16 by forming the gate electrode of the sample and hold TFT 160 in a meandering pattern as described above, and when the pixel pitch becomes small due to high integration. The sample hold circuit 16 can be formed accordingly.

FIG. 4 shows another modification of the first embodiment. In this modification, the area occupied by the sample hold circuit 16 can be reduced. That is, the end portions of the sampling signal wirings X1, X2, ..., Xn for controlling the gate electrode of the sample-hold TFT 160 are bifurcated, and the drain region 42 is bifurcated outside thereof.
Is connected to the data line 12. Since the pitch L3 of the adjacent data lines 12 is determined depending on the pitch per pixel which is not shown and is arranged, the pitch L3 of the adjacent data lines 12 constitutes the sample hold circuit 16 which constitutes one sample hold circuit 16. For TF
When the width is larger than the width of the source / drain region of T160, the sample-hold TFT 160 is formed with transistors on both sides of the source region 41 as shown in FIG. As a result, the lateral pitch L3 of the sample-hold circuit 16 can be effectively used to reduce the wasted space and the occupied area as a whole. Further, compared with the sampling signal wirings X1, X2, ..., Xn in FIG. 2, when the channel width L4 of the sample-hold TFT 160 is designed to have the same length, a drain current characteristic of about twice is obtained. Needless to say, the source region 41 may be bifurcated and the drain region 42 may be single.

FIG. 5 shows still another modification of the first embodiment. In this modification, the distances from the image signal lines V1 to V6 to the sample and hold circuit 16 are substantially equal to each other, so that the length L4 of the auxiliary relay wirings S1 to S6 is the same as the relay wirings H1 to H6. They are designed to be almost the same as each other. With this configuration, it is possible to further reduce the variation in the time constant for each image signal. In FIG. 5, the sample-hold circuit 16 is shown to have a bifurcated gate electrode, but it is also possible to form a single gate electrode as in FIG.

Further, in the embodiment shown in FIGS. 2 to 5, the sample and hold TFT constituted by the one channel type TFT.
Although 160 is shown, the sample-hold TFT 160
Needless to say, may be an N-channel TFT (FIG. 20A) or a P-channel TFT (FIG. 20B).

FIG. 6 shows another modification of the above embodiment. This modification is similar to the sample hold TFT 1 described above.
60 is a CMOS TFT (P-channel TFT 42P and N-channel TFT 42N are provided in parallel.
It is formed in C). P-channel TFT 42P
And to turn on the N-channel TFT 42N at the same time,
It is necessary to simultaneously apply a sampling signal having a phase opposite to that of the sampling signal transmitted to the gate electrode of the P-channel TFT 42P to the gate electrode of the N-channel TFT 42N. Therefore, sampling signal wirings X1, X2, ..., Xn including gate electrodes connected to the data line driving circuit 15 are provided.
Is systematized into two systems, and the P-channel TFT 42P has a gate electrode for the P-channel TFT sampling signal wiring X1.
, Pn, X2P, ..., XnP are also N-channel type TFT4
The sampling signal wirings X1N, X2N, ..., XnN for N-channel TFTs are connected to the relay wiring H on the 2N gate electrode.
1 to H6 and auxiliary relay wirings S1 to S6 are sandwiched and arranged substantially parallel to each other. With this configuration, it is possible to prevent the image signal from being lowered in level by the threshold value of the TFT. Further, the push-down of the sample-hold TFT 160 can be suppressed.

In the above embodiments, the image signal lines V1 to V1 for transmitting the phase expanded image signals VID1 to VID6.
The case where the present invention is applied to the portion for transmitting from V6 to the sample hold circuit 16 has been described, but the signal transmission line to which the present invention is applied is not only the image signal line for transmitting the image signal but also the precharge level for each data line 12. It can also be applied to the precharge circuit 17 for applying the voltage and the transmission portion between the clock signal wiring for transmitting the clock signal input from the outside to the shift register circuit and the shift register circuit.

(Embodiment 2) Next, a preferred embodiment 2 to which the present invention is applied will be described. FIG. 7 shows image auxiliary input signal lines 19A and 19B for supplying image auxiliary input signals NRS1 and NRS2 (see FIG. 1) from the outside to the precharge circuit 17 for applying a precharge level to each signal line 12 and the precharge circuit 17. An example in which the present invention is applied between and. In this embodiment, the image auxiliary input signal NRS
1, image auxiliary input signal line 19A for supplying NRS2, 1
Although not particularly limited, 9B is made of a metal film such as an aluminum film having a low resistance, and is wired substantially in parallel with each other, and the line widths thereof are substantially equal to each other, and are formed wide to reduce the wiring resistance. Also, these image auxiliary input signal lines 19A, 1
The relay wirings H1 and H2, which are alternately connected to 9B, are formed in the contact hole 49B formed at the edge portion on the side closer to the precharge TFT 170 with respect to the image auxiliary input signal line 19B on the side farther from the precharge TFT 170. And the image auxiliary input signal line 19A on the side closer to the precharge TFT 170 is connected to each other through a contact hole 49A formed at an edge portion on the side far from the TFT 15A, thereby having the same length, that is, the same. Is configured to have a time constant of. As a result, the wiring lengths of the relay wirings H1 and H2 (from the contact holes 49A to 5
By setting the distance to 0A or the distance L from the contact holes 49B to 50B) L, the width W, and the film thickness to be substantially constant, the wiring resistance and the overlapping capacitance can be made substantially uniform. That is, the time constant can be made uniform. In addition, the image auxiliary input signal lines 19A and 19B
When contact holes 49A and 49B are formed to connect the relay wirings H1 and H2 to each other as shown in FIG.
Since the length of the wiring region L6 can be designed to be the minimum, it is possible to omit a useless region and perform efficient design. Although not particularly limited, it is an effective means for drawing out the relay wiring from two signal lines whose signal polarities are exactly opposite.

Incidentally, also in this embodiment, the relay wiring H
1 and H2 are formed of the same polysilicon film as the polysilicon wiring 180 extending from the gate electrode of the precharge TFT 170 and transmitting the signal NRG for controlling the gate electrode, and the other ends of the relay wirings H1 and H2 are made of aluminum. Source region (or drain region) of the precharging TFT 170 via the auxiliary relay wirings S1 and S2 made of a film
Connected to. As the precharge TFT 170, a one-channel TFT (N-channel TFT or P-channel TFT; see FIG. 20) in which a gate electrode is formed straight is shown, but the pre-charge TFT 170 is not limited to this, and the gate electrode may be used. Bifurcated or CMOS type TFT
The one shown in FIG. 20C may be used. When a CMOS type TFT is used as the precharge TFT 170, at least two precharge circuit drive signal lines are required because the precharge circuit drive signal NRG and its inverted signal are required. It goes without saying that the relay wiring of the present invention can also be applied to this case. Also,
The polysilicon wiring 180 is connected to the precharge circuit drive signal line 18 made of an aluminum film, and a common signal NRG is applied.

(Third Embodiment) FIG. 8 shows an X shift register circuit 150 which constitutes the data line drive circuit 15 in FIG.
The relationship between the signal lines for transmitting the clock signals CLX1 to 4 and the negative phase clock signals CLXB1 to 4 is shown.

In this embodiment, an example in which the X shift register circuit 150 formed in the data line driving circuit is composed of the clocked inverters 200 and 201 is shown, but a transmission gate or the like may be used. Clock signal CL
X1 to CLX4 are divided into four systems and clock signal CL
Reverse phase clock signals CLXB1 to CLX of X1 to CLX4
Any of the eight-phase clock signals whose phases are shifted from each other by 45 ° in combination with B4 passes through the relay wirings 91 to 98,
It is driven by being transmitted to the gate electrode of the clocked inverter of the X shift register circuit 150. Therefore, the clock signal lines CLX1 to CLX4, CLXB1 to
In the configuration from CLXB4 to the relay wirings 91 to 98, the relay wirings H1 to H1 used in the signal path from the image signal lines V1 to V6 shown in FIG.
The same configuration as H6 and auxiliary relay wirings S1 to S6 is applied. That is, by connecting the clock signal line and the X shift register circuit 150, there is no time constant difference between the clock signal series of the X shift register circuit 150, and it is possible to suppress display unevenness in the active matrix liquid crystal display device. Become.

In the present embodiment, not only the X shift register circuit 150 but also the scanning line drive circuit 14 in FIG.
It goes without saying that the present invention can also be applied to the Y shift register circuit forming A and 14B. That is, the clock signal C
If the relay wiring and the auxiliary relay wiring of the present invention are used for the relay wiring between the clock signal line for transmitting LY and the negative phase clock signal CLYB and the Y shift register circuit, Y
Every other row scanning line 11 caused by a delay difference between the clock signal CLY and the anti-phase clock signal in the shift register circuit.
It is possible to provide a high-quality active matrix type liquid crystal display device by suppressing the delay difference of the above.

(Embodiment 4) Still another embodiment of the present invention is shown in FIG. This is, for example, the signal N1, which is sequentially transmitted from the shift register circuit and transmitted to the odd-numbered stages.
N3, N5, ... Are connected to one terminal of the two-terminal NAND circuit 202, and the enable signal ENB1 input from the outside is connected to the other terminal. Similarly, the signals N2, N4, N6, ...
It is connected to one terminal of the circuit 203 and the enable signal ENB2 input from the outside is connected to the other terminal.
With such a circuit configuration, as shown in the timing chart of FIG. 19, sampling signals X1, X2, ..., Xn may be overlapped (A) or separated (B) between adjacent sample signal lines. You can do it freely. Therefore, the enable signal line EN in the fourth embodiment
The relay wiring 81 relay-connected to the NAND circuit 202 from B1 and the relay wiring 82 relay-connected to the NAND circuit 203 from the enable signal line ENB2 include the image signal lines V1 to V6 and the sample hold circuit shown in FIG. TFT
Relay wirings H1 to H6 used for connecting to 160
The relationship between the auxiliary relay wirings S1 to S6 may be applied. This eliminates the signal delay difference between the enable signals ENB1 and ENB2 in the active matrix type liquid crystal display device substrate, so that a high quality active matrix type liquid crystal display device can be provided.

Further, these enable signals ENB1,
The circuit controlled by ENB2 is a 2-terminal NAND circuit 2
In addition to 02 and 203, a NAND circuit having three or more terminals may be combined with a plurality of enable signals and control signals generated in the peripheral drive circuit to form a complicated circuit configuration. Furthermore, a NOR circuit or the like may be used instead of the NAND circuit.

The present invention can be applied to all cases when a drive circuit having at least two signal wirings and controlled by a signal transmitted to the signal wirings is formed.

(Description of Manufacturing Process) FIGS. 9 to 11 show the manufacturing process of the pixel 13 and the image signal line portion in the order of steps. The pixel TFT portion of FIGS. 9 to 11 is a sectional view taken along the line AA ′ of the pixel plan view shown in FIG. 17, and the image signal line portion is a sectional view taken along the line BB ′ of the plan view of FIG. Indicates.

First, in step (1), a polysilicon film is formed on a substrate 10 such as a glass substrate or a quartz substrate by a low pressure CVD method or the like to a thickness of 500 to 2000 angstroms, preferably about 1000 angstroms. The semiconductor layer 1 is formed by depositing. The semiconductor layer 1 is formed by depositing an amorphous silicon film, and then 600 to 7
A polysilicon film may be formed by performing annealing treatment at 00 ° C. for 1 to 8 hours, or after depositing the polysilicon film, silicon is implanted to make it amorphous and then recrystallized by annealing treatment to form a polysilicon film. A silicon film may be formed.

In the step (2), the semiconductor layer 1 is patterned by a photolithography process, an etching process, etc., and the layer 1 including the island-shaped channel is formed in the pixel TFT portion.
a is formed.

In the step (3), the surface of the polysilicon film (1a) of the pixel TFT section formed in the step (2) is thermally oxidized at a temperature of 900 to 1300 ° C., so that the channel layer 1a is formed. A gate oxide film 2 is formed. In addition, in order to prevent the warpage of the substrate and the like, a multi-layer gate insulating film may be formed by forming a thermal oxide film of 200 to 500 angstrom and then forming an HTO film or a SiN film. By this step, the layer 1a containing the channel finally has a thickness of 300 to 1500 angstrom, preferably 350.
The thickness is about 450 angstroms, and the gate insulating film 2 is about 600 to 1500 angstroms.

In the step (4), a low resistance polysilicon film 3 to be a gate electrode and a scanning line is formed on the gate insulating film 2 of the pixel TFT section formed in the step (3) by the low pressure CVD method. And so on.

In step (5), the polysilicon film 3 formed in step (4) is patterned by a photolithography process and an etching process to form a gate electrode (scanning line) 11 in the pixel TFT section. At the same time, in the image signal line portion, the relay wiring H1 is formed of the same material as the gate electrode 11. Gate electrode 11 and relay wiring H1
As the material of, other than polysilicon, Mo, Ta, T
Refractory metals such as i and W or metal silicides thereof can be used.

In the step (6), an impurity (phosphorus) is added to the channel layer 1 by using the gate electrode 11 as a mask.
The low concentration regions 1d and 1e are formed by light doping at a dose amount of × 10 ¹³ / cm ^{2 to} 3 × 10 ¹³ / cm ² . Further, a resist film 100 is formed on the gate electrode with a mask layer wider than the width of the gate electrode 11, and impurities (phosphorus) 101 are added at 1 × 10 ¹⁵ / cm ^{2 to} 3 × 10 ¹⁵ / c.
Implanting with a dose amount of m ² forms an N-channel TFT. Similarly, when forming a P-channel TFT, although not shown, the N-channel TFT region is covered and protected with a resist, and then impurities (boron) are added in an amount of 1 × 10 ^13.
/ Cm ^{2 to} 3 × 10 ¹³ / cm ² is lightly doped to form the low concentration regions 1d and 1e. further,
A mask layer wider than the width of the gate electrode 3a is formed on the gate electrode 3
Impurities (boron) are formed on the surface of a to form 1 × 10 ¹⁵ / c
Implanting with a dose amount of m ^{2 to} 3 × 10 ¹⁵ / cm ² ,
A P-channel type TFT is formed. As a result, the masked region has a lightly doped drain (LDD) structure, and a CMOS TFT composed of an N-channel TFT and a P-channel TFT is formed. Alternatively, the regions 1d and 1e may be offset without lightly doping the impurities. Further, although the pixel TFT is formed of the N-channel type TFT in this embodiment, it goes without saying that it may be formed of the P-channel type TFT.

In the step (7), a first NSG film (silicate glass film containing no boron or phosphorus) or the like is formed so as to cover the gate electrode 11 and the relay wiring H1.
Of the inter-layer insulating film 4 of 800 by, for example, the atmospheric pressure CVD method or the like.
Deposition to a thickness such as 5000 to 15000 Angstroms at a temperature such as degrees. (FIG. 10) In the process of (8), the contact holes 5 are opened at the positions corresponding to the source regions in the pixel TFT portion by dry etching or the like in the first interlayer insulating film 4, and relayed at the image signal line portion. Contact holes 45 and 46 for connecting to the wiring H1 are opened. As a method of opening the contact holes 5, 45, and 46, it is advantageous to increase the definition of pixels by opening an anisotropic contact hole by dry etching such as reactive ion etching or reactive ion beam etching. is there. Further, when the dry etching and the wet etching are combined to form the opening portion in a tapered shape, it is effective in preventing disconnection at the time of wiring connection.

In the step (9), the low-resistance conductive film 6 is deposited by sputtering on the substrate as a metal film such as aluminum or aluminum alloy or a metal silicide film. In the pixel TFT section, the low resistance conductive film 6 is used as the contact hole 5
Is connected to the source region 1b via the contact line H1 and is connected to the relay wiring H1 via the contact holes 45 and 46 in the image signal line portion.

In step (10), the low resistance conductive film 6 is patterned by a photolithography process and an etching process to form a data line 12 which also serves as a source electrode so as to be connected to the source region 1b, and is used for relaying. Wiring H1
The image signal line V1 and the auxiliary relay wiring 51 connected to the above are formed. At this time, other image signal wirings V2 to V6 are simultaneously formed.

In the step (11), a second BPSG film (silicate glass film containing boron and phosphorus) is formed so as to cover the data lines 12, the image signal lines V1 to V6 and the auxiliary relay wiring 51. The interlayer insulating film 7 is formed by a plasma ozone TEOS method, a normal pressure ozone TEOS method or the like at a low temperature such as 500 degrees to a thickness of 5000 to 15000 angstroms. Alternatively, a flattening film having no step shape may be formed by applying an organic film or the like by spin coating. (FIG. 11) In the step (12), a photolithography process and an etching process are performed on the second interlayer insulating film 7 and the superposed film formed of the first interlayer insulating film 4 and the gate insulating film 2 thereunder. ,
The contact hole 8 is formed at a position corresponding to the drain region of the pixel TFT section. As a method of opening the contact hole 8, it is advantageous to make the pixel fine by opening an anisotropic contact hole by dry etching such as reactive ion etching or reactive ion beam etching. Further, when the dry etching and the wet etching are combined to form the opening portion in a tapered shape, it is effective in preventing disconnection at the time of wiring connection.

In the step (13), IT which becomes the pixel electrode 9a is formed on the second interlayer insulating film 7 in the pixel TFT section.
The O film 9 is formed by the sputtering method to have a thickness of 1500 angstrom, for example. At this time, in the TFT section, I
The TO film 9 is connected to the high concentration drain region 1c through the contact hole 8.

In the step (14), the pixel electrode 9a is formed on the ITO film 9 in the pixel TFT section by a photolithography process and an etching process.

An alignment film made of polyimide or the like is formed on the pixel electrode 9 and the second interlayer insulating film 7 in an amount of about 2.
A substrate for an active matrix type liquid crystal display device is obtained by forming the film with a thickness of 00 to 1000 angstroms and performing rubbing (alignment treatment). In the case of a reflection type active matrix type liquid crystal display device, a film having a high reflectance such as aluminum may be formed as the pixel electrode 9a.

Although not particularly limited, in this embodiment, as shown in FIG. 17, the drain region 1 of the pixel TFT is formed.
drain region 1c in order to add a capacitance attributed to c
And the capacitance line 3a to which a constant potential is constantly supplied via the gate insulating film 2 is arranged on the upper part of the capacitor line 3a. The capacitance line 3
a is formed of the same material and in the same process as the scanning line 11. Further, since the disclination generation portion of the liquid crystal which is conventionally affected by the lateral electric field of the pixel electrode 9a or the like causes deterioration of screen display quality, the dead space shielded by the black matrix on the counter substrate is used. However, the capacitance line 3 is present in the disclination generation area.
By disposing a, it is possible to provide a high-quality active matrix liquid crystal display device in which flicker or the like does not occur without deteriorating the aperture area through which the light of the pixel passes.

As described above, the relay wirings H1 to H6 made of the polysilicon film in the embodiments of FIGS. 2 to 8 are the polysilicon film 1 to be the gate electrode in the TFT section.
It is formed at the same time as 1. Further, the image signal lines V1 to V6 made of an aluminum film, the image auxiliary input signal lines 19A and 19B, and the clock signal line CL in the embodiment of FIGS.
X1 to CLX4, CLXB1 to CLXB4 and auxiliary relay wirings S1 to S6 are the data lines 1 in the TFT section.
It is formed simultaneously with the aluminum film to be 2. Needless to say, other signal wirings and respective relay wirings and auxiliary relay wirings can be formed in the same process. Thereby, the embodiments of FIGS. 2 to 8 can be realized without changing the process.

(Description of Active Matrix Liquid Crystal Display Device) FIG. 12A is a plan view of the active matrix liquid crystal display device manufactured in this embodiment. FIG. 12 (B)
FIG. 7A is a sectional view of the active matrix type liquid crystal display device taken along line YY ′ in FIG. As shown in FIG. 15, the substrate 1 for the active matrix type liquid crystal display device.
0 data line driving circuit 15 and scanning line driving circuit 14
A and 14B are arranged outside the outer periphery of the counter substrate 110 in order to prevent deterioration of the alignment film such as polyimide or the liquid crystal due to the direct current component of the charge. On the surface of the pixel electrode formed on the substrate for active matrix type liquid crystal display device, a transparent counter electrode potential can be applied on a transparent substrate such as glass, neocerum or quartz.
A counter substrate 110 having electrodes 111 made of a transparent conductive film such as a TO film is arranged at an appropriate interval, and as shown in FIG. 7, the data line driving circuit 15 and the scanning line driving circuits 14A and 14B and pixels. The data line 12 and the scanning line 11 between the lines 13 are sealed by the sealing material 112. Further, in the outside of the screen display area, a peripheral parting is formed on the counter substrate 31 in the same layer as the black matrix 113 so that light does not leak when assembled as a module. Reference numeral 114 denotes a common electrode potential LCCOM from the active matrix type liquid crystal display device side to the counter electrode 111 provided on the counter substrate 110 side.
(See FIG. 1) Upper and lower substrate conduction terminals 11 for supplying
5 and is configured to be electrically connected to the counter substrate by interposing a conductive adhesive having a predetermined diameter on the upper and lower substrate conduction terminals 115. Also, the external input / output terminal 11
6 is disposed outside the counter substrate 110 and is used for wire bonding, ACF (anisotropic).
c conductive film) Connected to an external IC by pressure bonding or the like.

As shown in FIG. 12 (B), a well-known TN (Twi
A liquid crystal 117 such as a steed Nematic) type liquid crystal is filled, and the liquid crystal sealing hole is sealed with a sealant 118 to form an active matrix type liquid crystal display device. In addition, by using a polymer-dispersed liquid crystal in which liquid crystal is dispersed as fine particles in a polymer, an alignment film and a polarizing plate are not required, so that light utilization efficiency is improved, and a bright active matrix liquid crystal display device is provided. it can. Further, in the case of a reflective liquid crystal display device using a non-transmissive metal film having a high reflectance such as an ITO film to an aluminum film for the pixel electrode, an SH (Sup) in which liquid crystal molecules are almost vertically aligned in the absence of applied voltage.
er Homeotropic) type liquid crystal or the like may be used. Needless to say, other liquid crystals may be used.

(Description of Projection Display Device) FIG. 13 shows a configuration example of a data projector as an example of a projection display device to which the active matrix liquid crystal display device having the above-mentioned configuration is applied as a light valve.

In FIG. 13, 370 is a light source such as a halogen lamp, 371 is a parabolic mirror, 372 is a heat ray cut filter, 373, 375 and 376 are blue-reflecting, green-reflecting and red-reflecting dichroic mirrors, respectively.
4, 377 is a reflection mirror, 378, 379 and 380 are light valves comprising the active matrix type liquid crystal display device of the above embodiment, 383 is a dichroic prism, 3
Reference numeral 85 is a control device. Image signals, clock signals, and various control signals externally supplied to the active matrix type liquid crystal display device substrate shown in FIG. 1 are formed by the control device 385.

In the data projector of this embodiment, the white light emitted from the light source 370 is condensed by the parabolic mirror 371 and passes through the heat ray cut filter 372 to block the heat rays in the infrared region, so that only visible light is emitted. It is incident on the dichroic mirror system. Then, first of all, the blue light (about 500 nm) is reflected by the blue reflection dichroic mirror 373.
The following wavelengths) are reflected and other light (yellow light) is transmitted. The reflected blue light changes its direction by the reflection mirror 374 and enters the blue modulation light valve 378.

On the other hand, the light transmitted through the blue reflection dichroic mirror 373 is green reflection dichroic mirror 3.
75, the green light (wavelength of about 500 to 600 nm) is reflected, and the other light, red light (about 600).
(wavelengths above nm) are transmitted. Dichroic mirror 3
The green light reflected at 75 is the green modulation light valve 379.
Incident on. Further, the red light transmitted through the dichroic mirror 375 changes its direction by the reflection mirrors 376 and 377 and is incident on the red modulation light valve 380.

The light valves 378, 379 and 380 are
Light that is driven by the blue, green, and red primary color signals supplied from a signal processing circuit (not shown) and enters each light valve is modulated by each light valve and then combined by the dichroic prism 383. The dichroic prism 383 has a red reflecting surface 381 and a blue reflecting surface 382.
And are formed so as to intersect with each other. Then, the color image combined by the dichroic prism 383 is enlarged and projected on the screen by the projection lens 384 and displayed.

[0063]

As described above, according to the present invention, a plurality of signal wirings are formed on a substrate and are connected to each of the plurality of signal wirings formed on the signal wirings via an insulating film. A relay wiring having a resistance higher than that of the signal wiring and an auxiliary relay wiring connected to the relay wiring and the transistor and having a resistance lower than the relay wiring, wherein the relay wiring is It is characterized in that the width, length, and film thickness of the other relay wirings connected to the signal wiring are substantially equal to each other, and the plurality of auxiliary relay wirings are auxiliary relay wirings of different lengths. As a result, the resistance value of the relay wiring becomes substantially uniform. Therefore, by wiring the plurality of signal wirings substantially in parallel with each other in a region intersecting with the relay wirings and making the wiring widths substantially equal to each other, the overlapping capacitance with other signal wirings becomes substantially uniform, and a signal to be transmitted is transmitted. The time constants for are almost equal among the signal wiring paths. Furthermore, since the length, width, and film thickness of the relay wiring are almost the same, even if the wiring width deviates from the target value due to process variations, the variation in resistance value and capacitance value between the signal wiring paths becomes almost constant, and the time constant There is an effect that it is possible to suppress the display unevenness of the active matrix type liquid crystal display device due to the variation of The signal wiring to which the present invention is applied is not only an image signal line for transmitting a phase expanded image signal, but also a clock signal wiring for transmitting an externally input clock signal to a shift register circuit, or the image signal line. There is an effect that it can be applied to various signal wirings such as an image auxiliary input signal line for transmitting an image auxiliary input signal for assisting a signal.

Since the relay wiring can be formed in the same process as the scanning line and the auxiliary relay wiring can be formed in the same process and the same material as the data line, it is not necessary to increase the number of processes, and the display of the active matrix type liquid crystal display device can be achieved. There is an effect that unevenness can be suppressed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of an active matrix type liquid crystal display device substrate that constitutes an active matrix type liquid crystal display device to which the present invention is applied.

FIG. 2 is a wiring layout diagram showing an embodiment in which the present invention is applied to a connection portion between a signal wiring group for supplying an image signal and a sample hold circuit in an active matrix type liquid crystal display device.

FIG. 3 is a wiring layout diagram showing a modified example of the embodiment of FIG.

FIG. 4 is a wiring layout diagram showing another modification of the embodiment of FIG.

5 is a wiring layout diagram showing still another modified example of the embodiment of FIG.

6 is a wiring layout diagram showing still another modified example of the embodiment of FIG.

FIG. 7 is a wiring layout diagram showing a second embodiment of the present invention.

FIG. 8 is a configuration diagram showing a shift register circuit and a clock signal wiring group which supplies a clock signal to the shift register circuit in an active matrix type liquid crystal display device to which the present invention is preferably applied.

FIG. 9 is a cross-sectional view showing the manufacturing process (first half) of the pixel TFT section and the image signal line section of the active matrix type liquid crystal display device to which the present invention is applied in the order of steps.

FIG. 10 is a cross-sectional view showing the manufacturing process (middle stage) of the pixel TFT section and the image signal line section of the active matrix type liquid crystal display device to which the present invention is applied in the order of steps.

FIG. 11 is a cross-sectional view showing the manufacturing process (second half) of the pixel TFT section and the image signal line section of the active matrix type liquid crystal display device to which the present invention is applied in the order of steps.

12A is a plan view of an active matrix liquid crystal display device, and FIG. 12B is a cross-sectional view taken along line YY ′ of FIG.

FIG. 13 is a schematic configuration diagram of a data projector as an example of a projection display device to which the active matrix liquid crystal display device of the embodiment is applied as a light valve.

FIG. 14 is a timing chart as an example showing a relationship between a phase expanded image signal and a sampling signal of an active matrix type liquid crystal display device.

FIG. 15 is a circuit diagram as an example showing a connection relationship between a signal hold group for supplying image signals and a sample hold circuit in a substrate for an active matrix type liquid crystal display device.

FIG. 16 is a layout diagram showing connection wirings of a signal wiring group for supplying image signals and a sample hold circuit in an active matrix type liquid crystal display device substrate.

FIG. 17 is a plan view of a pixel portion of an active matrix liquid crystal display device of the present invention.

FIG. 18 is a configuration diagram showing an example of a NAND circuit and a signal wiring group for supplying an enable signal to the NAND circuit in the preferred active matrix type liquid crystal display device to which the present invention is applied.

FIG. 19 is a timing chart as an example showing the relationship between the enable signal and the sampling signals X1, X2, ..., Xn in the active matrix type liquid crystal display device to which the present invention is preferably applied, and (A) Adjacent sampling , Xn overlap each other, and (B) a timing chart in which adjacent sampling signals X1, X2, ..., Xn are separated from each other.

FIG. 20 shows equivalent circuits constituting a sample hold circuit and a precharge circuit of an active matrix type liquid crystal display device of the present invention, which are (A) N-channel type TFT, (B) P-channel type TFT and (C), respectively. ) CMOS
An equivalent circuit diagram showing a TFT.

[Explanation of symbols]

1 semiconductor layer 1a channel region 2 gate insulating film 3 polysilicon film 3a capacitance line 4 first interlayer insulating film 5, 8 contact hole 6 aluminum film 7 second interlayer insulating film 9 ITO film 9a pixel electrode 10 substrate 11 scanning line 12 data Line (source electrode) 13 pixels 14A, 14B Y shift register circuit 15 data line drive circuit 16 sample hold circuit 17 precharge circuit 18 precharge circuit drive signal line 19A image auxiliary input signal line (NRS1) 19B image auxiliary input signal line ( NRS2) 20 Image signal wiring group 41 Sample-hold TFT source electrode 42 Sample-hold TFT drain electrode 42A P-channel TFT 42B N-channel TFT 43 Sample-hold TFT source electrode side contact hole 44 Sample-hold TFT drain Contact hole 45 between the image signal line and the relay wiring 49A contact hole between the relay wiring and the auxiliary relay wiring 49A Contact hole between the image auxiliary input signal line (NRS1) and the relay wiring 49B Contact hole 50A between input signal line (NRS2) and relay wiring Contact hole 50B between relay wiring H1 and auxiliary relay wiring S1 Contact holes 81 and 82 between relay wiring H2 and auxiliary relay wiring S2 Enable signal lines To wirings 91 to 98 for relaying from the NAND circuit to wirings for relaying from the clock signal line to the shift register circuit 100 Resist 101 High concentration impurity ions 110 Counter substrate 111 Counter electrode 112 Sealing material 113 Black matrix 115 Vertical conduction terminal 116 External input / output Terminal 117 Liquid crystal 118 Stopper 130 Pixel region 150 X shift register circuit 160 Sample and hold TFT 170 Precharge TFT 180 Polysilicon wiring 200, 201 Clocked inverter 202, 203 NAND circuit 370 Lamp 373, 375, 376 Dichroic mirror 374, 377 Reflection mirror 378 , 379, 380 Light valve 383 Dichroic prism 384 Projection lens 385 Control device

Claims (12)

(57) [Claims] 1. A relay having a plurality of signal wirings on a substrate and a plurality of signal wirings connected to each of the plurality of signal wirings via an insulating film and having a resistance higher than that of the signal wirings. Wiring, and an auxiliary relay wiring connected to the relay wiring and a transistor of a peripheral circuit and having a resistance lower than that of the relay wiring. The relay wiring is connected to another signal wiring. And the width and length of the relay wiring and the film thickness are almost equal to each other,
The substrate for an active matrix type liquid crystal display device, wherein the plurality of auxiliary relay wirings are formed of auxiliary relay wirings having different lengths. 2. The substrate for an active matrix type liquid crystal display device according to claim 1, wherein the plurality of relay wirings have the same pattern shape. 3. The substrate for an active matrix type liquid crystal display device according to claim 1, wherein the signal wiring and the auxiliary relay wiring are formed of the same film. 4. The transistor of the peripheral circuit has a plurality of first contact holes that connect a source region and the auxiliary relay wiring, and a plurality of second contact holes that connect a drain region and the wiring, The first contact holes and the second contact holes are alternately arranged, and the gate electrodes are the first contact holes and the second contact holes.
4. The substrate for an active matrix type liquid crystal display device according to claim 1, wherein the substrate is meandering so as to avoid the contact hole. 5. The active matrix type liquid crystal display device according to claim 1, wherein the width of the auxiliary relay wiring is narrowed in a region of a transistor of the peripheral circuit. substrate. 6. The active matrix type according to claim 1, wherein the signal wiring is an image signal line and the peripheral circuit is a sampling and holding circuit. Substrate for liquid crystal display device. 7. The active element according to claim 1, wherein the signal line is an image auxiliary input signal line, and the peripheral circuit is a precharge circuit. Substrate for matrix type liquid crystal display device. 8. The substrate for an active matrix type liquid crystal display device according to claim 7, wherein the plurality of image auxiliary input signal lines are image auxiliary input signal lines having polarities opposite to each other. 9. The relay wiring is a transistor for driving a pixel.
9. The substrate for an active matrix type liquid crystal display device according to claim 1, wherein the conductive film is formed of the same film as the gate electrode of the transistor . 10. The auxiliary relay wiring drives a pixel.
10. The substrate for an active matrix type liquid crystal display device according to any one of 1 to 9, which is a conductive film formed of the same film as a data line connected to a transistor . 11. The active matrix type liquid crystal display device substrate according to claim 1 and a transparent counter substrate having a counter electrode are arranged at an appropriate interval, and An active matrix type liquid crystal display device, wherein liquid crystal is filled in a space between the active matrix type liquid crystal display device substrate and the counter substrate. 12. A light source and light from the light source are modulated,
An active matrix type liquid crystal display device according to claim 11 which transmits or reflects, and projection optical means for condensing and magnifying and projecting light modulated by the active matrix type liquid crystal display device. Projection display device.