CN112764282B

CN112764282B - Array substrate, liquid crystal display panel and liquid crystal display device

Info

Publication number: CN112764282B
Application number: CN202110126495.2A
Authority: CN
Inventors: 陈国朵; 余思慧
Original assignee: HKC Co Ltd
Current assignee: HKC Co Ltd
Priority date: 2021-01-29
Filing date: 2021-01-29
Publication date: 2022-01-04
Anticipated expiration: 2041-01-29
Also published as: WO2022161103A1; CN112764282A

Abstract

The application provides an array substrate, a liquid crystal display panel and a liquid crystal display device, and relates to the technical field of display, wherein the array substrate comprises a display area and a peripheral area surrounding the display area, the display area comprises a plurality of sub-pixel areas which are arranged in an array manner, one sub-pixel area corresponds to one sub-pixel unit, the peripheral area comprises a plurality of connecting areas, and at least one side, close to the peripheral area, of each row of sub-pixel area is provided with one connecting area; the connecting region is provided with a driving auxiliary lead and a scanning auxiliary lead which extend along the column direction, and the length of the driving auxiliary lead along the column direction, the length of the scanning auxiliary lead along the column direction and the length of the sub-pixel region along the column direction are the same; the array substrate enables the connecting regions to be uniformly distributed relative to the pixel regions by changing the lengths of the driving auxiliary lead and the scanning auxiliary lead, and further solves the problem of nonuniform alignment.

Description

Array substrate, liquid crystal display panel and liquid crystal display device

Technical Field

The application belongs to the technical field of display, and particularly relates to an array substrate, a liquid crystal display panel and a liquid crystal display device.

Background

A Liquid Crystal Display (LCD) panel has the advantages of low radiation, small size, and low power consumption, and is widely used in various electronic devices such as notebook computers and televisions.

Among them, the Liquid Crystal display panel generally includes an array substrate (TFT), a Color Filter substrate (CF), and a Liquid Crystal (LC) and a sealant frame sandwiched between the array substrate and the Color Filter substrate.

In the prior art, before coating liquid crystal on an array substrate, an alignment film coated on the array substrate needs to be processed by an alignment film alignment process, so that the alignment film has an ability to align liquid crystal molecules along a uniform direction at a certain pretilt angle, and an ability to form alignment anisotropy.

A commonly used alignment film alignment process is rubbing alignment: the cloth outside the roller is utilized to generate friction according to the mechanics principle for alignment. Rubbing alignment requires that the display area (AA) on the array substrate is uniformly processed, but at the edge of the display area, for example, at the side of the display area close to the scan driving circuit, usually in order to introduce the signal of the scan driving circuit into the display area, it is necessary to connect the scan driving circuit with the scan lines in the display area by using connecting lines, so that the scan signal sent by the scan driving circuit can be transmitted to the scan lines of the display area after being transmitted through the connecting lines, but the arrangement of the connecting lines is usually not uniformly distributed relative to the sub-pixel areas in the display area, which causes different abrasion to the cloth outside the roller during alignment, thereby causing the problem of uneven alignment (rubbing mura) in the sub-pixel areas.

Disclosure of Invention

The embodiment of the application provides an array substrate, a liquid crystal display panel and a liquid crystal display device, wherein the length of a driving auxiliary lead and the length of a scanning auxiliary lead are changed, so that a connecting region is uniformly distributed relative to a pixel region, and the problem of nonuniform alignment is solved.

In order to achieve the purpose, the technical scheme is as follows:

in a first aspect, an array substrate is provided, including: the substrate base plate, this array substrate still includes:

the display device comprises a display area and a peripheral area surrounding the display area, wherein the display area comprises a plurality of sub-pixel areas which are arranged in an array mode, one sub-pixel area corresponds to one sub-pixel unit, the peripheral area comprises a plurality of connecting areas, and one connecting area is arranged on at least one side, close to the peripheral area, of each row of sub-pixel areas;

the connecting region is provided with a driving auxiliary lead and a scanning auxiliary lead which extend along the column direction, and the length of the driving auxiliary lead along the column direction and the length of the scanning auxiliary lead along the column direction are the same as the length of the sub-pixel region along the column direction;

the driving auxiliary lead is used for being electrically connected with a scanning driving circuit, the scanning auxiliary lead is used for being electrically connected with the corresponding row of sub-pixel units, the driving auxiliary lead is electrically connected with the scanning auxiliary lead, and the driving auxiliary lead transmits scanning signals sent by the scanning driving circuit to the corresponding sub-pixel units.

According to the array substrate provided by the embodiment of the application, the length of the driving auxiliary lead and the length of the scanning auxiliary lead in the column direction are increased, so that the lengths of the driving auxiliary lead and the scanning auxiliary lead are the same as the length of the sub-pixel region in the column direction, the abrasion degree of a roller is uniform when alignment processing is performed subsequently, particularly when the roller rolls in the row direction, and the problem of nonuniform alignment of the sub-pixel region can be solved.

Optionally, as a possible implementation manner, the connection region is further provided with a plurality of pairs of via holes uniformly arranged in a column direction, each pair of via holes includes a first via hole and a second via hole arranged in a row direction, the first via hole is disposed on one side of the driving auxiliary lead, which is away from the substrate, along a thickness direction of the array substrate, and a projection of the first via hole is located in a projection of the driving auxiliary lead, the second via hole is disposed on one side of the scanning auxiliary lead, which is away from the substrate, and a projection of the second via hole is located in a projection of the scanning auxiliary lead; the driving auxiliary lead and the scanning auxiliary lead are electrically connected through the conducting layers laid in the first through hole and the second through hole. In this implementation manner, the first via holes corresponding to the driving auxiliary leads are uniformly distributed in the column direction, and the second via holes corresponding to the scanning auxiliary leads are uniformly distributed in the column direction, so that the wear degree of the roller is further uniform when alignment processing is performed subsequently, particularly when the roller rolls in the row direction.

Optionally, as a possible implementation manner, the peripheral region further includes a plurality of driving leads extending along the row direction, the driving leads are in one-to-one correspondence with and connected to the driving auxiliary leads, the display region further includes a plurality of scanning lines extending along the row direction, and the scanning lines are in one-to-one correspondence with and connected to the scanning auxiliary leads;

along the thickness direction of the array substrate, the driving auxiliary lead is positioned on one side of the scanning auxiliary lead, which is far away from the substrate, the scanning line and the scanning auxiliary lead are positioned on the same layer, and the driving lead and the driving auxiliary lead are positioned on the same layer;

the driving lead is further electrically connected with the scanning driving circuit and used for receiving scanning signals sent by the scanning driving circuit and transmitting the scanning signals to the corresponding driving auxiliary lead, and the scanning lines are used for receiving the scanning signals sent by the scanning auxiliary lead and transmitting the scanning signals to the corresponding sub-pixel units. In this implementation, the driving lead is electrically connected to the scanning driving circuit, and the scanning line is electrically connected to the corresponding sub-pixel unit, so that the function of the scanning driving circuit sending the scanning signal to the sub-pixel circuit can be realized.

Optionally, as a possible implementation manner, when the driving auxiliary lead and the scanning auxiliary lead are located in adjacent layers, a projection of the driving auxiliary lead and a projection of the scanning auxiliary lead are not adjacent in a thickness direction of the array substrate. In this implementation, since the drive auxiliary leads and the scan auxiliary leads are located at adjacent layers, direct contact can be avoided when the projections are not adjacent.

Optionally, as a possible implementation manner, when the driving auxiliary lead and the scanning line are located at two non-adjacent layers, along the thickness direction of the array substrate, a projection of the driving auxiliary lead and a projection of the scanning auxiliary lead overlap;

the projection of the second via hole is located in a first non-overlapping area, wherein the first non-overlapping area is used for indicating a region where the projection of the scanning auxiliary lead is not overlapped with the projection of the driving auxiliary lead in the projection of the scanning auxiliary lead. In this implementation, the second via hole is disposed in the first non-overlapping region, so that the influence on the driving auxiliary lead when the second via hole is formed can be avoided.

Optionally, as a possible implementation manner, the driving auxiliary lead is located on a side of the scanning auxiliary lead away from the display area along the row direction. In this implementation, material can be saved.

Optionally, as a possible implementation manner, the driving auxiliary lead includes a plurality of first connector sub-portions, the scanning auxiliary lead includes a plurality of second connector sub-portions, and the number of the first connector sub-portions is the same as that of the second connector sub-portions;

the plurality of first connector sub-sections positioned in odd-numbered rows and the plurality of second connector sub-sections positioned in even-numbered rows form the same column, and the plurality of first connector sub-sections positioned in even-numbered rows and the plurality of second connector sub-sections positioned in odd-numbered rows form the same column;

the opposing cross-sections of two adjacent first connector portions overlap and the opposing cross-sections of two adjacent second connector portions overlap.

Optionally, as a possible implementation manner, the first via and the first connector sub-portion correspond to each other one by one; the second via hole and the second connector sub-portion correspond to each other one to one.

Optionally, as a possible implementation manner, in the thickness direction of the array substrate, a projection of the first via is located at the center of the first connector sub-portion, and a projection of the second via is located at the center of a second non-overlapping area, where the second non-overlapping area is used to indicate an area where a projection of the second connector sub-portion is not overlapped with a projection of the first connector sub-portion in the projection of the second connector sub-portion.

Optionally, as a possible implementation manner, the cross section of the driving auxiliary lead and the cross section of the scanning auxiliary lead are both rectangular cross sections and have the same size.

Optionally, as a possible implementation manner, the pairs of the via holes are even and are symmetrically distributed about a center line of the sub-pixel region in the row direction.

Optionally, as a possible implementation manner, the opening sizes of the first via and the second via are the same.

In a second aspect, a liquid crystal display panel is provided, which includes the array substrate and the opposite substrate as described in any one implementation manner of the first aspect and the first aspect, and a liquid crystal layer disposed between the array substrate and the opposite substrate.

In a third aspect, there is provided a liquid crystal display device comprising: the liquid crystal display panel and the driving device for driving the display panel according to the first aspect are described in any one implementation manner of the first aspect and the second aspect.

In a fourth aspect, an electronic device is provided, comprising: a liquid crystal display device as described in the third aspect.

According to the array substrate, the liquid crystal display panel, the liquid crystal display device and the electronic equipment, the length of the driving auxiliary lead and the length of the scanning auxiliary lead in the column direction are increased in the array substrate, so that the lengths of the driving auxiliary lead and the scanning auxiliary lead are the same as the length of the sub-pixel area in the column direction, the first through holes corresponding to the driving auxiliary lead are uniformly distributed in the column direction, the second through holes corresponding to the scanning auxiliary lead are uniformly distributed in the column direction, and therefore when alignment processing is carried out subsequently, particularly when a roller rolls in the row direction, the degree of abrasion of the roller is uniform, and the problem of nonuniform alignment of the sub-pixel area can be solved.

Drawings

Fig. 1 is a schematic structural diagram of a liquid crystal display device according to an embodiment of the present disclosure;

fig. 2 is a schematic top view of an array substrate according to an embodiment of the present disclosure;

FIG. 3 is a schematic top view of a connection region and a sub-pixel region on an array substrate in accordance with an exemplary technique;

FIG. 4 is a schematic cross-sectional view of the sub-pixel area along direction AA' in FIG. 3;

FIG. 5 is a schematic cross-sectional view of the attachment zone of FIG. 3 taken along direction aa';

fig. 6 is a schematic top view of a connection region and a sub-pixel region in an array substrate according to an embodiment of the present disclosure;

FIG. 7 is a schematic cross-sectional view of the attachment zone in FIG. 6 in the direction bb';

FIG. 8 is a schematic top view of a drive lead and a drive assist lead provided by an embodiment of the present application;

FIG. 9 is a schematic top view of a driving auxiliary lead and a scanning auxiliary lead provided by an embodiment of the present application;

fig. 10 is a schematic top view of another array substrate provided in the embodiments of the present application;

FIG. 11 is a schematic cross-sectional view of the attachment zone of FIG. 10 in the cc' direction;

fig. 12 is a schematic top view of driving auxiliary leads and scanning auxiliary leads provided in an embodiment of the present application.

Reference numerals:

1-a frame; 2-cover glass; 3-a liquid crystal display panel; 4-a backlight module; 5-a circuit board; 31-a display area; 32-a peripheral zone; 33-subpixel areas; 34-a connecting zone; 35-connecting lines; 351-driving auxiliary leads; 352-drive leads; 36-scan line; 361-scan auxiliary lead; 37-data line; 3510-first connector portion; 3610-a second connector portion; 40-a scan drive circuit; 100-sub-pixel unit; 300-an array substrate; 310-substrate base plate; 320-a first insulating layer; 330-pixel electrodes; 340-a second insulating layer; 350-common electrode; 355-a common electrode line; 360-a third insulating layer; 370-a fourth insulating layer; 380-a conductive layer; 400-a counter substrate; 500-liquid crystal; 600-alignment film; 700-via holes; 710-a first via; 720-a second via; 800-liquid crystal display device; 810-driving means.

Detailed Description

In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.

Unless otherwise defined, technical or scientific terms used herein shall have the ordinary meaning as understood by those skilled in the art. The terms "first," "second," "third," "fourth," and the like as used in the description and in the claims of the present application do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. Thus, features defined as "first", "second", "third", "fourth" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, "a plurality" means two or more unless otherwise specified.

The directional terms "left", "right", "upper" and "lower" are defined with respect to the orientation in which the display assembly is schematically placed in the drawings, and it is to be understood that these directional terms are relative concepts, which are used for descriptive and clarifying purposes, and may be changed accordingly according to the change of the orientation in which the array substrate or the display device is placed.

With the development of display technology, liquid crystal display technology has been widely applied to various electronic devices. An electronic apparatus for performing display using a liquid crystal display technology includes a liquid crystal display device, and the liquid crystal display device generally includes a liquid crystal display panel including an array substrate and a driving device for driving the liquid crystal display panel. The embodiment of the application provides an array substrate which is applied to a liquid crystal display device in electronic equipment.

The electronic device can be a plurality of different types of electronic devices such as a smart phone, a tablet computer, an electronic reader, a vehicle-mounted computer, a navigator, a digital camera, a smart television and a smart wearable device. The embodiments of the present application do not set any limit to this.

Fig. 1 shows a schematic structural diagram of a liquid crystal display device 800 according to an embodiment of the present application. As shown in fig. 1, the main structure of the liquid crystal display device 800 includes a frame 1, a cover glass 2, a liquid crystal display panel 3, a backlight module 4, a circuit board 5, and other electronic components including a camera. The circuit board 5 is a driving device for driving the liquid crystal display panel, or is a part of the driving device for driving the liquid crystal display panel.

As shown in fig. 1, the liquid crystal display panel 3 includes an array substrate 300, a counter substrate 400, a liquid crystal layer 500 disposed between the array substrate 300 and the counter substrate 400, and upper and lower polarizing layers. The array substrate 300 and the opposite substrate 400 are bonded together by the sealant, so that the liquid crystal layer 500 is limited in the region surrounded by the sealant. When the color filter layer is disposed on the opposite substrate 400, the opposite substrate 400 is a color film substrate.

The longitudinal section of the frame 1 is U-shaped, the liquid crystal display panel 3, the backlight module 4, the circuit board 5 and other electronic accessories including a camera and the like are arranged in the frame 1, the backlight module 4 is positioned below the liquid crystal display panel 3, the circuit board 5 is positioned between the backlight module 4 and the frame 1, and the cover plate glass 2 is positioned on one side of the liquid crystal display panel 3, which is far away from the backlight module 4.

As shown in fig. 1, an alignment film 600 is usually disposed on each of the array substrate 300 and the opposite substrate 400, and after the alignment film 600 contacts with the liquid crystal in the liquid crystal layer 500, the liquid crystal can generate a pretilt angle in a certain direction, so as to provide an angle for the liquid crystal molecules, and the pretilt angle has an important influence on the driving voltage, the contrast ratio, the response time, the viewing angle, and the like of the liquid crystal display panel 3.

On the basis of fig. 1, fig. 2 shows a schematic top view of an array substrate 300 in fig. 1. As shown in fig. 2, in the top view, the array substrate 300 includes a display area 31 and a peripheral area 32, and the peripheral area 32 surrounds the display area 31 in fig. 2 as an example.

As shown in fig. 2, the display area 31 includes a plurality of scan lines 36 (G1 to Gm, m being a positive integer shown in fig. 2) extending in a row direction (x direction shown in fig. 2) and a plurality of data lines 37 (S1 to Sn, n being a positive integer shown in fig. 2) extending in a column direction (y direction shown in fig. 2), wherein the x direction and the y direction are perpendicular to each other.

As shown in fig. 2, the display area 31 further includes sub-pixel areas 33 defined by the scan lines 36 and the data lines 37 crossing each other, and one sub-pixel unit 100 is distributed in each sub-pixel area 33. In fig. 2, a plurality of rectangular sub-pixel regions 33 arranged in an array is illustrated as an example, in this case, the sub-pixel units 100 arranged in a row along the row direction are referred to as a row of sub-pixel units 100, and the sub-pixel units 100 arranged in a row along the column direction are referred to as a column of sub-pixel units 100. Based on this, if each scan line 36 is connected to a row of sub-pixel units 100, and each data line 37 is connected to a column of sub-pixel units 100, the scan line 36 is used for transmitting a scan signal to the corresponding row of sub-pixel units 100, and the data line 37 is used for transmitting a data signal to the corresponding column of sub-pixel units 100. Here, the sub-pixel units 100 distributed in the plurality of sub-pixel regions 33 are respectively used to form corresponding red sub-pixel units R, green sub-pixel units G, or blue sub-pixel units B.

As shown in fig. 2, the peripheral region 32 is used for wiring, and the scan driving circuit 40 may be disposed in the peripheral region 32. The scan driving circuit 40 is connected to the plurality of scan lines 36 in the display area 31, and the scan driving circuit 40 is used for providing scan signals to the sub-pixel units 100 through the scan lines 36. Therefore, a plurality of connecting lines 35 (L1-Lm, m is a positive integer shown in fig. 2) can be led out from the scan driving circuit 40, each connecting line 35 is connected to one scan line 36 in the display area 31, and the connecting lines 35 are used for receiving the scan signal sent by the scan driving circuit 40 and forwarding the scan signal to the scan lines 36 in the display area 31.

As shown in fig. 2, when each connection line 35 is connected to one scan line 36 in the display area 31, a connection area 34 is formed at the connection point, and the connection area 34 is located on a side of the 1 st sub-pixel area of each row near the peripheral area. Taking m scan lines 36 on the array substrate 300 as an example, m connection lines 35 are required to connect the m scan lines 36, so as to form m connection regions 34. As shown in fig. 2, the connection lines 35 are disposed on the left side of the display area 31, and the m connection areas 34 are arranged in a row on the left side of the display area 31 and adjacent to the 1 st row of the sub-pixel areas 33 in the display area 31. It should be understood that the connection lines 35, the scan lines 36, and the data lines 37 are disposed on one side of the array substrate 300 toward the opposite substrate 400 in the thickness direction of the array substrate 300. Here, the scan lines 36 and the data lines 37 are located at different layers and an insulating layer may also be generally disposed between the layers.

On the basis, when the alignment film 600 is coated on the array substrate 300, in order to enable the subsequent alignment film 600 to act on the liquid crystal better, the size of the coated alignment film 600 is usually larger than that of the display area 31, and at this time, the boundary of the alignment film 600 is located in the peripheral area 32, and the m connection areas 34 are closer to the display area 31 and usually included in the boundary of the alignment film 600. As shown in fig. 2, the m connection regions 34 are located between the left side boundary of the alignment film 600 and the left side boundary of the display region 31. Then, after the alignment film 600 is coated on the array substrate 300, the m connection regions 34 are usually covered by the alignment film 600, and an alignment process is subsequently performed on the alignment film 600 above the m connection regions 34.

Fig. 3 is a schematic top view of a connection region and a sub-pixel region 33 on an array substrate 300 in an exemplary technology, and fig. 3 includes a connection region 34 and a sub-pixel region 33. Fig. 4 is a schematic cross-sectional view of the sub-pixel region 33 in fig. 3 along the direction AA'. Fig. 5 is a schematic cross-sectional view of the attachment zone 34 of fig. 3 taken along direction aa'.

As shown in fig. 4, the array substrate 300 includes a substrate 310, and the array substrate 300 is provided with a Thin Film Transistor (TFT) circuit layer and a pixel electrode layer on a side of the substrate 310 close to the opposite substrate 400, the TFT circuit layer including TFTs, and the pixel electrode layer including pixel electrodes.

Illustratively, as shown in fig. 4, the array substrate 300 is provided with a TFT and a pixel electrode 330 electrically connected to a first electrode of the TFT on a substrate 310 of the array substrate and at each sub-pixel region 33. That is, the sub-pixel unit 100 includes a TFT and a pixel electrode 330 electrically connected to a first pole of the TFT.

The gates of the TFTs included in the sub-pixel units 100 in the same row are electrically connected to the same scan line 36, and the second poles of the TFTs included in the sub-pixel units 100 in the same column are electrically connected to the same data line 37. Wherein the first and second poles of the TFT are one of a source and a drain of the TFT, respectively.

As shown in fig. 4, a common electrode 350 may be further disposed on the array substrate 300, wherein, to facilitate power supply to the common electrode 350, the common electrode 350 in all the sub-pixel regions 33 may be an integrated film structure. Of course, the common electrode 350 may be separately provided. When the common electrodes 350 are separately disposed, the array substrate 300 further needs to dispose a plurality of common electrode lines 355 on the substrate 310, and referring to fig. 3, the number and the extending direction of the common electrode lines 355 are the same as those of the scan lines 36, and one common electrode line 355 and one scan line 36 correspond to the sub-pixel units 100 in the same row and are separately disposed on two opposite sides of the sub-pixel units 100 in the same row. The common electrode line 355 is connected to the common electrode 350 in the same row of the sub-pixel region 33, and supplies power to the common electrode 350 in the same row of the sub-pixel region 33. In order to facilitate direct connection between the common electrode 350 and the common electrode line 355 disposed at different layers, the common electrode 350 may have a size slightly larger than that of the pixel electrode 33 and may be overlaid on the common electrode line 355 such that the common electrode line 355 is in direct contact with the common electrode 350. Here, it is understood that the TFT, the pixel electrode 330, the common electrode 350, and the common electrode line 355 are disposed on a side of the substrate base plate 310 facing the opposite base plate 400.

In the thickness direction of the array substrate, fig. 4 illustrates that the common electrode 350 is positioned between the TFT and the pixel electrode 330, and in this case, the common electrode 350 and the pixel electrode 330 are isolated from each other by the first insulating layer 320. In addition, a second insulating layer 340 may be disposed between the TFT and the common electrode 350, and based on this, the pixel electrode 330 is electrically connected to the drain electrode of the TFT through a channel located on the first insulating layer 320, the common electrode 350, and the second insulating layer 340. The first insulating layer 320 and the second insulating layer 340 are uniformly laid on the display area 31, and only the first insulating layer 320 in the area, or the second insulating layer 340 in the area, or the first insulating layer 320 in the area and the second insulating layer 340 in the area need to be removed by a method such as opening a hole in the area.

Of course, the common electrode 350 may also be disposed on the side of the pixel electrode 330 away from the TFT, in which case, the common electrode 350 and the pixel electrode 330 may also be isolated by the first insulating layer 320.

As shown in fig. 3 and 5, for example, when designing a connection structure of the connection lines 35 and the scan lines 36, in order to facilitate connection of the connection lines 35 and the scan lines 36 and increase a connection area, each connection line 35 may include one driving auxiliary lead 351 and one driving lead 352, where the driving lead 352 extends in a row direction, the driving auxiliary lead 351 extends in a column direction, and a projection shape of the driving lead 352 and the driving auxiliary lead 351 on the substrate is a T shape, and of course, may also be an L shape, which is not limited in this embodiment of the present application. Here, the driving auxiliary lead 351 and the driving lead 352 are located at the same layer in the thickness direction of the array substrate 300 and are in an integrated structure. The driving lead 352 is used for connecting to the scan driving circuit 40 and receiving a scan signal transmitted from the scan driving circuit 40.

Accordingly, in order to facilitate the connection of the scan line 36 with the connection line 35, a scan auxiliary lead 361 extending in the column direction is externally connected to one end of the scan line 36 adjacent to the connection line 35. The scan auxiliary lead 361 extends in the column direction y, the scan line 36 extends in the row direction x, the scan auxiliary lead 361 is located in the connection region 34, and the scan line 36 is located in the display region 31. The projection shapes of the scan auxiliary lead 361 and the scan line 36 on the substrate base plate are L-shaped. Here, the scan auxiliary lead 361 and the scan line 36 are located at the same layer and integrated along the thickness direction of the array substrate 300.

In the exemplary technique, the connecting line 35 is located on a side of the scan line 36 away from the substrate base 310 in the thickness direction of the array substrate, and there is no overlap in the projections of the connecting line 35 and the scan line 36 on the substrate base. Accordingly, in order to connect the driving auxiliary lead line 351 and the scanning auxiliary lead line 361, a plurality of first via holes 710 are formed at a side of the driving auxiliary lead line 351 remote from the substrate, and a plurality of second via holes 720 are formed at a side of the scanning auxiliary lead line 361 remote from the substrate, so that the driving auxiliary lead line 351 and the scanning auxiliary lead line 361 can be connected through the conductive layer 380 laid in the first via holes 710 and the second via holes 720.

However, in the exemplary technique, only the connection problem is considered, and the distribution of the driving auxiliary lead line 351 and the scanning auxiliary lead line 361 and the first via hole 710 and the second via hole 720 only satisfies the connection requirement, for example, with respect to each row of the 1 st sub-pixel region 33, the driving auxiliary lead line 351 and the scanning auxiliary lead line 361 in the corresponding connection region 34 are located at a side close to the scan line 36, so that the plurality of first via holes 710 and second via holes 720 corresponding to the driving auxiliary lead line 351 and the scanning auxiliary lead line 361 are also concentrated at the side close to the scan line 36 when being opened, which results in that the region indicated by Z in fig. 3 is empty, that is, with respect to the sub-pixel region 33, there is no wiring and no opening at the side close to the common electrode line 355. Therefore, when the uneven-distribution driving auxiliary lead 351 and scanning auxiliary lead 361, and the first via hole 710 and the second via hole 720 respectively formed on the driving auxiliary lead 351 and scanning auxiliary lead 361 are aligned after the alignment film is coated subsequently, and the roller is subjected to rolling processing in the left-to-right direction, the uneven-distribution wiring structure and the via holes are different in abrasion to the cloth outside the roller, so that the problem of uneven alignment (rubbing mura) occurs in the sub-pixel region 33.

In view of this, the embodiment of the present application provides an array substrate, in which the lengths of the driving auxiliary lead and the scanning auxiliary lead in the column direction are increased to be the same as the length of the sub-pixel region in the column direction, so that when the sub-pixel region rolls in the row direction by using the roller, the abrasion on both sides of the roller is uniform, and the alignment of the sub-pixel region is uniform.

The structure of the array substrate 300 according to the embodiment of the present invention will be described in detail with reference to fig. 2 and 6 to 12.

Fig. 6 is a schematic top view of a connection region and a sub-pixel region on an array substrate 300 according to an embodiment of the present disclosure, and fig. 6 includes a connection region 34 and a sub-pixel region 33. Fig. 7 is a schematic cross-sectional view of the attachment zone 34 in fig. 6 in the direction bb'.

The embodiment of the present application provides an array substrate 300, as shown in fig. 7, the array substrate 300 includes a substrate base plate 310. Illustratively, the substrate 310 is typically made of glass.

As shown in fig. 2 and 6, the array substrate 300 includes: a display area 31 and a peripheral area 32 surrounding the display area 31. The display area 31 includes a plurality of sub-pixel areas 33 arranged in an array, and one sub-pixel area 33 corresponds to one sub-pixel unit 100.

It should be understood that the display region 31, which refers to a region on the array substrate 300 where an image can be displayed, may be disposed at a middle portion of the array substrate 300. The peripheral area 32, which is an area incapable of displaying an image, surrounds the display area 31, wherein the width of the peripheral area 32 surrounding the display area 31 in the four directions of up, down, left, and right is not necessarily the same with respect to the display area 31. The sub-pixel region 33 refers to a region corresponding to display of any one of three primary color data included in one pixel data in an image.

Here, the structure of the sub-pixel unit 100 corresponding to the sub-pixel region 33 is the same as that of the sub-pixel unit 100 in the exemplary technology, and the structure thereof can be referred to the description of fig. 4.

The peripheral region 32 includes a plurality of connection regions 34, and one connection region 34 is provided on at least one side of each row of sub-pixel regions adjacent to the peripheral region 32.

As shown in fig. 2, both the left and right sides of each row of sub-pixel regions 33 are close to the peripheral region, and thus, one connection region 34 may be provided on the left side of each row of sub-pixel regions 33, or one connection region 34 may be provided on the right side of each row of sub-pixel regions 33, or one connection region may be provided on both the left and right sides of each row of sub-pixel regions 33. The arrangement of the connection region may specifically be set according to a driving manner, for example, in the case of single-side driving, one connection region may be arranged on the left side or the right side of each row of the sub-pixel region, and in the case of double-side driving, for example, one connection region may be arranged on both the left side and the right side of each row of the sub-pixel region. The embodiment of the present application does not limit this.

As shown in fig. 2, taking the display area 31 including m rows and n columns of sub-pixel regions 33, and taking each sub-pixel region 33 in the 1 st column of sub-pixel regions from left as the 1 st sub-pixel region 33 in each row of sub-pixel regions 33 as an example, one connecting region 34 may be disposed on the left side of each row of sub-pixel regions 33 near the peripheral region 32, that is, one connecting region 34 is correspondingly disposed in the peripheral region on the left side of each row of 1 st sub-pixel region 33, and then, m connecting regions 34 are disposed in total in the peripheral region 32 on the left side of m rows of sub-pixel regions 33. Also, the m connection regions 34 are arranged in a row in the row direction.

It is to be understood that the distance in the row direction between the connection region 34 and the sub-pixel region 33 may be set small in order to save space.

The connection region 34 is provided with a driving auxiliary lead 351 and a scanning auxiliary lead 361 extending in the column direction. Here, the length of the driving auxiliary wiring 351 in the column direction, the length of the scanning auxiliary wiring 361 in the column direction, and the length of the sub-pixel region 33 in the column direction are all the same.

Here, generally, for the convenience of connection, the lengths of the driving auxiliary wiring 351 and the scanning wiring 361 in the column direction are the same, and based on this, in the present application, the length of the driving auxiliary wiring 351 in the column direction, the length of the scanning auxiliary wiring 361 in the column direction, and the length of the sub-pixel region 33 in the column direction are all set to be the same with respect to the example technology, and at this time, by increasing the lengths of the driving auxiliary wiring 351 and the scanning auxiliary wiring 361 in the connection region 34 in the column direction, the driving auxiliary wiring 351 and the scanning auxiliary wiring 361 in the connection region 34 are distributed relatively uniformly in the column direction with respect to the sub-pixel region 33, so that the degree of abrasion to the roller is relatively uniform when alignment processing is performed subsequently, and the possibility of the problem of uneven alignment in the sub-pixel region 33 can be reduced.

The driving auxiliary lead line 351 is used for being electrically connected with the scanning driving circuit 40, the scanning auxiliary lead line 361 is used for being electrically connected with the corresponding sub-pixel units 100 in one row, the driving auxiliary lead line 351 is electrically connected with the scanning auxiliary lead line 361, and the driving auxiliary lead line 351 transmits scanning signals sent by the scanning driving circuit 40 to the corresponding sub-pixel units 100.

Optionally, as a possible implementation manner, the connection region 34 further defines a plurality of pairs of vias 700 uniformly arranged along the column direction, and each pair of vias 700 includes a first via 710 and a second via 720 arranged along the row direction. Referring to fig. 7, in the thickness direction of the array substrate 300, the first via 710 is disposed on a side of the driving auxiliary lead 351 away from the substrate 310, a projection of the first via 710 is located in a projection of the driving auxiliary lead 351, the second via 720 is disposed on a side of the scanning auxiliary lead 361 away from the substrate, and a projection of the second via 720 is located in a projection of the scanning auxiliary lead 361.

The driving auxiliary lead is electrically connected with the scanning auxiliary lead through the conducting layers laid in the first through hole and the second through hole.

It should be understood that the connection region 34 is provided with a plurality of pairs of vias 700 uniformly arranged in the column direction, each pair of vias 700 includes a first via 710 and a second via 720 arranged in the row direction, that is, the number of the first vias 710 and the second vias is the same, and the plurality of first vias 710 are uniformly arranged in the column direction and the plurality of second vias 720 are also uniformly arranged in the column direction.

Optionally, as a possible implementation manner, the pairs of the vias are even and symmetrically distributed about a center line of the sub-pixel region in the row direction.

As shown in fig. 6, the connection region 34 is opened with 6 pairs of vias, and the 6 pairs of vias are uniformly distributed along the column direction and symmetrically distributed about a center line (a straight line indicated by k in fig. 6) of the sub-pixel region 33 along the row direction.

The number of the first vias 710 disposed on the side of the driving auxiliary lead away from the substrate base plate is 6, and the first vias are symmetrically distributed about the center line k of the sub-pixel region 33 along the row direction, and the number of the second vias 720 disposed on the side of the scanning auxiliary lead away from the substrate base plate is also 6, and the second vias are symmetrically distributed about the center line k of the sub-pixel region 33 along the row direction.

In addition, the number of pairs of vias may be odd, and when the number of pairs of vias is odd, the pairs of vias may be symmetrically distributed about a center line of the sub-pixel region 33 in the row direction.

Optionally, as a possible implementation, the openings of the first via 710 and the second via 720 are the same size.

It should be understood that, since the distribution of the vias 700 also has a certain influence on the aligned roller, for example, the roller is abraded more by the area without vias, and less by the area with vias, when a plurality of pairs of vias are arranged uniformly in the column direction, the roller is abraded more uniformly in the longitudinal direction of the roller when rolling in the left-to-right direction, and when the pairs of vias are even and are distributed symmetrically about the center line of the sub-pixel region 33 in the row direction, the first and

second vias

710 and 720 included in the vias 700 have the same opening size, which further reduces the problem of non-uniform alignment of the roller on the sub-pixel region 33.

Of course, the opening sizes of the first via 710 and the second via 720 may also be different, and the specific size may be set and changed according to the need, which is not limited in this embodiment.

In addition, the conductive layer 380 may be formed simultaneously with the pixel electrode 330 in the sub-pixel region 33 by using the same material.

Optionally, as a possible implementation manner, the peripheral region 32 further includes a plurality of driving lead lines 352 extending along the row direction, the driving lead lines 352 correspond to and are connected to the driving auxiliary lead lines 351 in a one-to-one manner, the display region 31 further includes a plurality of scanning lines 36 extending along the row direction, and the scanning lines 36 correspond to and are connected to the scanning auxiliary lead lines 361 in a one-to-one manner.

Fig. 8 shows a schematic top view of one drive lead and one drive auxiliary lead connected. The projections of the driving leads 352 and the driving auxiliary leads 351 on the substrate base plate may be T-shaped as shown in (a) in fig. 8, or the projections of the driving leads 352 and the driving auxiliary leads 351 on the substrate base plate may be L-shaped as shown in (b) in fig. 8. In addition, the projections of the driving lead 352 and the driving auxiliary lead 351 may have other shapes, and may be specifically set according to needs, which is not limited in any way by the embodiment of the present application.

Along the thickness direction of the array substrate 300, the driving auxiliary lead line 351 is located at a side of the scanning auxiliary lead line 361 away from the substrate 310, the scanning line 36 and the scanning auxiliary lead line 361 are located at the same layer, and the driving lead line 352 and the driving auxiliary lead line 351 are located at the same layer.

The driving lead 352 is used for receiving a scanning signal sent by the scanning driving circuit 40 and transmitting the scanning signal to a corresponding driving auxiliary lead, and the scanning line 36 is used for receiving a scanning signal sent by the scanning auxiliary lead 361 and transmitting the scanning signal to a corresponding sub-pixel unit 100.

It should be understood that the driving auxiliary lead line 351 is located at a side of the scanning auxiliary lead line 361 away from the substrate base plate 310 in the thickness direction of the array substrate 300, and taking fig. 7 as an example, the driving auxiliary lead line 351 will be above when the scanning auxiliary lead line 361 is below. The driving auxiliary lead line 351 and the scanning auxiliary lead line 361 may be disposed at adjacent layers as shown in (a) of fig. 7, or the driving auxiliary lead line 351 and the scanning auxiliary lead line 361 may be disposed at two layers which are not adjacent as shown in (b) of fig. 7.

It is to be understood that the driving leads 352 and the driving auxiliary leads 351 may be formed at one time by a photolithography technique at the time of manufacturing when the driving leads 352 and the driving auxiliary leads 351 are located at the same layer. At this time, the thicknesses of the driving wire 352 and the driving auxiliary wire 351 are the same. In addition, the line widths of the driving wire 352 and the driving auxiliary wire 351 may be the same or different, and the present application does not limit the line widths at all.

It should be understood that when the scan line 36 and the scan auxiliary lead 361 are located at the same layer, the scan line 36 and the scan auxiliary lead 361 may be formed at one time by a photolithography technique when they are manufactured. At this time, the thicknesses of the scan line 36 and the scan auxiliary lead 361 are the same. In addition, the line widths of the scan line 36 and the scan auxiliary lead line 361 may be the same or different, and the application does not limit this.

Alternatively, as a possible implementation, the cross section of the driving auxiliary lead 351 and the cross section of the scanning auxiliary lead 361 are uniform rectangular cross sections and have the same size.

It is to be understood that when the cross section of the driving auxiliary lead line 351 and the cross section of the scanning auxiliary lead line 361 are both rectangular cross sections and the sizes are the same, it is explained that the thicknesses of the driving auxiliary lead line 351 and the scanning auxiliary lead line 361 are the same (i.e., the width of the rectangular cross section) and the line widths are the same (i.e., the length of the rectangular cross section).

Of course, the cross section of the driving auxiliary lead 351 and the cross section of the scanning auxiliary lead 361 may also be in other shapes such as a right trapezoid, an isosceles trapezoid, and the like, and in addition, the sizes of the cross section of the driving auxiliary lead 351 and the cross section of the scanning auxiliary lead 361 may also be different, and specifically, the driving auxiliary lead and the scanning auxiliary lead may be set and changed as needed, which is not limited in this embodiment of the present application.

As shown in fig. 6 and 7, the left end of the driving lead 352 is connected to the scanning driving circuit 40, the right end is connected to the corresponding driving auxiliary lead 351, the scanning auxiliary lead 361 in the same connection region 34 is connected to the driving auxiliary lead 351 through the conductive layer 380, the lower end of the scanning auxiliary lead 361 is connected to the left end of the scanning line 36, and the scanning line 36 is further connected to the corresponding row of sub-pixel units 100. Based on the connection relationship, when the scan driving circuit 40 sends a scan signal, the scan signal is transmitted to the driving auxiliary lead 351 through the driving lead 352, passes through the conductive layer 380, is transmitted to the scanning auxiliary lead 361, is transmitted to the scan line 36, and is transmitted to the plurality of sub-pixel units 100 in the corresponding row through the scan line 36.

Here, since each scan line 36 is located between two adjacent rows of sub-pixel regions 33, and each scan line 36 is connected to a plurality of sub-pixel units 100 corresponding to the upper adjacent row of sub-pixel regions 33, the scan signal can be transmitted to all sub-pixel units 100 in the corresponding row through the scan line 36.

Alternatively, as shown in (a) of fig. 7, when the driving auxiliary lead line 351 and the scanning auxiliary lead line 361 are located at adjacent layers, a projection of the driving auxiliary lead line and a projection of the scanning auxiliary lead line 361 are not adjacent in the thickness direction of the array substrate 300.

To avoid the short-circuit problem, the driving auxiliary lead line 351 and the scanning auxiliary lead line 361 cannot be in direct contact, and therefore, when the driving auxiliary lead line 351 and the scanning auxiliary lead line 361 are located in adjacent layers, as shown in (a) of fig. 9, the projections of the driving auxiliary lead line 351 and the scanning auxiliary lead line 361 are not adjacent, that is, the driving auxiliary lead line 351 and the scanning auxiliary lead line 361 are separated, cannot overlap, and cannot be edge-adjacent.

Alternatively, as shown in (b) of fig. 7, when the driving auxiliary lead line 351 and the scanning auxiliary lead line 361 are located at two non-adjacent layers, the projection of the driving auxiliary lead line 351 and the projection of the scanning auxiliary lead line 361 may or may not overlap in the thickness direction of the array substrate 300.

When the projection of the driving auxiliary lead line 351 and the scanning auxiliary lead line 361 are disposed at two non-adjacent layers, an insulating layer may be disposed between the driving auxiliary lead line 351 and the scanning auxiliary lead line 361 for isolation. Since the insulating layer is already provided between the driving auxiliary lead line 351 and the scanning auxiliary lead line 361, the projections of the driving auxiliary lead line 351 and the scanning auxiliary lead line 361 may or may not overlap, and at this time, the short-circuit problem is not caused.

Wherein the so-called non-overlapping comprises: as shown in (a) of fig. 9, the projection of the driving auxiliary lead 351 and the projection of the scanning auxiliary lead 361 are separated, and as shown in (b) of fig. 9, the projection of the driving auxiliary lead 351 and the projection of the scanning auxiliary lead 361 are adjacent.

The so-called overlap includes: as shown in (c) and (d) of fig. 9, the projection of the driving auxiliary lead 351 and the projection of the scanning auxiliary lead 361 overlap.

As shown in (b) of fig. 7, when the driving auxiliary lead 351 and the scan line 36 are located at two non-adjacent layers, and the projection of the driving auxiliary lead 351 and the projection of the scanning auxiliary lead 361 overlap, the projection of the second via 720 is located in a first non-overlapping region (the region indicated by F1 in fig. 7).

The first non-overlapping area is used to indicate a region where the projection of the scanning auxiliary lead 361 and the projection of the driving auxiliary lead 351 do not overlap in the projection of the scanning auxiliary lead 361.

It should be understood that, since the second via hole 720 is used for laying the conductive layer 380 to connect with the scanning auxiliary lead 361, when the projection of the driving auxiliary lead 351 overlaps with the projection of the scanning auxiliary lead 361, in order to avoid the influence on the driving auxiliary lead 351 when the second via hole 720 is opened, the second via hole 720 needs to be opened in a region where the projection of the scanning auxiliary lead 361 does not overlap with the projection of the driving auxiliary lead 351.

Alternatively, as a possible implementation manner, the scanning auxiliary wiring 361 is located on a side of the driving auxiliary wiring 351 away from the display region 31 in the row direction.

At this time, the scan auxiliary line 361 is located at the left side, the driving auxiliary line 351 is located at the right side, and a portion of the scan line 36 overlaps the driving auxiliary line 351, and the first via 710 cannot be disposed in the overlapping region. A part of the projection of the driving wire 352 also overlaps the scan auxiliary wire 361, and the second via 720 cannot be disposed in the overlapping region.

Alternatively, as another possible implementation, the driving auxiliary wiring 351 is located on a side of the scanning auxiliary wiring 361 away from the display region 31 in the row direction.

At this time, the projection of the driving wire 352 and the projection of the scanning auxiliary wire 361 do not overlap, and the length of the driving wire 352 is shortest, thereby saving material. The projection of the scanning line 36 and the projection of the driving auxiliary lead 351 do not overlap, and the installation length of the scanning line 36 is the shortest, which can save materials. Meanwhile, the first via hole 710 and the second via hole 720 are more conveniently formed.

Alternatively, fig. 10 is a partial schematic top view of another array substrate provided in this embodiment of the present application, and fig. 10 includes a connection region 34 and a sub-pixel region 33. Fig. 11 is a schematic sectional view of the connection region 34 in fig. 10 in the cc' direction.

As shown in fig. 10 and 11 (a), in a case where the driving auxiliary lead 351 and the scanning auxiliary lead 361 are located at two non-adjacent layers and the projection of the driving auxiliary lead 351 and the projection of the scanning auxiliary lead 361 overlap in the thickness direction of the array substrate 300, the driving auxiliary lead 351 includes a plurality of first connector portions 3510, the scanning auxiliary lead 361 includes a plurality of second connector portions, and the number of the first connector portions 3510 is the same as the number of the second connector portions 3610.

It is to be understood that, since the lengths of the driving auxiliary lead 351 and the scanning auxiliary lead 361 in the column direction are the same, when the numbers of the first and

second connector portions

3510 and 3610 are the same, it is explained that the lengths of the first and

second connector portions

3510 and 3610 in the column direction are the same.

Of course, as shown in fig. 11 (b), when the driving auxiliary lead 351 and the scanning auxiliary lead 361 are located at two non-adjacent layers and the projection of the driving auxiliary lead 351 and the projection of the scanning auxiliary lead 361 are adjacent to each other in the thickness direction of the array substrate 300, the driving auxiliary lead 351 may include a plurality of first connector portions 3510 and the scanning auxiliary lead 361 may include a plurality of second connector portions 3610. The number of the first connector portions 3510 is the same as that of the second connector portions 3610.

Based on this, the plurality of first connector portions 3510 located in the odd-numbered rows and the plurality of second connector portions 3610 located in the even-numbered rows form the same column, and the plurality of first connector portions 3510 located in the even-numbered rows and the plurality of second connector portions 3610 located in the odd-numbered rows form the same column. The opposing cross sections of two adjacent first connector portions 3510 overlap, and the opposing cross sections of two adjacent second connector portions 3610 overlap.

It should be understood that the driving auxiliary lead 351 includes a plurality of first connector parts 3510, and although the first connector parts 3510 positioned in the odd-numbered rows and the first connector parts 3510 positioned in the even-numbered rows are divided into two columns, since the plurality of first connector parts 3510 need to perform a function of transmitting signals, the plurality of first connector parts need to be connected, and thus, when two opposite cross sections overlap for adjacent two first connector parts, the adjacent two first connector parts can be connected. In addition, the connection can also be achieved when, for two adjacent first connector portions, the two opposing cross sections coincide at the edge closest in the row direction.

Similarly, the scan auxiliary lead 361 includes a plurality of second connecting sub-portions 3610, and although the second connecting sub-portions 3610 located in the odd-numbered rows and the second connecting sub-portions 3610 located in the even-numbered rows are divided into two columns, since the plurality of second connecting sub-portions 3610 need to perform a function of transmitting signals, the plurality of second connecting sub-portions 3610 need to be connected, and then, when two opposite cross sections overlap for two adjacent second connecting sub-portions 3610, the two adjacent second connecting sub-portions 3610 can be connected. In addition, when two opposite cross sections overlap each other at the edge closest to the row direction, the two adjacent second connecting sub-portions 3610 can be connected to each other.

Fig. 12 is a schematic top view illustrating a driving auxiliary lead 351 and a scanning auxiliary lead 361 according to an embodiment of the present disclosure.

As shown in (a) and (b) of fig. 12, the opposing cross sections of adjacent two first connector portions overlap, and the opposing cross sections of adjacent two second connector portions 3610 overlap. Meanwhile, the plurality of first connector portions 3510 positioned in the odd-numbered rows and the plurality of second connector portions 3610 positioned in the even-numbered rows are aligned with the edge away from the display region, and the plurality of first connector portions 3510 positioned in the even-numbered rows and the edge of the plurality of first connector portions 3510 positioned in the even-numbered rows close to the display region are aligned with each other.

As shown in (c) and (d) of fig. 12, the opposing cross sections of the adjacent two first connector portions 3510 coincide with the closest edge in the row direction, and the opposing cross sections of the adjacent two second connector portions 3610 coincide with the closest edge in the row direction. Meanwhile, projections of the first and

second connector portions

3510 and 3610 of the same row are adjacent.

It should be understood that the above are only a few examples of the arrangement of the first and

second connector portions

3510 and 3610, and do not constitute a limitation on the first and

second connector portions

3510 and 3610.

Alternatively, as a possible implementation manner, as shown in fig. 12, the first vias 710 correspond to the first connector portions 3510 one to one, and the second vias 720 correspond to the second connector portions 3610 one to one.

It should be understood that the first vias 710 correspond to the first connector portions 3510 one-to-one, meaning that the number of the first vias 710 is the same as the number of the first connector portions 3510, and one first via 710 is disposed in a projection of each first connector portion 3510. Similarly, the one-to-one correspondence between the second vias 720 and the second connecting sub-portions 3610 means that the number of the second vias 720 is the same as that of the second connecting sub-portions 3610, and one second via 720 is disposed in a projection of each second connecting sub-portion 3610.

Of course, a plurality of first vias 710 may be disposed in the projection of each first connector portion 3510, a plurality of second vias 720 may be disposed in the projection of the second connector portion 3610, and the number of the vias 700 may be set and changed as needed, which is not limited in this embodiment of the application.

Alternatively, as shown in (a) and (b) of fig. 12, along the thickness direction of the array substrate 300, the projection of the first via 710 is located at the center of the first connector portion 3510, and the projection of the second via 720 is located at the center of the second non-overlapping region (the region indicated by F2 in fig. 12).

The second non-overlapping area is used to indicate an area where the projection of the second connector portion 3610 does not overlap with the projection of the first connector portion 3510 in the projection of the second connector portion 3610.

Alternatively, as shown in (c) and (d) of fig. 12, when the opposing cross sections of two adjacent first connector portions 3510 coincide at the nearest edge in the row direction, the projection of the first via 710 is located at the center of the first connector portion 3510 and the projection of the second via 720 is located at the center of the second connector portion 3610 in the thickness direction of the array substrate 300.

The embodiment of the present application further provides a liquid crystal display panel 3, including: the array substrate 300 and the opposite substrate 400 as described in the embodiments of the present application, and the liquid crystal layer disposed between the array substrate 300 and the opposite substrate 400.

The beneficial effects of the liquid crystal display panel provided by the embodiment of the application are the same as those of the array substrate, and are not repeated herein.

The embodiment of the present application further provides a liquid crystal display device 800, including: a liquid crystal display panel 3 and a driving device 810 for driving the liquid crystal display panel as described in the embodiments of the present application.

The beneficial effects of the liquid crystal display device provided by the embodiment of the application are the same as those of the array substrate, and are not repeated herein.

An embodiment of the present application further provides an electronic device, including: a liquid crystal display device as described in the embodiments of the present application.

The electronic device provided by the embodiment of the application has the same beneficial effects as the array substrate, and is not repeated herein.

The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present application and are intended to be included within the scope of the present application.

Claims

1. An array substrate, comprising a substrate base plate, the array substrate further comprising:

the driving auxiliary lead is used for being electrically connected with a scanning driving circuit, the scanning auxiliary lead is used for being electrically connected with a corresponding row of the sub-pixel units, the driving auxiliary lead is electrically connected with the scanning auxiliary lead, and the driving auxiliary lead transmits scanning signals sent by the scanning driving circuit to the corresponding sub-pixel units;

the connecting area is further provided with a plurality of pairs of through holes which are uniformly distributed along the column direction, each pair of through holes comprises a first through hole and a second through hole which are distributed along the row direction, and the pairs of the through holes are symmetrically distributed along the central line of the sub-pixel area along the row direction;

along the thickness direction of the array substrate, the first via hole is arranged on one side, away from the substrate, of the driving auxiliary lead, the projection of the first via hole is located in the projection of the driving auxiliary lead, the second via hole is arranged on one side, away from the substrate, of the scanning auxiliary lead, and the projection of the second via hole is located in the projection of the scanning auxiliary lead;

the driving auxiliary lead and the scanning auxiliary lead are electrically connected through the conducting layers laid in the first through hole and the second through hole.

2. The array substrate according to claim 1, wherein the peripheral region further comprises a plurality of driving leads extending along a row direction, the driving leads and the driving auxiliary leads are in one-to-one correspondence and are connected, the display region further comprises a plurality of scanning lines extending along the row direction, and the scanning lines and the scanning auxiliary leads are in one-to-one correspondence and are connected;

the driving lead is further electrically connected with the scanning driving circuit and used for receiving scanning signals sent by the scanning driving circuit and transmitting the scanning signals to the corresponding driving auxiliary lead, and the scanning lines are used for receiving the scanning signals sent by the scanning auxiliary lead and transmitting the scanning signals to the corresponding sub-pixel units.

3. The array substrate of claim 2, wherein when the driving auxiliary lead and the scanning auxiliary lead are located at adjacent layers, a projection of the driving auxiliary lead and a projection of the scanning auxiliary lead are not adjacent in a thickness direction of the array substrate.

4. The array substrate according to claim 2, wherein when the driving auxiliary lead and the scan line are located at two non-adjacent layers, a projection of the driving auxiliary lead and a projection of the scan auxiliary lead overlap in a thickness direction of the array substrate;

the projection of the second via hole is located in a first non-overlapping area, wherein the first non-overlapping area is used for indicating a region where the projection of the scanning auxiliary lead is not overlapped with the projection of the driving auxiliary lead in the projection of the scanning auxiliary lead.

5. The array substrate of claim 3 or 4, wherein the driving auxiliary lead is located on a side of the scanning auxiliary lead away from the display area along the row direction.

6. The array substrate of claim 4, wherein the driving auxiliary lead comprises a plurality of first connector portions, the scanning auxiliary lead comprises a plurality of second connector portions, and the number of the first connector portions is the same as that of the second connector portions;

7. The array substrate of claim 6, wherein the first vias and the first connector sub-portions are in one-to-one correspondence; the second via hole and the second connector sub-portion correspond to each other one to one.

8. A liquid crystal display panel comprising the array substrate and the opposite substrate according to any one of claims 1 to 7, and a liquid crystal layer disposed between the array substrate and the opposite substrate.

9. A liquid crystal display device, comprising: the liquid crystal display panel according to claim 8 and a driving device for driving the display panel.