JP3603887B2 - Active matrix substrate, active matrix liquid crystal display device using the same, and projection display device - Google Patents

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a technology for adjusting a time constant of a signal line in an electronic circuit, for example, a peripheral driving circuit for driving a pixel electrode having a thin film transistor (hereinafter, referred to as a TFT), or an active matrix liquid crystal display including the peripheral driving circuit. And a projection display device using the active matrix liquid crystal display device.
[0002]
[Prior art]
Conventionally, as an active matrix type liquid crystal display device, pixel electrodes are formed in a matrix on a glass substrate, and TFTs using amorphous silicon or polysilicon are formed corresponding to each pixel electrode, and each pixel electrode is formed. An active matrix type liquid crystal display device configured to drive a liquid crystal by applying a voltage by a TFT has been put to practical use. Among them, an active matrix type liquid crystal display device using a polysilicon TFT is a TFT for sampling an image signal inputted from the outside and transmitting the signal to a data line, and a shift register circuit for sequentially turning on and off the TFT. Since a complementary TFT (hereinafter referred to as a CMOS type TFT) constituting the peripheral driving circuit of FIG. 1 can be integrated and formed on the same substrate in the same process together with a TFT for driving a pixel, the TFT is widely used in recent years. It has become to.
[0003]
In addition, since the image signal supplied to the active matrix type liquid crystal display device is an analog signal, when the frequency band of the image signal is narrowed, when the sampling signal turns on the sample and hold circuit to supply the image signal to the data line. In some cases, sampling is performed in a portion where the image signal changes. In this case, since the image signal immediately before the sample-and-hold TFT constituting the sample-and-hold circuit is turned off is sampled, a higher voltage is used instead of an average voltage when the voltage of the image signal is increasing. In addition, when the voltage of the image signal changes in a decreasing direction, a lower voltage is sampled. Further, there is a disadvantage that the sampling voltage changes even if the timing of the sampling signal is slightly shifted.
[0004]
Therefore, for example, as shown in FIG. 14, the image signal is phase-expanded into a plurality of streams to expand the frequency band, and the image signal VID1 being sampled is synchronized with the timing of each sampling signal X1, X2,. To VID6 (for example, as shown by the dotted ellipse in FIG. 14 so that the average voltage of the image signal appears during the sampling period), and then the active matrix liquid crystal is processed. There is a technique for supplying a display device.
[0005]
In an active matrix type liquid crystal display device configured to be driven by a plurality of phase-developed image signals as described above, generally, as shown in FIG. 15, externally input from input terminals T1 to T6 as shown in FIG. The plurality of image signals VID1 to VID6 transmitted are transmitted to the image signal lines V1 to V6, and are supplied to the sample and hold circuit 16 switched by the data line driving circuit 15 via the relay wirings H1 to H6.
[0006]
[Problems to be solved by the invention]
However, the image signal lines V1 to V6 that supply the image signals VID1 to VID6 from the input terminals T1 to T6 to the sample and hold circuit 16 include sampling signal lines X1, X2,. Therefore, the same conductive film (for example, an aluminum film of a low-resistance metal or the like) cannot be formed from the input terminals T1 to T6 to the sample hold circuit 16. Therefore, conventionally, the image signals VID1 to VID6 are first transmitted to the vicinity of the sample-and-hold circuit 16 by the image signal lines V1 to V6 made of an aluminum film and being substantially parallel to each other and having substantially the same wiring width. In this case, the signal is transferred to the source electrode (or the drain electrode) of the sample and hold circuit 16 after being switched to the relay connection wirings H1 to H6 made of another conductive film (for example, a polysilicon film or the like). In this case, if the sample and hold circuits 16 are arranged in a line as shown in FIG. 16 according to a general layout method, the wiring lengths (distances from the contact holes 45 to 46) L of the relay wirings H1 to H6 differ. It becomes. In FIG. 16, the sampling signal lines X1, X2,..., Xn are formed of a polysilicon film of the same material as the relay wirings H1 to H6.
[0007]
However, when the relay wirings H1 to H6 are formed of a polysilicon film, the polysilicon film has a resistivity that is at least two orders of magnitude higher than the aluminum film. When the wiring film thickness is formed substantially constant, the wiring length L differs for each of the relay wirings H1 to H6, and thus the resistance between the relay wirings H1 to H6 differs. That is, the image signal sampled by the sample-and-hold circuit 16 has a different time constant for each of VID1 to VID6, which causes a problem that display unevenness of the active matrix type liquid crystal display device occurs. Therefore, the line width W is changed for each of the relay wirings H1 to H6. (If the distance from the image signal lines V1 to V6 to the sample hold circuit 16 is short, the line width W of the relay wirings H1 to H6 is reduced. If the length is long, the line width W is increased) to make the resistance value constant. However, in the method of changing the width of the wiring to make the resistance value constant (FIG. 16), the overlapping capacitance with other image signal lines cannot be made constant, and if the wiring width fluctuates due to process variation. The change in the resistance value with respect to the variation in the wiring width differs depending on the wiring width W. Since the smaller the wiring width W is, the more significantly affected by the process variation, it becomes clear that the variation in the time constant increases. Was.
[0008]
An object of the present invention is to reduce the variation in the resistance value and the capacitance value even when the wiring width W of a relay wiring for transmitting a signal from a plurality of signal wirings to a driving circuit is small, and to substantially reduce the time constant between the plurality of signal wirings. Can be uniform. Accordingly, an object of the present invention is to provide an active matrix type liquid crystal display device which can suppress display unevenness of the active matrix type liquid crystal display device and perform high quality display.
[0009]
[Means for Solving the Problems]
In order to achieve the above object, the present invention provides first and second image auxiliary input signal lines formed in parallel on a substrate, and first and second image auxiliary input signal lines arranged corresponding to a plurality of data lines. A second transistor made of polysilicon, which is connected to the first image auxiliary input signal line from a second transistor and a wiring on the source side of the first transistor via a first auxiliary relay wiring made of metal; A second relay line made of a metal having a length different from that of the first auxiliary relay line from a first relay line and a source-side line of the second transistor; A second relay wiring made of polysilicon connected to the input signal line, the first and second relay wirings have substantially the same wiring width, length, and film thickness, The first image auxiliary input signal line is 2 is located farther from the first and second transistors with respect to the second image auxiliary input signal line, and the tip of the first relay wiring is connected to the transistor in the wide first image auxiliary input signal line. A connection is made at a near edge, and a tip of the second relay wiring is connected at a far edge to the transistor in the wide second image auxiliary input signal line.
[0010]
Thereby, the resistance value of the relay wiring becomes substantially uniform. Therefore, by arranging the plurality of signal wirings almost in parallel with each other in a region intersecting with the relay wirings and making the wiring widths substantially equal, the overlapping capacity with other signal wirings becomes almost uniform, and the signal to be transmitted is Becomes substantially equal between the signal wiring paths. Further, since the length, width and film thickness of the relay wiring are almost equal, even if the wiring width deviates from the target value due to process variations, the variation in the resistance value and the capacitance value between the signal wiring paths becomes almost constant, and the time constant There is an advantage that display unevenness of the active matrix type liquid crystal display device due to the variation of the above can be suppressed.
Further, in the configuration of the present invention, the parasitic capacitance is formed at the first second image auxiliary input line at the intersection of the relay wiring and the image auxiliary input line, and the potential fluctuation of the relay wiring due to the parasitic capacitance. Is minimally affected. Further, in this configuration, the length of the relay wiring can be minimized, so that the resistance of the relay wiring can be reduced, and the area required for the wiring can be minimized, so that efficient design can be performed.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, preferred embodiments of the present invention will be described with reference to the drawings.
[0012]
(Reference Example 1)
FIG. 1 shows a configuration example of a substrate for an active matrix liquid crystal display device of an active matrix liquid crystal display device to which the present invention is applied. In FIG. 1, reference numeral 10 denotes a substrate such as a glass substrate or a quartz substrate which constitutes an active matrix type liquid crystal display device, 11 and 12 denote scanning lines and data lines arranged in directions crossing each other, and 13 denotes the scanning lines. Each pixel 13 is composed of a pixel electrode made of ITO or the like and a TFT for sequentially applying a voltage according to an image signal to this pixel electrode. The TFTs in the same row have their gate electrodes connected to the same scanning line 11 and their drain electrodes connected to the corresponding pixel electrodes. The source electrodes of the TFTs in the same column are connected to the same data line 12. In this embodiment, the TFT for driving the pixel is constituted by a so-called polysilicon TFT using a polysilicon film as a channel layer, and a peripheral driving circuit (the data line driving circuit 15, the scanning line driving circuits 14A and 14B, etc.) is used. It is formed on the same substrate by the same process together with the constituent CMOS type TFT.
[0013]
In this embodiment, scanning line driving circuits 14A and 14B including a Y shift register circuit and a buffer circuit for sequentially selecting and driving the scanning lines 11 are provided at both ends of the scanning lines 11, respectively. The scanning line driving circuits 14A and 14B apply the same voltage to each scanning line 11 at the same timing. That is, one scanning line 11 is simultaneously driven from both sides. As a result, it is possible to reduce a voltage level drop and a signal delay due to the parasitic resistance of the scanning line 11.
[0014]
On the other hand, in the present embodiment, a data line driving circuit 15 including an X shift register circuit, a buffer circuit, and the like for selectively driving the data line 12 is provided. Further, circuits 16 and 17 for sampling an image signal are provided at both ends of the data line 12. Of these, 17 is a precharge circuit for applying a precharge level to each data line 12, and the other 16 is a sample and hold circuit for applying a voltage according to an image signal to each data line 12. The sample hold circuit 16 and the precharge circuit 17 belong to any of the three types shown in FIG. 20 in a basic equivalent circuit diagram. In other words, the sample-hold TFT 160 and the precharge TFT 170 take one of the following forms: (A) an N-channel TFT, (B) a P-channel TFT, and (C) a CMOS TFT. FIG. 20 shows that the sampling signal SB of the P-channel TFT is an inverted signal of the sampling signal S with respect to the sampling signal S of the N-channel TFT. Externally supplied image auxiliary input signals NRS1 and NRS2 are applied to the source of the precharge circuit 17 (electrodes opposite to the connection electrodes on the data line 12 side) to the data lines 12 every other line. The signal is supplied to the precharge circuit 17 by the input signal lines 19A and 19B, and a timing signal NRG supplied from the outside is commonly applied to the gate electrode of the precharge circuit 17 via the signal wiring 18. As a result, all the data lines 12 are simultaneously precharged to the levels of the image auxiliary input signals NRS1 and NRS2 before the application of the image signal level from the sample hold circuit 16 during one horizontal blanking period. Further, when performing driving to change the polarity of the image signal for each adjacent data line 12, it is effective to make the image auxiliary input signals NRS1 and NRS2 have polarities opposite to each other.
[0015]
To the source electrode of the sample-and-hold circuit 16 provided at the other end of each data line 12, phase-developed image signals VID1 to VID6 supplied from the outside are input via the image signal line group 20, and the sample-and-hold circuit A sampling signal output from a data line driving circuit 15 including a shift register circuit, a buffer circuit, and the like for sequentially selecting the data lines 12 is applied to the 16 gate electrodes. In the present embodiment, the image signal is developed into six phases. However, if the writing characteristic of the sample-and-hold TFT 160 is high, the number of phase developments can be reduced. If the writing characteristic is low, the number of phase developments can be increased. Is also good. Needless to say, RGB parallel signals corresponding to NTSC signals and PAL signals may be used. The data line drive circuit 15 sequentially selects all the data lines 12 once during one horizontal scanning period based on a start signal SPX supplied from the outside and eight clock signals CLX1 to CLX4 to CLXB1 to CLXB4. Such sampling signals X1, X2, X3,... Xn are formed and supplied to the gate electrode of the sample hold circuit 16. The clock signals CLX1 to CLX4 (or their opposite-phase clock signals CLXB1 to CLX4) are clock signals of the same cycle, the phases of which are sequentially shifted by 45 ° from each other. Incidentally, the inverted phase clock signals CLXB1 to CLXB4 can be generated inside the active matrix type liquid crystal display device substrate by a signal generation circuit provided in the peripheral driving circuit based on the clock signals CLX1 to CLX4 input from the outside. It is.
[0016]
Although not particularly limited, in this embodiment, as shown in FIG. 8, the data line drive circuit 15 is configured by four systems of shift register circuits, and each system of shift register circuits has an opposite phase of one. It is operated by a pair of clock signals CLXi and CLXBi, and is configured to supply a timing signal for selecting a signal wiring every fourth line. Since there are eight clock signals, the driving frequencies of the clock signals CLX1 to CLX4 and CLXB1 to CLXB4 input from the outside can be reduced, and the load of the peripheral driving circuit of the active matrix type liquid crystal display device can be reduced. Is reduced.
[0017]
Further, in the present embodiment, the method of sequentially driving the data lines 12 line by line at a fixed timing has been described, but a number of adjacent data lines 12 such as three lines, six lines, and twelve lines are connected to one line. The present embodiment can also be used in a method of simultaneously selecting with a data sampling signal and changing the timing of an image signal input from the outside.
[0018]
Further, in this embodiment, the peripheral driving circuit including the data line driving circuit 15 and the scanning line driving circuits 14A and 14B, the plurality of data lines 12 connected to the data line driving circuit 15 and the scanning line driving circuits 14A and 14B are provided. An active matrix type in which connected scanning lines 11 are crossed in a matrix, and a pixel transistor connected to the data line 12 and the scanning line 11 and a pixel electrode connected to the pixel transistor are formed on the same substrate. Although the liquid crystal display device has been described, a portion of the peripheral driving circuit is formed by a high-temperature polysilicon TFT on an expensive substrate such as a quartz substrate, and a region 130 including the data line 12, the scanning line 11, and the pixel 13 (dotted line in FIG. 1) ) Formed on an inexpensive substrate such as a glass substrate using amorphous silicon TFTs or low-temperature polysilicon TFTs with a process temperature of 600 ° C or less. It is also possible that by connecting these substrates constituting the substrate for an active matrix type liquid crystal display device.
[0019]
FIG. 2 shows an embodiment in which the present invention is applied to a connection portion between the image signal line group 20 and the sample hold circuit 16, wherein V1 to V6 are input from external input terminals and the phase-expanded image is displayed. This is an image signal line as a signal line for transmitting the signals VID1 to VID6. These image signal lines V1 to V6 are formed of a low-resistance aluminum film made of the same material as the data line 12, although not particularly limited. . , Xn are wirings for supplying a sampling signal output from the data line driving circuit 15 to the gate electrode of the sample hold circuit 16, and the sampling signal lines X1, X2, ..., Xn are It is provided in a direction crossing the image signal lines V1 to V6, is made of a polysilicon film of the same material as the scanning lines, and is formed so as to be continuous with the gate electrode of the sample hold circuit 16.
[0020]
Reference numerals 41 and 42 denote source / drain regions of the sample / hold TFT 160 constituting the sample / hold circuit 16 formed of a polysilicon film provided on both sides of the sampling signal lines X1, X2,. Lead lines S1 to S6 as auxiliary relay wiring made of a low-resistance aluminum film or the like are connected to the source region 41 through contact holes 43. The data line 12 connected to the pixel driving TFT is connected to the drain region 42 of each sample hold circuit 16 through a contact hole 44. In this embodiment, although not particularly limited, the data lines 12, the auxiliary relay wirings S1 to S6, and the image signal lines V1 to V6 are made of an aluminum film formed by the same process.
[0021]
Further, in this embodiment, between the image signal line V1 and the auxiliary relay wiring S1, the image signal lines V2 to V6 are interposed between the image signal lines V1 to V6 via an interlayer insulating film in a direction crossing the image signal lines V1 to V6. In another layer, a relay wiring H1 made of a conductive film such as a polysilicon film in the same layer as the scanning line 11 is provided. At the wiring end, the relay wiring H1 is connected to the image signal line V1 by a contact hole 45, and is connected to the auxiliary relay wiring S1 by a contact hole. Similarly, between the other image signal lines V2 to V6 and the auxiliary relay lines S2 to S6 corresponding to the image signal lines V2 to V6 are connected to the relay lines H2 to H6 at the contact holes 45 and 46, respectively. You. The image signals VID1 to VID6 are transmitted to the source electrodes of the sample and hold TFTs 160 constituting the sample and hold circuit 16 via the relay wires H1 to H6. The relay wirings H1 to H6 are all designed so that their line width W and length (the distance from the contact holes 45 to 46) L and the wiring film thickness are substantially equal, and the relay wiring H1 The signal path between H6 and the sample hold circuit 16 is configured to absorb the difference in length by extending the auxiliary relay wirings S1-S6. The image signal lines V1 to V6 are arranged at least substantially in parallel with each other in a region intersecting with the relay wirings H1 to H6, and the image signal lines V1 to V6 are designed to have substantially the same line width.
[0022]
When the relay wirings H1 to H6 are formed of a polysilicon film forming a gate electrode of a TFT and the auxiliary relay wirings S1 to S6 are formed of an aluminum film, the resistivity of the aluminum film is higher than that of the polysilicon film. Since it is smaller by about two digits, the difference in resistance value due to the difference in length of the auxiliary relay wirings S1 to S6 can be extremely small. Further, since the overlapping area with the other image signal lines becomes equal, the overlapping capacitance becomes uniform, and the capacitance of each image signal line is also made uniform. Therefore, the time constant for the transmitted image signal becomes equal between the signal paths, the line widths of the image signal lines V1 to V6 are substantially equal to each other, and the line width W between the relay wirings H1 to H6 is also substantially equal to each other. In addition, even if the line width deviates from the design target value due to the process variation, the variation of the capacitance value and the resistance value between the image signals becomes substantially the same, and the display unevenness due to the variation of the time constant can be suppressed.
[0023]
It is most efficient to set the length L of the relay wirings H1 to H6 within the line width L1 + 30 μm of the signal wiring group 20 (image signal lines V1 to V6). The length L of the relay wirings H1 to H6 having a high resistance value is the shortest, the wiring resistance is reduced, and the occupied area can be reduced. Therefore, an efficient design for finely integrating the peripheral drive circuit region can be performed.
[0024]
In the present embodiment, the data lines 12 and the auxiliary relay wirings S1 to S6 and the image signal lines V1 to V6 are formed by aluminum films formed by the same process. However, a metal film such as Cr or Ta or a metal silicide film is used. It is also possible to use a different conductive film. In addition, if the relay wirings H1 to H6 are formed of not only a polysilicon film but also a metal film such as Mo, Ta, W, or Cr, or a metal silicide film such as Mo-Si or W-Si, the resistance can be reduced. And the effect is further improved in making the time constant between the wirings uniform.
[0025]
FIG. 3 shows a modification of the first embodiment. In this modification, the contact holes 43 to the source region 41 and the contact holes 44 to the drain region 42 of the sample and hold TFT 160 constituting the sample and hold circuit 16 are alternately arranged, and the sampling signal lines X1, X2, .., Xn are obtained by meandering the gate electrode portion of the sample hold TFT 160 so as to avoid the contact holes 43 and 44. If the opening of the contact hole is too small, the size of the contact hole is limited due to factors such as an increase in contact resistance, and cannot be made larger than the minimum width of the connection wiring. Therefore, by forming the gate electrode of the sample-hold TFT 160 in a meandering pattern as described above, the pitch L2 between the adjacent sample-hold circuits 16 can be reduced, and when the pixel pitch is reduced due to high integration. The sample and hold circuit 16 can be formed accordingly.
[0026]
FIG. 4 shows still another modification of the first embodiment. In this modification, the area occupied by the sample and hold circuit 16 can be reduced. That is, the ends of the sampling signal wirings X1, X2,..., Xn for controlling the gate electrode of the sample-holding TFT 160 are bifurcated, and the data line 12 is connected to the drain region 42 formed bifurcated outside. It is configured. Since the pitch L3 between the adjacent data lines 12 is determined depending on the pitch per one pixel arranged, not shown, etc., the pitch L3 between the adjacent data lines 12 is a sample-and-hold that forms one sample-and-hold circuit 16. In the case where the width is larger than the width of the source / drain region of the TFT 160, the sample-hold TFT 160 is configured such that transistors are formed on both sides of the source region 41 as shown in FIG. This makes it possible to effectively use the horizontal pitch L3 of the sample and hold circuit 16 to reduce useless space and reduce the occupied area as a whole. Also, compared to the sampling signal wirings X1, X2,..., Xn in FIG. 2, when the channel width L4 of the sample-and-hold TFT 160 is designed to be the same length, about twice the drain current characteristic can be obtained. Needless to say, the source region 41 may be formed in two branches, and the drain region 42 may be formed in a single part.
[0027]
FIG. 5 shows still another modification of the first embodiment. In this modified example, the length L4 of the auxiliary relay wirings S1 to S6 is the same as that of the relay wirings H1 to H6 by making the distances from the image signal lines V1 to V6 to the sample hold circuit 16 substantially the same. They are almost identical to each other. With this configuration, it is possible to further reduce the variation of the time constant for each image signal. In FIG. 5, the sample-and-hold circuit 16 is shown with the gate electrode formed in two branches, but it is also possible to form a single gate electrode as in FIG.
[0028]
Also, in the embodiment shown in FIGS. 2 to 5, the sample-and-hold TFT 160 constituted by a one-channel type TFT is shown, but the sample-and-hold TFT 160 may be an N-channel type TFT (FIG. 20A). It goes without saying that a channel type TFT (FIG. 20B) may be used.
[0029]
FIG. 6 shows still another modification of the above embodiment. In this modification, the sample-hold TFT 160 is formed of a CMOS TFT (a P-channel TFT 42P and an N-channel TFT 42N are provided in parallel; FIG. 20C). In order to turn on the P-channel TFT 42P and the N-channel TFT 42N at the same time, it is necessary to apply simultaneously the sampling signal transmitted to the gate electrode of the P-channel TFT 42P and the sampling signal of the opposite phase to the gate electrode of the N-channel TFT 42N. . Therefore, the sampling signal wirings X1, X2,..., Xn including the gate electrodes connected to the data line driving circuit 15 are divided into two systems, and the P-channel TFT sampling signal wirings X1P, , XnP, and N-channel TFT sampling signal wirings X1N, X2N,..., XnN on the gate electrode of the N-channel TFT 42N across the relay wirings H1 to H6 and the auxiliary relay wirings S1 to S6. They are connected and arranged substantially parallel to each other. With this configuration, it is possible to prevent the level of the image signal from decreasing by the threshold value of the TFT. Further, the push-down of the sample hold TFT 160 can be suppressed.
[0030]
In the above embodiment, the case where the present invention is applied to a portion for transmitting the phase-expanded image signals VID1 to VID6 from the image signal lines V1 to V6 to the sample and hold circuit 16 has been described. The transmission path includes not only an image signal line for transmitting an image signal, but also a precharge circuit 17 for applying a precharge level to each data line 12 and a clock signal for transmitting a clock signal input from the outside to the shift register circuit. The present invention can be applied to a transmission portion between a wiring and a shift register circuit.
[0031]
(Optimal embodiment)
Next, an optimal embodiment to which the present invention is applied will be described. FIG. 7 shows image pre-charge circuits 17 and image auxiliary input signal lines 19A and 19B for supplying external image auxiliary input signals NRS1 and NRS2 (see FIG. 1) to a pre-charge circuit 17 for applying a pre-charge level to each signal line 12. An example in the case where the present invention is applied between the steps will be described. In this embodiment, the image auxiliary input signal lines 19A and 19B for supplying the image auxiliary input signals NRS1 and NRS2 are not particularly limited, but are made of a metal film such as a low-resistance aluminum film, and are wired substantially parallel to each other. The widths are substantially equal to each other, and are formed widely, so that the wiring resistance is reduced. The relay wirings H1 and H2 alternately connected to these image auxiliary input signal lines 19A and 19B are closer to the precharge TFT 170 for the image auxiliary input signal line 19B farther from the precharge TFT 170. In the contact hole 49B formed in the edge on the side, and the contact hole 49A formed in the edge on the side far from the TFT 15A for the image auxiliary input signal line 19A on the side near the precharge TFT 170, respectively. By being connected, they are configured to have the same length, that is, the same time constant. Thereby, the wiring length (the distance from the contact holes 49A to 50A or the distance from the contact holes 49B to 50B) L, the width W, and the film thickness of the relay wirings H1 and H2 are made substantially constant. It is possible to make the resistance and the overlap capacitance substantially uniform. That is, the time constant can be made uniform. Further, if the contact holes 49A and 49B for connecting the image auxiliary input signal lines 19A and 19B and the relay wirings H1 and H2 are formed as shown in FIG. 7, the length of the wiring area L6 can be designed to be minimum. Area can be omitted, and efficient design can be performed. Although not particularly limited, this is an effective means when the relay wiring is drawn out from two signal lines having opposite signal polarities.
[0032]
Also in this embodiment, the relay wirings H1 and H2 are formed of the same polysilicon film as the polysilicon wiring 180 extending from the gate electrode of the precharge TFT 170 and transmitting the signal NRG for controlling the gate electrode. The other ends of the wirings H1 and H2 are connected to the source region (or the drain region) of the precharge TFT 170 via the auxiliary relay wirings S1 and S2 made of an aluminum film. The precharge TFT 170 is a single-channel TFT (N-channel TFT or P-channel TFT; see FIG. 20) having a straight gate electrode, but is not limited thereto. A bifurcated or CMOS type TFT (FIG. 20C) may be used. When a CMOS TFT is used as the precharge TFT 170, a precharge circuit drive signal NRG and its inverted signal are required, so that at least two precharge circuit drive signal lines are required. In this case, it is needless to say that the relay wiring of the present invention can be applied. The polysilicon wiring 180 is connected to a precharge circuit drive signal line 18 made of an aluminum film, and a common signal NRG is applied.
[0033]
(Reference Example 2)
FIG. 8 shows the relationship between the X shift register circuit 150 constituting the data line driving circuit 15 in FIG. 1 and the signal lines for transmitting the clock signals CLX1 to CLX4 and the inverted phase clock signals CLXB1 to CLXB4.
[0034]
In the present embodiment, an example is shown in which the X shift register circuit 150 formed in the data line driving circuit is constituted by the clocked inverters 200 and 201, but a transmission gate or the like may be used. The clock signals CLX1 to CLX4 are divided into four systems, and any one of the eight-phase clock signals whose phases are shifted by 45 ° from each other by combining the inverted clock signals CLXB1 to CLXB4 of the clock signals CLX1 to CLX4 is connected to the relay wiring 91 to The drive is performed by being transmitted to the gate electrode of the clocked inverter of the X shift register circuit 150 through 98. Therefore, the configuration from the clock signal lines CLX1 to CLX4 and CLXB1 to CLXB4 to the relay wirings 91 to 98 includes the relay used in the signal path from the image signal lines V1 to V6 to the sample hold circuit 16 shown in FIG. The same configuration as the wirings H1 to H6 and the auxiliary relay wirings S1 to S6 is applied. That is, by connecting the clock signal line to the X shift register circuit 150, the time constant difference between the clock signal series of the X shift register circuit 150 is eliminated, and the display unevenness in the active matrix type liquid crystal display device can be suppressed. Become.
[0035]
Further, in the present embodiment, it goes without saying that the present invention can be applied not only to the X shift register circuit 150 but also to the Y shift register circuit forming the scanning line driving circuits 14A and 14B in FIG. That is, if the relay wiring and the auxiliary relay wiring of the present invention are used for the relay wiring between the clock signal line transmitting the clock signal CLY and the inverted phase clock signal CLYB and the Y shift register circuit, The delay difference between the scanning lines 11 in every other row caused by the delay difference between the clock signal CLY and the negative-phase clock signal can be suppressed, and a high-quality active matrix liquid crystal display device can be provided.
[0036]
(Reference Example 3)
FIG. 18 shows still another embodiment of the present invention. This is achieved, for example, by connecting signals N1, N3, N5,... Transmitted to the odd-numbered stages sequentially transmitted from the shift register circuit to one terminal of the two-terminal NAND circuit 202 and being externally input to the other terminal. Is connected to the enable signal ENB1. Similarly, the signals N2, N4, N6,... Transmitted to the even-numbered stages are connected to one terminal of the two-terminal NAND circuit 203, and the other terminal is connected to an enable signal ENB2 input from the outside. With such a circuit configuration, as shown in the timing chart of FIG. 19, the sampling signals X1, X2,..., Xn between adjacent sample signal lines may be overlapped (A) or separated (B). You can do it freely. Therefore, the relay wiring 81 relayed from the enable signal line ENB1 to the NAND circuit 202 and the relay wiring 82 relayed from the enable signal line ENB2 to the NAND circuit 203 in the third embodiment are shown in FIG. The relationship between the relay wirings H1 to H6 and the auxiliary relay wirings S1 to S6 used for connecting the signal lines V1 to V6 and the sample hold circuit TFT 160 may be applied. This eliminates the signal delay difference between the enable signals ENB1 and ENB2 in the active matrix type liquid crystal display device substrate, and provides a high quality active matrix type liquid crystal display device.
[0037]
The circuits controlled by these enable signals ENB1 and ENB2 are not only two-terminal NAND circuits 202 and 203 but also three-terminal or more NAND circuits, and further combine a plurality of enable signals and control signals generated inside the peripheral driving circuit. However, a complicated circuit configuration is also possible. Further, a NOR circuit or the like may be used instead of the NAND circuit.
[0038]
The present invention can be applied to all cases where a driving circuit having at least two or more signal wirings and controlled by signals transmitted to the signal wirings is configured.
[0039]
(Description of manufacturing process)
9 to 11 show a manufacturing process of the pixel 13 and the image signal line portion in the order of steps. 9 to 11 are cross-sectional views taken along the line AA ′ of the pixel plan view shown in FIG. 17, and the image signal lines are cross-sectional views taken along the line BB ′ of the plan view of FIG. Is shown.
[0040]
First, in a step (1), a polysilicon film is deposited on a substrate 10 such as a glass substrate or a quartz substrate by a low pressure CVD method or the like so as to have a thickness of 500 to 2,000 angstroms, preferably about 1000 angstroms. The semiconductor layer 1 is formed. The semiconductor layer 1 may be formed by depositing an amorphous silicon film and then performing annealing at 600 to 700 ° C. for 1 to 8 hours to form a polysilicon film, or after depositing the polysilicon film, A polysilicon film may be formed by implanting silicon into an amorphous state and recrystallizing by annealing.
[0041]
In the step (2), the semiconductor layer 1 is patterned by a photolithography step, an etching step, and the like to form a layer 1a including an island-shaped channel in the pixel TFT portion.
[0042]
In the step (3), the surface of the polysilicon film (1a) of the pixel TFT portion formed in the step (2) is thermally oxidized at a temperature of 900 to 1300 ° C., thereby forming a gate oxide film on the channel layer 1a. Form 2 Further, in order to prevent the substrate from warping or the like, a multi-layer gate insulating film may be formed by forming an HTO film, a SiN film, or the like after forming a thermal oxide film in a thickness of 200 to 500 angstroms. By this step, the layer 1a including the channel finally has a thickness of 300 to 1500 angstroms, preferably 350 to 450 angstroms, and the gate insulating film 2 has a thickness of about 600 to 1500 angstroms.
[0043]
In the step (4), a low-resistance polysilicon film 3 serving as a gate electrode and a scanning line is deposited on the gate insulating film 2 in the pixel TFT portion formed in the step (3) by a low-pressure CVD method or the like. I do.
[0044]
In the step (5), the polysilicon film 3 formed in the step (4) is patterned by a photolithography step and an etching step, and a gate electrode (scanning line) 11 is formed in the pixel TFT portion, and at the same time, an image signal is formed. In the line portion, the relay wiring H1 is formed of the same material as the gate electrode 11. As the material of the gate electrode 11 and the relay wiring H1, a high melting point metal such as Mo, Ta, Ti, W, or a metal silicide thereof can be used in addition to polysilicon.
[0045]
In the step (6), using the gate electrode 11 as a mask, an impurity (phosphorus) is ^Thirteen / Cm ² ~ 3 × 10 ^Thirteen / Cm ² To form low concentration regions 1d and 1e. Further, a resist film 100 is formed on the gate electrode with a mask layer wider than the width of the gate electrode 11, and the impurity (phosphorus) 101 is reduced to 1 × 10 ^Fifteen / Cm ² ~ 3 × 10 ^Fifteen / Cm ² To form an N-channel TFT. Similarly, in the case of forming a P-channel TFT, although not shown, the N-channel TFT region is covered and protected with a resist, and then an impurity (boron) is added to 1 × 10 4. ^Thirteen / Cm ² ~ 3 × 10 ^Thirteen / Cm ² To form low concentration regions 1d and 1e. Further, a mask layer wider than the width of the gate electrode 3a is formed on the gate electrode 3a, and impurities (boron) are reduced to 1 × 10 ^Fifteen / Cm ² ~ 3 × 10 ^Fifteen / Cm ² To form a P-channel TFT. As a result, the masked region has a lightly doped drain (LDD) structure, and a CMOS TFT including an N-channel TFT and a P-channel TFT is formed. Further, the 1d and 1e regions may be set in an offset state without light doping the impurity. In this embodiment, the pixel TFT is formed of an N-channel TFT, but it is needless to say that the pixel TFT may be formed of a P-channel TFT.
[0046]
In the step (7), the first interlayer insulating film 4 made of an NSG film (silicate glass film containing neither boron nor phosphorus) or the like is covered with, for example, normal pressure CVD so as to cover the gate electrode 11 and the relay wiring H1. It is deposited to a thickness of 5000 to 15000 angstroms at a temperature of 800 degrees by a method or the like. (FIG. 10)
In the step (8), a contact hole 5 is formed in the first interlayer insulating film 4 at a position corresponding to the source region in the pixel TFT portion by dry etching or the like, and in the image signal line portion, the contact hole 5 is formed in the relay wiring H1. Contact holes 45 and 46 for connection are opened. As a method of forming the contact holes 5, 45 and 46, it is advantageous to form an anisotropic contact hole by dry etching such as reactive ion etching or reactive ion beam etching in order to increase the definition of pixels. is there. When the dry etching and the wet etching are combined and the opening is formed in a tapered shape, there is an effect of preventing disconnection at the time of wiring connection.
[0047]
In the step (9), a low-resistance conductive film 6 is deposited on the substrate by a sputtering method using a metal film such as aluminum or an aluminum alloy or a metal silicide film. The low-resistance conductive film 6 is connected to the source region 1b via the contact hole 5 in the pixel TFT portion, and is connected to the relay wiring H1 via the contact holes 45 and 46 in the image signal line portion.
[0048]
In the step (10), the low-resistance conductive film 6 is patterned by a photolithography step and an etching step to form a data line 12 also serving as a source electrode so as to be connected to the source region 1b. The connected image signal line V1 and the auxiliary relay wiring 51 are formed. At this time, other image signal wirings V2 to V6 are simultaneously formed.
[0049]
In the step (11), a second interlayer insulating film such as a BPSG film (a silicate glass film containing boron and phosphorus) is formed so as to cover the data lines 12, the image signal lines V1 to V6, and the auxiliary relay wiring 51. The film 7 is formed to a thickness of 5000 to 15000 angstroms at a low temperature of, for example, 500 degrees by a plasma ozone TEOS method, a normal pressure ozone TEOS method, or the like. Alternatively, a flattening film having no step may be formed by applying an organic film or the like by spin coating. (FIG. 11)
In the step (12), the second interlayer insulating film 7 and the superposed film composed of the first interlayer insulating film 4 and the gate insulating film 2 under the second interlayer insulating film 7 are subjected to a photolithography step, an etching step, and the like to perform a pixel TFT portion. Contact hole 8 is formed at a position corresponding to the drain region of FIG. As a method of forming the contact hole 8, it is more advantageous to form an anisotropic contact hole by dry etching such as reactive ion etching or reactive ion beam etching in order to increase the definition of pixels. When the dry etching and the wet etching are combined and the opening is formed in a tapered shape, there is an effect of preventing disconnection at the time of wiring connection.
[0050]
In the step (13), in the pixel TFT portion, an ITO film 9 serving as a pixel electrode 9a is formed on the second interlayer insulating film 7 by sputtering to a thickness of, for example, 1500 angstroms. At this time, in the TFT section, the ITO film 9 is connected to the high-concentration drain region 1c through the contact hole 8.
[0051]
In the step (14), a pixel electrode 9a is formed on the ITO film 9 by a photolithography step and an etching step in the pixel TFT portion.
[0052]
Then, an alignment film made of polyimide or the like is formed on the pixel electrode 9 and the second interlayer insulating film 7 so as to have a thickness of about 200 to 1000 angstroms, and rubbing (alignment treatment) is performed. It becomes a liquid crystal display substrate. In the case of a reflection type active matrix type liquid crystal display device, a film having high reflectance such as aluminum may be formed as the pixel electrode 9a.
[0053]
Although not particularly limited, in the present embodiment, as shown in FIG. 17, the drain region 1c is extended in order to add a capacitance attributed to the drain region 1c of the pixel TFT, and an upper portion thereof is formed by a gate insulating film. A capacitor line 3a to which a constant potential is always supplied via the capacitor 2 is arranged. The capacitance line 3a is formed of the same material and in the same process as the scanning line 11. In addition, since the disclination generating portion of the liquid crystal which is conventionally affected by the horizontal electric field or the like of the pixel electrode 9a or the like causes the deterioration of the screen display quality, the dead space which is shielded by the black matrix on the counter substrate is used. However, by arranging the capacitor line 3a in the disclination generation region, a high-quality active matrix liquid crystal display device that does not cause flicker or the like without deteriorating the aperture area through which the light of the pixel passes is realized. Can be provided.
[0054]
As described above, the relay wirings H1 to H6 made of a polysilicon film in the embodiment of FIGS. 2 to 8 are formed simultaneously with the polysilicon film 11 serving as a gate electrode in the TFT portion. Further, the image signal lines V1 to V6, the image auxiliary input signal lines 19A and 19B, the clock signal lines CLX1 to CLX4, CLXB1 to CLXB4, and the auxiliary relay wirings S1 to S6 in the embodiment of FIGS. Are formed at the same time as the aluminum film serving as the data line 12 in the TFT portion. Needless to say, the other signal wires, the respective relay wires and the auxiliary relay wires can be formed in the same process. As a result, the embodiment shown in FIGS. 2 to 8 can be realized without changing any process.
[0055]
(Description of active matrix type liquid crystal display device)
FIG. 12A is a plan view of an active matrix liquid crystal display device manufactured in this embodiment. FIG. 12B is a cross-sectional view of the active matrix liquid crystal display device taken along line YY ′ in FIG. As shown in FIG. 15, the data line driving circuit 15 and the scanning line driving circuits 14A and 14B on the active matrix type liquid crystal display substrate 10 prevent deterioration of the alignment film such as polyimide or the liquid crystal due to the DC component of the electric charge. In order to move the counter substrate 110, the counter substrate 110 is disposed outside the outer periphery. Further, the surface of the pixel electrode formed on the substrate for the active matrix type liquid crystal display device is formed of a transparent conductive film such as an ITO film capable of applying a transparent counter electrode potential on a transparent substrate such as glass, neoceram or quartz. Opposite substrates 110 having electrodes 111 are disposed at appropriate intervals, and as shown in FIG. 7, the data lines 12 and the scanning lines between the pixels 13 and the data line driving circuit 15 and the scanning line driving circuits 14A and 14B. Sealing is performed on the line 11 with the sealing material 112. Further, on the outer side of the screen display area, a peripheral partition is formed on the opposite substrate 31 in the same layer as the black matrix 113 so that light does not leak when assembled as a module. Reference numeral 114 denotes an upper and lower substrate conduction terminal 115 for supplying a common electrode potential LCCOM (see FIG. 1) from the active matrix type liquid crystal display device side to the opposite electrode 111 provided on the opposite substrate 110 side. It is configured such that a conductive adhesive having a predetermined diameter is interposed on the substrate conduction terminal 115 so as to establish conduction with the counter substrate. Further, the external input / output terminal 116 is disposed outside the counter substrate 110 and is connected to an external IC by wire bonding, ACF (anisotropic conductive film) crimping, or the like.
[0056]
As shown in FIG. 12B, a liquid crystal 117 such as a well-known TN (Twisted Nematic) liquid crystal is filled in a space surrounded by a sealant 112, and a liquid crystal sealing hole is filled with a sealant 118. By sealing, an active matrix liquid crystal display device is formed. In addition, if a polymer dispersed liquid crystal in which liquid crystal is dispersed as fine particles in a polymer is used, an alignment film and a polarizing plate are not required, so that light use efficiency is increased and a bright active matrix liquid crystal display device is provided. it can. Further, in the case of a reflection type liquid crystal display device using a non-transmissive metal film such as an aluminum film or the like for a pixel electrode from an ITO film and having a high reflectance, SH (Super) in which liquid crystal molecules are almost vertically aligned in a state where no voltage is applied. (Homeotropic) type liquid crystal may be used. Needless to say, other liquid crystals may be used.
[0057]
(Description of projection display device)
FIG. 13 shows a configuration example of a data projector as an example of a projection display device in which the active matrix liquid crystal display device having the above configuration is applied as a light valve.
[0058]
In FIG. 13, 370 is a light source such as a halogen lamp, 371 is a parabolic mirror, 372 is a heat ray cut filter, 373, 375 and 376 are dichroic mirrors of blue reflection, green reflection and red reflection, 374 and 377 are reflection mirrors, respectively. Reference numerals 378, 379, and 380 denote light valves composed of the active matrix liquid crystal display device of the above embodiment, 383 denotes a dichroic prism, and 385 denotes a control device. An image signal, a clock signal, and various control signals supplied from the outside to the substrate for the active matrix type liquid crystal display device shown in FIG. 1 are formed by the control device 385.
[0059]
In the data projector of this embodiment, the white light emitted from the light source 370 is condensed by the parabolic mirror 371 and passes through the heat ray cut filter 372 to block the heat rays in the infrared region, so that only visible light is a dichroic mirror system. Is incident on. First, the blue light (wavelength of approximately 500 nm or less) is reflected by the blue reflecting dichroic mirror 373, and the other light (yellow light) is transmitted. The reflected blue light changes its direction by the reflection mirror 374 and enters the blue modulation light valve 378.
[0060]
On the other hand, the light transmitted through the blue reflecting dichroic mirror 373 is incident on a green reflecting dichroic mirror 375, where green light (having a wavelength of approximately 500 to 600 nm) is reflected, and red light (having a wavelength of approximately 600 nm or more) which is other light. Is transmitted. The green light reflected by the dichroic mirror 375 enters the green modulation light valve 379. The red light transmitted through the dichroic mirror 375 changes its direction by the reflection mirrors 376 and 377 and enters the red modulation light valve 380.
[0061]
The light valves 378, 379, and 380 are respectively driven by blue, green, and red primary color signals supplied from a signal processing circuit (not shown). Light incident on each light valve is modulated by the light valve, and then dichroic. The light is synthesized by the prism 383. The dichroic prism 383 is formed such that the red reflection surface 381 and the blue reflection surface 382 cross each other. Then, the color image synthesized by the dichroic prism 383 is enlarged and projected on a screen by the projection lens 384 and displayed.
[0062]
【The invention's effect】
As described above, the present invention relates to a first and a second image auxiliary input signal line formed in parallel on a substrate, and a timing signal line formed in parallel with the image auxiliary input signal line. A transistor provided corresponding to the data line, a relay wiring connected to one of the first and second image auxiliary input signal lines and a wiring on a source side of the transistor, and a transistor connected to the timing signal line. And a precharge circuit having a drive signal line forming a gate electrode of the transistor, wherein the relay wiring has substantially the same wiring width, length and thickness as other relay wirings.
Thereby, the resistance value of the relay wiring becomes substantially uniform. Therefore, by arranging the plurality of signal wirings almost in parallel with each other in a region intersecting with the relay wirings and making the wiring widths substantially equal, the overlapping capacity with other signal wirings becomes almost uniform, and the signal to be transmitted is Becomes substantially equal between the signal wiring paths. Further, since the length, width and film thickness of the relay wiring are almost equal, even if the wiring width deviates from the target value due to process variations, the variation in the resistance value and the capacitance value between the signal wiring paths becomes almost constant, and the time constant There is an effect that display unevenness of the active matrix type liquid crystal display device due to the variation of the above can be suppressed.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an example of an active matrix type liquid crystal display device substrate included in an active matrix type liquid crystal display device to which the present invention is applied.
FIG. 2 is a wiring layout diagram showing an embodiment in which the present invention is applied to a connection portion between a signal wiring group for supplying an image signal and a sample hold circuit in an active matrix type liquid crystal display device.
FIG. 3 is a wiring layout diagram showing a modification of the embodiment of FIG. 2;
FIG. 4 is a wiring layout diagram showing another modification of the embodiment of FIG. 2;
FIG. 5 is a wiring layout diagram showing still another modification of the embodiment of FIG. 2;
FIG. 6 is a wiring layout diagram showing still another modified example of the embodiment of FIG. 2;
FIG. 7 is a wiring layout diagram showing a second embodiment of the present invention.
FIG. 8 is a configuration diagram showing a shift register circuit and a clock signal wiring group for supplying a clock signal to the shift register circuit in an active matrix type liquid crystal display device suitable for applying the present invention.
FIG. 9 is a cross-sectional view showing a manufacturing process (first half) of a pixel TFT portion and an image signal line portion of an active matrix type liquid crystal display device to which the present invention is applied in the order of steps.
FIG. 10 is a sectional view showing a manufacturing process (middle stage) of a pixel TFT portion and an image signal line portion of an active matrix liquid crystal display device to which the present invention is applied, in the order of steps.
FIG. 11 is a cross-sectional view showing a manufacturing process (second half) of a pixel TFT portion and an image signal line portion of an active matrix liquid crystal display device to which the present invention is applied, in the order of steps.
12A is a plan view of an active matrix liquid crystal display device, and FIG. 12B is a cross-sectional view taken along line YY ′ of FIG.
FIG. 13 is a schematic configuration diagram of a data projector as an example of a projection display device in which the active matrix liquid crystal display device of the embodiment is applied as a light valve.
FIG. 14 is a timing chart illustrating an example of a relationship between a phase-developed image signal and a sampling signal of an active matrix liquid crystal display device.
FIG. 15 is a circuit diagram as an example showing a connection relationship between a signal wiring group for supplying an image signal and a sample-hold circuit in an active matrix liquid crystal display device substrate.
FIG. 16 is a layout diagram showing connection wiring between a signal wiring group for supplying an image signal and a sample-and-hold circuit in an active matrix type liquid crystal display device substrate.
FIG. 17 is a plan view of a pixel portion of an active matrix liquid crystal display device of the present invention.
FIG. 18 is a configuration diagram as an example showing a NAND circuit and a signal wiring group for supplying an enable signal to the NAND circuit in an active matrix type liquid crystal display device suitable for applying the present invention.
19 is a timing chart illustrating an example of a relationship between an enable signal and sampling signals X1, X2,..., Xn in an active matrix type liquid crystal display device suitable for applying the present invention. .., Xn overlap each other, and (B) is a timing chart in which adjacent sampling signals X1, X2,.
FIGS. 20A and 20B show equivalent circuits constituting a sample-hold circuit and a precharge circuit of an active matrix liquid crystal display device of the present invention, wherein (A) an N-channel TFT, (B) a P-channel TFT, and (C), respectively. 3) An equivalent circuit diagram showing a CMOS type TFT.
[Explanation of symbols]
1 Semiconductor layer
1a Channel region
2 Gate insulating film
3 Polysilicon film
3a capacity line
4 First interlayer insulating film
5, 8 Contact hole
6 Aluminum film
7 Second interlayer insulating film
9 ITO film
9a Pixel electrode
10 Substrate
11 scanning lines
12 Data line (source electrode)
13 pixels
14A, 14B Y shift register circuit
15 Data line drive circuit
16 Sample hold circuit
17 Precharge circuit
18 Precharge circuit drive signal line
19A Image auxiliary input signal line (NRS1)
19B Image auxiliary input signal line (NRS2)
20 Image signal wiring group
41 TFT source electrode for sample hold
42 TFT drain electrode for sample hold
42A P-channel TFT
42B N-channel TFT
43 Contact hole on the TFT source electrode side for sample hold
44 TFT hold electrode side contact hole for sample hold
45 Contact hole between image signal line and relay wiring
46 Contact hole between relay wiring and auxiliary relay wiring
49A Contact hole between image auxiliary input signal line (NRS1) and relay wiring
49B Contact hole between image auxiliary input signal line (NRS2) and relay wiring
50A Contact hole between relay wiring H1 and auxiliary relay wiring S1
50B Contact hole between relay wiring H2 and auxiliary relay wiring S2
81, 82 Relay wiring from enable signal line to NAND circuit
91-98 Relay wiring from clock signal line to shift register circuit
100 resist
101 High concentration impurity ion
110 Counter substrate
111 Counter electrode
112 Sealing material
113 Black Matrix
115 Vertical conduction terminal
116 External input / output terminal
117 liquid crystal
118 sealant
130 pixel area
150 X shift register circuit
160 Sample Hold TFT
170 Precharge TFT
180 polysilicon wiring
200,201 Clocked inverter
202,203 NAND circuit
370 lamp
373,375,376 Dichroic mirror
374,377 Reflection mirror
378,379,380 Light valve
383 dichroic prism
384 Projection lens
385 control unit

Claims (5)

First and second image auxiliary input signal lines formed in parallel on a substrate;
First and second transistors arranged in parallel corresponding to the plurality of data lines;
A first relay wiring made of polysilicon, connected from the wiring on the source side of the first transistor to the first image auxiliary input signal line via a first auxiliary relay wiring made of metal;
A second image auxiliary input signal line is connected from a source-side wiring of the second transistor to a second image auxiliary input signal line via a second auxiliary relay wiring made of a metal having a length different from that of the first auxiliary relay wiring. A second relay wiring made of polysilicon,
A precharge circuit having
The first and second relay wirings have substantially the same wiring width, length and thickness, and
The first image auxiliary input signal line is located farther from the first and second transistors with respect to the second image auxiliary input signal line;
An end of the first relay wiring is connected to an edge of the wide first image auxiliary input signal line closer to the transistor,
A tip of the second relay wiring is connected to an edge of the wide second image auxiliary input signal line that is farther from the transistor;
An active matrix substrate, characterized in that: A drive signal line formed in parallel with the first and second image auxiliary input signal lines;
A polysilicon wiring connected to the drive signal line and forming a gate electrode of the first and second transistors;
2. The active matrix substrate according to claim 1, wherein the polysilicon wiring has a width reduced in the gate electrode region. 3. The active matrix substrate according to claim 1, wherein signals having opposite signal polarities are supplied to the first and second image auxiliary input signal lines. The active matrix substrate according to claim 1, and a transparent counter substrate having a counter electrode are arranged at an appropriate distance, and the active matrix substrate and the counter substrate are arranged at an appropriate distance. An active matrix type liquid crystal display device characterized in that liquid crystal is sealed in a space between the liquid crystal display device and the liquid crystal display device. 5. The active matrix type liquid crystal display device according to claim 4, wherein the light source modulates the light from the light source and transmits or reflects the light, and collects and modulates and projects the light modulated by the active matrix type liquid crystal display device. A projection display device comprising: projection optical means.

Images