JP2001085693A - Method for manufacturing semiocnductor device, electro- optical device and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a structure which can absorb an irregularity in a character istic due to a mask displacement when a lightly doped drain(LDD) structure is formed in a thin-film transistor(TFT) or the like having the LDD structure and to provide its manufacturing method or the like. SOLUTION: This semiconductor device (a TFT or the like) is constituted in such a way that source-drain regions to which impurities are introduced are provided and that LDD regions to which impurities are introduced at a concentration which is lower than the concentration of the impurities introduced to the source-drain regions are provided. In this case, an intermediately doped region 1g and an intermediately doped region 1h whose impurity concentration is lower than that of the source-drain regions and whose impurity concentration is higher than that of the LDD regions are formed in regions between the source-drain regions 1d, 1e and between the LDD regions 1b, 1c.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device and a method for manufacturing the same, and an electro-optical device and a method for manufacturing the same. In particular, the present invention relates to a semiconductor device having an LDD (Lightly Doped Drain) structure.

[0002]

2. Description of the Related Art In a liquid crystal device as an example of an electro-optical device, a thin film transistor (TFT) is often used as a switching element for pixel switching and a switching element in a peripheral driving circuit. In this case, the pixel switching TFT
It is preferable to use an LDD (Lightly Doped Drain) structure.

FIG. 3 shows the structure of a pixel switching TFT having an LDD structure. In the figure, a pixel switching TFT 30 insulates a scanning line (gate electrode) 3a, a channel region 1a 'of a semiconductor layer 1a where a channel is formed by an electric field from the scanning line 3a, and the scanning line 3a and the semiconductor layer 1a. Gate insulating film 2, data line 6a, low-concentration source region (source-side LDD region) 1 of semiconductor layer 1a
b and low concentration drain region (drain side LDD region) 1
c, a high-concentration source region 1d and a high-concentration drain region 1e of the semiconductor layer 1a. High concentration drain region 1
e is connected to a corresponding one of the plurality of pixel electrodes 9a. As described later, the source regions 1b and 1d and the drain regions 1c and 1e are different from the semiconductor layer 1a.
It is formed by doping a predetermined concentration of n-type or p-type dopant depending on whether an n-type or p-type channel is formed. An n-type channel TFT has the advantage of a high operating speed, and is often used as a pixel switching TFT that is a pixel switching element.

A switching element in the peripheral drive circuit preferably has an LDD (Lightly Doped Drain) structure.

[0005]

However, the LDD
When manufacturing a semiconductor device such as a TFT having a structure, an LD
The method of forming a mask on the LDD region in order to block the introduction of impurities into the D region has a problem that variation in TFT characteristics due to mask displacement is large. This variation in characteristics leads to variation in alignment (flickering of the screen) in the alignment control of the liquid crystal in the liquid crystal device.
In a semiconductor device, the threshold characteristics vary.

SUMMARY OF THE INVENTION The present invention has been made under the above-mentioned background, and has as its object to provide a structure capable of absorbing variations in characteristics due to mask displacement when forming an LDD structure, and a method of manufacturing the same.

[0007]

According to the present invention, there is provided a method of manufacturing a semiconductor device, comprising: a source / drain region in which an impurity is introduced into a semiconductor layer formed on a substrate; and an impurity introduced into the source / drain region. A method of manufacturing a semiconductor device having an LDD region into which an impurity is introduced at a concentration lower than that of the semiconductor device, wherein after forming the semiconductor layer on the substrate, at least a portion of the semiconductor layer to be the LDD region A step of covering a portion adjacent to the LDD region and serving as a medium concentration region with respect to the impurity concentration of the source / drain region with a mask, and introducing a high concentration of impurities into a portion serving as a source / drain region; Is covered with a mask, an impurity is introduced at a medium concentration in the portion to be a medium concentration region, and after removing the mask in the portion to be the LDD region, L A step of introducing a low concentration of impurities in the portion to be a D region, and having at least a.

According to such a configuration of the present invention, since the medium density region is provided, there is an effect that variations in characteristics due to mask shift can be reduced.

In particular, the present invention is characterized in that the step of introducing impurities at a high concentration is performed before forming a gate insulating film of the semiconductor device. Further, the step of introducing the impurity into the medium concentration region is performed after forming the gate electrode. Further, the method is characterized in that a low concentration impurity is introduced after removing a mask for introducing an impurity into the medium concentration region.

By forming a semiconductor device having a medium-concentration region by such a process, a semiconductor device with reduced variation in characteristics can be obtained.

Further, according to the present invention, a semiconductor layer formed on a substrate has a source / drain region in which an impurity having a first conductivity type is introduced, and a first conductivity type in which the source / drain region is introduced. A semiconductor device having an LDD region into which an impurity is introduced at a concentration lower than the impurity concentration and a semiconductor device having a source / drain region into which an impurity of the second conductivity type is introduced are formed on the same substrate. A method for manufacturing a semiconductor device, comprising: forming at least the semiconductor layer on the substrate;
A portion that becomes a D region, a portion that is adjacent to the LDD region and becomes a medium concentration region with respect to the impurity concentration of the source / drain region of the first conductivity type, and a portion that becomes the second conductivity type are covered with a mask, A step of introducing a first conductivity type impurity into a portion to be a region at a high concentration; a step of covering the LDD region portion with a mask; and introducing a first conductivity type impurity at a medium concentration; Removing the mask in a portion to be an LDD region, and introducing a low concentration of an impurity to be an LDD region.

By adopting such a manufacturing method, a semiconductor device doped with impurities of different conductivity types can be formed on the same substrate, and variations in characteristics are small because the medium concentration region is formed. A semiconductor device can be obtained. Further, when the semiconductor device of the present invention is a thin film transistor, for example, in a liquid crystal device, there is an effect that variations in liquid crystal control (screen flicker) and variations in peripheral driving circuits can be reduced.

Further, the step of introducing the impurity which becomes the first conductivity type at a high concentration at a high concentration is performed before forming a gate insulating film of the semiconductor device. Further, the method is characterized in that a step of introducing the impurity having the second conductivity type into a portion serving as a source / drain region after at least processing a gate electrode of the semiconductor device having the second conductivity type is provided. Further, the step of introducing an impurity having the first conductivity type into the intermediate concentration region includes, after processing at least a gate electrode of the semiconductor device having the second conductivity type, the gate electrode of the semiconductor device having the first conductivity type. It is characterized in that it is performed after formation.

The step of introducing the impurity of the first conductivity type into the middle concentration region is performed before removing the mask material for processing the gate electrode. Further, the step of introducing the impurity of the first conductivity type into the middle concentration region includes overetching the width of the gate electrode by 0.2 μm or more and 1.5 μm in the gate length direction with respect to a mask material for processing the gate electrode. After that, it is performed before the mask is removed. Further, after removing the mask for introducing the impurity into the intermediate concentration region, the impurity of the first conductivity type is added to at least both the semiconductor device of the first conductivity type and the semiconductor device of the second conductivity type. It is characterized in that each gate electrode is introduced as a mask.

Further, the semiconductor device having the first conductivity type is connected to the drain region, extends from an extraction electrode connected to the drain region, and is formed in the same layer as the gate electrode via a gate insulating film. In the method of manufacturing a semiconductor device in which a capacitance is formed by the formed electrode or wiring and the extension, at least a semiconductor layer of the extension and a source / drain region of the semiconductor device simultaneously have an impurity of the first conductivity type. Is introduced.

An electro-optical device comprising: a plurality of scanning lines; a plurality of data lines; pixel electrodes and switching elements arranged in a matrix corresponding to intersections of the scanning lines and the data lines; An electro-optical device, wherein the switching element is formed by the method of manufacturing a semiconductor device described above.

Further, the electro-optical device includes a plurality of scanning lines, a plurality of data lines, and pixel electrodes and switching elements arranged in a matrix corresponding to intersections of the scanning lines and the data lines. An electro-optical device, wherein the switching element is formed by the method of manufacturing a semiconductor device described above. According to such a configuration, a thin film transistor in which variations in characteristics due to mask displacement are reduced is formed. For example, in a liquid crystal device formed as an electro-optical device, variations in liquid crystal control (screen flicker) and variations in peripheral driving circuits are caused. Can be reduced.

An electronic apparatus according to the present invention includes the above-described electro-optical device according to the present invention.

According to such a configuration of the present invention, since the electro-optical device using the thin film transistor in which the variation in the characteristics due to the mask shift is reduced is provided, for example, the display quality can be improved. Having.

[0020]

Embodiments of the present invention will be described below with reference to the drawings.

(Configuration of Electro-Optical Device) FIG. 1 shows the configuration of the electro-optical device according to this embodiment together with the operation thereof.
This will be described with reference to FIG.

FIG. 1 is an equivalent circuit diagram of various elements, wirings, and the like in a plurality of pixels formed in a matrix forming an image display area of the electro-optical device. FIG. 2 is a diagram showing a configuration of a TFT array substrate on which data lines, scanning lines, pixel electrodes, light-shielding films and the like are formed among a pair of substrates constituting the electro-optical device. It is a top view. FIG. 3 is a sectional view taken along line AA ′ of FIG. In FIGS. 3 and 4, the scale of each layer and each member is made different so that each layer and each member have a size recognizable in the drawings.

In FIG. 1, a plurality of pixels formed in a matrix and constituting an image display area of the electro-optical device according to the present embodiment include a pixel electrode 9a and the pixel electrode 9a.
And a data line 6a to which an image signal is supplied is electrically connected to a source of the TFT 30. The image signals S1, S2,..., Sn to be written to the data lines 6a may be supplied line-sequentially in this order, or may be supplied to a plurality of adjacent data lines 6a for each group. good. Also, T
The scanning line 3a is electrically connected to the gate of the FT 30, and is configured to apply the scanning signals G1, G2,..., Gm in a pulsed manner to the scanning line 3a in this order at a predetermined timing. ing. The pixel electrode 9a is a TFT 30
Of the TFT 30 which is a switching element and is closed by a switch for a predetermined period, so that the image signal S supplied from the data line 6a is provided.
1, S2,..., Sn are written at a predetermined timing. The image signals S1, S2,..., Sn of a predetermined level written in the electro-optical material via the pixel electrodes 9a are held for a certain period between the counter electrodes (described later) formed on the counter substrate (described later). Is done. In an electro-optical material, the orientation and order of a molecular assembly change depending on the applied voltage level. Thus, for example, when the electro-optical material is a liquid crystal, the incident light incident on the electro-optical device is modulated by the electro-optical material, thereby enabling a gray scale display. In the normally white mode, the incident light is modulated by the electro-optic material according to the applied voltage and cannot pass through the polarizing element. In the normally black mode, the incident light is modulated according to the applied voltage. The incident light is modulated by the electro-optical material and allowed to pass by the polarizing element, and the electro-optical device emits light having a contrast corresponding to the image signal as a whole.
Here, in order to prevent the held image signal from leaking, the storage capacitor 70 is connected in parallel with the electro-optical material capacitor formed between the pixel electrode 9a and the counter electrode formed on the counter substrate.
Is added. For example, the voltage of the pixel electrode 9a is held by the storage capacitor 70 for a time that is three orders of magnitude longer than the time during which the source voltage is applied. Thereby, the holding characteristics are further improved, and an electro-optical device having a high contrast ratio can be realized.

In FIG. 2, T which constitutes the electro-optical device
On the FT array substrate, a plurality of transparent pixel electrodes 9a are arranged in a matrix (the outlines are indicated by dotted lines 9a ').
Are provided, and the data line 6a, the scanning line 3a, and the capacitor line 3b are provided along the vertical and horizontal boundaries of the pixel electrode 9a. The data line 6a is electrically connected to a source region described later in the semiconductor layer 1a made of a polysilicon film or the like via the contact hole 5, and the pixel electrode 9a is
The semiconductor layer 1a is electrically connected to a drain region to be described later in the semiconductor layer 1a through the contact hole 8. In addition, the scanning line 3a is arranged so as to face a channel region (a hatched region on the right in the figure) of the semiconductor layer 1a.
a functions as a gate electrode.

The capacitance line 3b has a main line portion extending substantially linearly along the scanning line 3a, and a protruding portion protruding forward (upward in the drawing) along the data line 6a from a portion intersecting the data line 6a. And

The first light-shielding film 11a is provided in each of the rectangular island regions indicated by the thick lines in the drawing. More specifically, each of the island-shaped first light-shielding films 11a has at least a channel region of each TFT when viewed from the TFT array substrate side.
It is provided at a position to cover each pixel.

Next, as shown in the cross-sectional view of FIG. 3, the electro-optical device includes a TFT array substrate 10 and an opposing substrate 20 that is disposed to oppose the TFT array substrate. TFT array substrate 10
Is made of, for example, a glass substrate or a quartz substrate,
0 is also formed of, for example, a glass substrate or a quartz substrate. Pixel electrodes 9a are provided in a matrix on the TFT array substrate 10, and an alignment film 16 on which a predetermined alignment process such as a rubbing process is performed is provided above the pixel electrodes 9a. The pixel electrode 9a is made of, for example, a transparent conductive thin film such as an ITO film (Indium Tin Oxide film). The alignment film 16 is made of, for example, an organic thin film such as a polyimide thin film.

On the other hand, a counter electrode (common electrode) 21 is provided on the entire surface of the counter substrate 20, and an alignment film 23 on which a predetermined alignment process such as a rubbing process is performed is provided below the counter electrode (common electrode). Is provided. The counter electrode 21 is, for example, I
It is made of a transparent conductive thin film such as a TO film. Also, the alignment film 23
Consists of an organic thin film such as a polyimide thin film.

As shown in FIG. 3, the TFT array substrate 10 is provided with a pixel switching TFT 30 which is connected to each pixel electrode 9a and controls switching of each pixel electrode 9a.

As shown in FIG. 3, the counter substrate 20 further includes a region other than the opening region of each pixel (that is, a region where the incident light actually transmits and effectively contributes to the display in the image display region). , A second light-shielding film 22 called a black mask or a black matrix is provided. For this reason, the incident light from the side of the opposing substrate 20 is applied to the channel region 1 a ′ of the semiconductor layer 1 a of the pixel switching TFT 30 or the LD.
It does not enter the D (Lightly Doped Drain) regions 1b and 1c. Further, the second light-shielding film 22 has a function of improving contrast, preventing color mixture of color materials, and the like.

A sealing material described later (see FIGS. 9 and 10) is provided between the TFT array substrate 10 and the opposing substrate 20 having the above-described structure and in which the pixel electrode 9a and the opposing electrode 21 are arranged so as to face each other. The electro-optical material is sealed in the space surrounded by (), and the electro-optical material layer 50 is formed. The electro-optical material layer 50 assumes a predetermined alignment state by the alignment films 16 and 23 in a state where no electric field is applied from the pixel electrode 9a. The electro-optical material layer 50 is made of, for example, one or several types of nematic liquid crystal. The sealing material is an adhesive made of, for example, a photo-curing resin or a thermosetting resin for bonding the two substrates 10 and 20 around them, and a glass for setting a distance between the two substrates to a predetermined value. Spacers such as fibers or glass beads are mixed.

As shown in FIG. 3, an insulating film 12 is provided between the TFT array substrate 10 and the plurality of pixel switching TFTs 30. The insulating film 12 is made of TF
By being formed on the entire surface of the T array substrate 10, it also has a function as a base film for the pixel switching TFT 30. That is, it has a function of preventing deterioration of the characteristics of the pixel switching TFT 30 due to roughening of the surface of the TFT array substrate 10 during polishing, dirt remaining after cleaning, and the like. The insulating film 12 is made of, for example, a silicon oxide film, a silicon nitride film, or the like.

In FIG. 3, the pixel switching TFT
Reference numeral 30 denotes an LDD (Lightly Doped Drain) structure, and includes a scanning line 3a and a channel region 1 of a semiconductor layer 1a in which a channel is formed by an electric field from the scanning line 3a.
a ', the gate insulating film 2 for insulating the scanning line 3a from the semiconductor layer 1a, the data line 6a, the low-concentration source region (source-side LDD region) 1b and the medium-concentration source region (not shown) of the semiconductor layer 1a, and the low-concentration source region. Concentration drain region (drain side L
DD region 1c, a medium-concentration source region (not shown), a high-concentration source region 1d of the semiconductor layer 1a, and a high-concentration drain region 1e. A corresponding one of the plurality of pixel electrodes 9a is connected to the high-concentration drain region 1e. As will be described later, the source regions 1b and 1d and the drain regions 1c and 1e
It is formed by doping a predetermined concentration of n-type or p-type dopant depending on whether a type or p-type channel is formed. An n-type channel TFT has the advantage of a high operating speed, and is often used as a pixel switching TFT 30 that is a pixel switching element.

In this embodiment, particularly, as shown in FIG. 4, the impurity concentration between the source / drain region and the LDD region is lower than that of the source 1d and the drain region 1e and higher than that of the LDD regions 1b and 1c. Medium concentration area 1g, 1
Since h is provided, it is possible to structurally absorb variations in characteristics due to mask misalignment when forming the LDD structure. In this case, the density, width, etc. of the middle density regions 1g, 1h can be appropriately designed according to the purpose of the present invention. In this embodiment, the gate electrode 3a of the pixel switching TFT 30 is connected to the source
Although only one single gate structure is arranged between the drain regions 1d and 1e, two or more gate electrodes may be arranged between them. At this time, the same signal is applied to each gate electrode. When a TFT is formed with a dual gate or triple gate or more as described above, a leak current at a junction between a channel and a source-drain region can be prevented, and a current in an off state can be reduced.
If at least one of these gate electrodes has a structure having an intermediate concentration region or an LDD structure, the off-state current can be further reduced and a stable switching element can be obtained.

As described above in detail, according to the present embodiment, a medium-concentration region having a lower impurity concentration and a higher impurity concentration than the source / drain region between the source / drain region and the LDD region of the TFT. Has been established,
Variations in TFT characteristics due to mask displacement can be structurally absorbed.

(Manufacturing Process of TFT Array Substrate and Electro-Optical Device) Next, with respect to the manufacturing process of the electro-optical device having the above configuration, the process of the TFT array substrate forming the electro-optical device will be described with reference to FIGS. This will be described with reference to FIG. 5 and 6 are process diagrams showing cross sections of the respective layers on the TFT array substrate side in the respective steps.

In FIGS. 5 and 6, T in the display area
The scanning signal or the gate signal is applied not only to the manufacturing process of the FT60 (N-channel TFT) and the storage capacitor, but also to a peripheral region formed in parallel with the manufacturing process (that is, the TFT 60 in the display region). The manufacturing process of TFTs (complementary TFTs 61 (N-channel) and TFT 62 (P-channel)) in a peripheral circuit in which TFTs and the like are formed around the display area in order to drive this is also described. It is.

As shown in FIG. 5A, the glass substrate 31
An insulating layer 32 is formed thereon. In this case, for example, after cleaning the glass substrate 31, an insulating film 32 of passivation, such as SiO2 or SiNx, is formed with a thickness of about 1000 to 5000 angstroms. The insulating film 32 is formed by, for example, SiH4,
O2 or TEOS, O2 is used to convert SiO2 to SiH4, N2.
SiNx is formed using H3 and O2. This first step is the same in the display area and the peripheral area.

Next, as shown in FIG.
2 and an amorphous silicon layer 33 of 200 to 1
It is formed to about 000 angstroms. The amorphous silicon layer 33 can be formed by various methods such as an LP-CVD method, a sputtering method, or a method using amorphous silicon formed by plasma CVD and subjected to dehydrogenation annealing. This second step is the same in the display area and the peripheral area.

Next, as shown in FIG. 5C, the amorphous silicon layer 33 is recrystallized by subjecting the amorphous silicon layer 33 to a heat treatment such as an excimer laser anneal treatment, so that the amorphous silicon layer 33 is recrystallized. Silicon layer 3
4 (the thickness is, for example, 500 angstroms). Note that an RTP method or a solid layer growth method at about 600 ° C. may be used instead of the laser annealing treatment. This third
The steps are the same in the display area and the peripheral area.
The glass substrate is omitted from FIG.

Next, as shown in FIG. 5D, the polysilicon layer 34 is patterned into an island shape by photolithography to obtain a polysilicon pattern 34a. This fourth step is the same in the display area and the peripheral area.

Next, as shown in FIG. 5 (5), phosphorus is applied to the source / drain regions of the N-channel TFTs 60 and 61 by using a mask 35 made of a resist or a metal, from 1 × 10 ^{14 to} 5 ×. It is introduced at a high concentration of 10 ¹⁵ particles / cm ² . At this time, the mask 35 is formed so as to cover from 1 to 3 μm outside the position where the gate electrode will be formed later. Note that this value changes due to misalignment.
In the present embodiment, the portion outside the portion serving as the LDD region is covered with the mask as described above, so that a later-described medium-density region can be formed. Note that the insulating layer is omitted from FIG.

Next, as shown in FIG.
5 is removed, and the gate insulating film 3 is covered so as to cover the entire substrate.
6 is formed to a thickness of about 500 to 1500 angstroms. The gate insulating film 36 is formed by plasma CVD or EC.
It can be formed using a means such as an R plasma CVD method.

Next, as shown in FIG. 5 (7), a metal serving as a gate electrode, for example, Al, Ta, MoTa, AlT
After a composite material of a, Cr, AlCu, and aluminum is formed on the entire surface of the substrate by a sputtering method or the like, only the P channel portion is etched to form the gate electrode 37a and the metal layer 37 serving as the gate electrode. Note that these materials described above can be stacked and formed. The film thickness depends on the design, but must be a film thickness that functions as a mask when introducing impurities such as phosphorus and boron. For example, 2000
About 8000 angstroms. Etching is performed by a method suitable for each material.

Next, as shown in FIG. 5 (8), a metal layer 37 serving as a gate electrode of the N channel portion in the state of raw boron 7e ¹⁴ ~ in a portion serving as source and drain regions of the P-channel 5e Introduce at a high concentration of ¹⁵ particles / cm ² .

Next, as shown in FIG. 5 (9), the metal layer 37 serving as an unprocessed gate electrode in the channel portion is processed to form gate electrodes 37b and 37c and a wiring 37d.

Next, as shown in FIG. 5 (10), a mask 38 made of a resist or a metal is used to mask the portions to be the LDD regions of the P channel and the N channel, and
Medium concentration of about ^{13 to} 7e ¹⁴ / cm ² is introduced.
The mask 38 is formed so as to cover the gate electrode by about 0.5 to 1.5 μm.

Next, as shown in FIG. 6 (11), after removing the medium concentration impurity introduction mask 38, the introduction of the low concentration of ^1e 13 ^{~1e 14} pieces / cm ² about the phosphorus across the substrate. The LDD region is set to about 0.5 to 1.5 μm.

Next, as shown in FIG. 6 (12), the entire substrate is covered with a first interlayer insulating film 39. As the first interlayer insulating film 39, an organic insulating film such as an acrylic resin or polyimide is also effective, or a commonly used inorganic insulating film such as SiO ₂ may be used.

Next, as shown in FIG. 6 (13), after annealing for impurity activation, for example, annealing at 300 to 400 ° C., a connection is made to connect the extraction electrodes from the source / drain regions of each thin film transistor. The contact hole 40 is opened by means such as exposure, development, wet or dry etching.

Next, as shown in FIG. 6 (14), a metal 4 mainly composed of aluminum, such as AlCu, serving as an extraction electrode.
1 is formed by a sputtering method or the like. Note that a material other than aluminum may be used.

Next, as shown in FIG. 6 (15), a layer serving as an extraction electrode is etched to form an extraction electrode 41a.

Next, as shown in FIG. 6 (16), a second interlayer insulating film 42 made of an inorganic insulating film or an organic insulating film is formed so as to cover the whole, for example. This second interlayer insulating film 4
In the case of forming a liquid crystal device as an electro-optical device, it is possible to reduce the capacitance added to the signal line if an organic insulating film can be formed by a coating method at the same time as forming the liquid crystal device. Since the disorder of the alignment of the liquid crystal sandwiched in the device can be eliminated, it is very effective for increasing the number of pixels. At this time, the thickness of the insulating film on the extraction electrode is desirably about 5,000 to 40,000 angstroms.

Next, as shown in FIG. 6 (17), a second contact hole 43 for connecting a pixel electrode is formed in the drain electrode portion of the thin film transistor in the display region of the second interlayer insulating film. . The opening is made by means suitable for the material of the second interlayer insulating film.

Finally, as shown in FIG. 1 (18), a metal electrode 44 such as a transparent conductive film ITO or aluminum for reflecting light or an aluminum composite material such as AlCu is formed to form a TF.
All steps of the T array substrate are completed.

In the above steps, activation annealing and the like may be performed in steps other than the positions described above.

Thereafter, an opposing electrode is formed on the opposing substrate (not shown), and a liquid crystal device is completed through processing such as filling liquid crystal between the pixel electrode 44 and the opposing electrode.

In the present embodiment, a middle concentration region having an impurity concentration lower than that of the source / drain region and higher than that of the LDD region is provided between the source / drain region and the LDD region. Can be structurally absorbed.

In the present embodiment, a single gate structure in which only one gate electrode 3a of the pixel switching TFT 30 is disposed between the source-drain regions 1d and 1e has been described. Electrodes may be arranged. At this time, the same signal is applied to each gate electrode. When a TFT is formed with a dual gate or triple gate or more as described above, a leak current at a junction between a channel and a source-drain region can be prevented, and a current in an off state can be reduced. If at least one of these gate electrodes has an LDD structure, the off-state current can be further reduced, and a stable switching element can be obtained.

In this embodiment, in particular, the impurity concentration between the source / drain region and the LDD region in the LDD-TFT in the display region and the peripheral region of the electro-optical device is lower than that of the source / drain region and the LDD region. Since a higher medium density region is provided, T
Variations in FT characteristics can be structurally absorbed.

(Overall Configuration of Electro-Optical Device) The overall configuration of each embodiment of the electro-optical device configured as described above will be described with reference to FIG. 7 and FIG. FIG. 7 is a plan view of the TFT array substrate 10 together with the components formed thereon as viewed from the counter substrate 20 side. FIG. It is H 'sectional drawing.

In FIG. 7, a sealing material 52 is provided on the TFT array substrate 10 along the edge thereof.
In parallel with the inside, the third light-shielding film 5 as a peripheral parting, which is made of the same or different material as the second light-shielding film 22, for example.
3 are provided. In a region outside the sealing material 52,
A data line driving circuit 101 and a mounting terminal 102 are provided along one side of the TFT array substrate 10, and a scanning line driving circuit 104 for supplying a signal to a scanning line connected to the TFT includes a scanning line driving circuit 104 adjacent to this side. It is provided along the side. If the delay of the scanning signal supplied to the scanning line is not a problem, it goes without saying that the scanning line driving circuit 104 may be provided on only one side. Further, data line driving circuits 101 for supplying signals to the data lines connected to the TFTs may be arranged on both sides along the sides of the image display area. For example, the odd-numbered data lines supply image signals from a data line driving circuit disposed along one side of the image display area, and the even-numbered data lines extend along the opposite side of the image display area. The image signal may be supplied from the data line driving circuit provided. If the data lines are driven in a comb-tooth shape as described above, the area occupied by the data line driving circuit can be expanded, so that a complicated circuit can be formed. Further, on the remaining one side of the TFT array substrate 10, a plurality of wirings 105 for connecting between the scanning line driving circuits 104 provided on both sides of the image display area are provided. In at least one of the corners of the opposing substrate 20, an upper / lower conducting member 106 for establishing electric conduction between the TFT array substrate 10 and the opposing substrate 20 is provided. Then, as shown in FIG. 8, the counter substrate 20 having substantially the same contour as the sealing material 52 shown in FIG. 7 is fixed to the TFT array substrate 10 by the sealing material 52.

In the embodiments described above with reference to FIGS. 1 to 8, instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the TFT array substrate 10, for example, TAB (tape automated) is used. A drive LSI mounted on a bonding substrate) may be electrically and mechanically connected via an anisotropic conductive film provided on the periphery of the TFT array substrate 10. For example, the side of the opposite substrate 20 on which the projected light is incident and the side of the TFT array substrate 10 on which the emitted light is emitted are, for example, T
A phase element such as a retardation film according to an operation mode such as N (twisted nematic) mode, STN (super TN) mode, D-STN (double-STN) mode, and normally white mode / normally black mode , Polarizing plate, polarizing beam splitter (PB
A polarizing element such as S) is set and arranged under predetermined conditions.

The electro-optical device according to each embodiment described above is applied to a light valve of a projector.
That is, three electro-optical devices are used as light valves for RGB, and light of each color separated through a dichroic mirror for RGB color separation is incident on each panel as projection light. Become. Therefore, in each embodiment, the counter substrate 20 is not provided with a color filter. However, in a predetermined region facing the pixel electrode 9a where the second light shielding film 22 is not formed, RGB
May be formed on the counter substrate 20 together with the protective film. In this way, the present invention can be applied to a direct-view or reflection-type color electro-optical device other than the projector. Further, one corresponding microlens may be formed for each pixel on the counter substrate 20. If you do this,
By improving the efficiency of condensing incident light, a bright electro-optical device can be realized. Furthermore, a dichroic filter that produces RGB colors using light interference may be formed by depositing a number of interference layers having different refractive indexes on the counter substrate 20. According to the counter substrate with the dichroic filter, a brighter color electro-optical device can be realized.

In the electro-optical device according to each of the embodiments described above, incident light is incident from the side of the counter substrate 20 as in the related art. However, as shown in FIG. Since the light shielding film 11a is provided, T
The incident light may be incident from the FT array substrate 10 side and may be emitted from the counter substrate 20 side. That is, even if the electro-optical device is attached to the projector in this manner, the channel region 1a 'and the LDD regions 1b, 1b
Light can be prevented from entering c, and a high-quality image can be displayed. Here, conventionally, the TFT
In order to prevent reflection on the rear surface side of the array substrate 10, a polarizing plate coated with an anti-reflection AR coating is separately arranged,
It was necessary to attach an R film. However, in each embodiment, the surface of the TFT array substrate 10 and the semiconductor layer 1
a at least the channel region 1a 'and the LDD region 1
Since the first light-shielding film 11a is formed between b and 1c, it is necessary to use such an AR-coated polarizing plate or AR film, or to use a substrate obtained by AR-processing the TFT array substrate 10 itself. Disappears. Therefore, according to each of the embodiments, the material cost can be reduced, and the yield is not significantly reduced due to dust, scratches or the like at the time of attaching the polarizing plate, which is very advantageous. In addition, since light resistance is excellent, even if a bright light source is used or polarization conversion is performed by a polarizing beam splitter to improve light use efficiency, image quality deterioration such as crosstalk due to light does not occur.

The switching element provided in each pixel has been described as a normal stagger type or coplanar type polysilicon TFT.
The embodiments are also effective for other types of TFTs such as TFTs and amorphous silicon TFTs.

(Electronic Apparatus) Next, an embodiment of an electronic apparatus having the electro-optical device described in detail above will be described with reference to FIG.
Will be described with reference to FIG.

First, FIG. 9 shows a schematic configuration of an electronic apparatus having a liquid crystal device 100 as an example of an electro-optical device.

In FIG. 9, the electronic equipment includes a display information output source 1000, a display information processing circuit 1002, a drive circuit 10
04, a liquid crystal device 100, a clock generation circuit 1008, and a power supply circuit 1010. The display information output source 1000 includes a ROM (Read Only Memory), RA
M (Random Access Memory), a memory such as an optical disk device, a tuning circuit for tuning and outputting an image signal, etc.
Based on a clock signal from the clock generation circuit 1008, display information such as an image signal in a predetermined format is output to the display information processing circuit 1002. Display information processing circuit 1
Reference numeral 002 includes various known processing circuits such as an amplification / polarity inversion circuit, a serial-parallel conversion circuit, a rotation circuit, a gamma correction circuit, and a clamp circuit, and includes a display information input based on a clock signal. Digital signals are sequentially generated and output to the drive circuit 1004 together with the clock signal CLK. The drive circuit 1004 drives the liquid crystal device 100. The power supply circuit 1010 supplies a predetermined power to each of the above-described circuits. The driving circuit 1004 may be mounted on the TFT array substrate constituting the liquid crystal device 100. In addition, the display information processing circuit 1002 may be mounted and the driving circuit 6 may be mounted.

Next, FIGS. 10 to 11 show specific examples of the electronic apparatus configured as described above.

In FIG. 10, a liquid crystal projector 1100, which is an example of electronic equipment, prepares three liquid crystal display modules each including the liquid crystal device 100 in which the above-described drive circuit 1004 is mounted on a TFT array substrate, and each of the light emitting devices for RGB. The projector is used as the bulbs 100R, 100G, and 100B. In the liquid crystal projector 1100, when projection light is emitted from a lamp unit 1102 of a white light source such as a metal halide lamp, three mirrors 1106 and two dichroic mirrors 11 are provided.
08, light components R corresponding to the three primary colors of RGB,
Light valve 100 divided into G and B and corresponding to each color
R, 100G and 100B, respectively. At this time, in particular, the B light is used to prevent light loss due to a long optical path, so that the input lens 1122, the relay lens 1123, and the output lens 11
24, through a relay lens system 1121. Then, the light valves 100R, 100G and 10
The light components corresponding to the three primary colors, each modulated by 0B,
After being recombined by the dichroic prism 1112, it is projected as a color image on the screen 1120 via the projection lens 1114.

In FIG. 11, a multimedia type laptop personal computer (PC) 1200, which is another example of electronic equipment, has the above-described liquid crystal device 100 provided in a top cover case, and further includes a CPU,
The keyboard 1202 accommodates a memory, a modem, and the like.
Is provided.

In addition to the electronic devices described with reference to FIGS. 10 to 11, a liquid crystal television, a viewfinder type or a monitor direct-view type video tape recorder, a car navigation device, an electronic organizer, a calculator, a word processor, an engineering machine, and the like. A workstation (EWS), a mobile phone, a video phone, a POS terminal, a device equipped with a touch panel, and the like are examples of the electronic apparatus shown in FIG.

As described above, according to the present embodiment, it is possible to realize various electronic devices including a liquid crystal device capable of displaying a high-quality image with high manufacturing efficiency.

[Brief description of the drawings]

FIG. 1 is an equivalent circuit of various elements, wirings, and the like provided in a plurality of pixels in a matrix forming an image display area and a peripheral area in an embodiment of an electro-optical device.

FIG. 2 shows a data line in the embodiment of the electro-optical device,
FIG. 3 is a plan view of a plurality of pixel groups adjacent to each other on a TFT array substrate on which a scanning line, a pixel electrode, a light shielding film, and the like are formed.

FIG. 3 is a sectional view taken along line A-A 'of FIG.

FIG. 4 is an enlarged sectional view of a main part of FIG.

FIG. 5 is a process diagram (part 1) for sequentially illustrating the manufacturing process of the electro-optical device.

FIG. 6 is a process diagram (part 2) for sequentially illustrating the manufacturing process of the electro-optical device.

FIG. 7 is a plan view of the TFT array substrate in the embodiment of the electro-optical device together with the components formed thereon as viewed from the counter substrate side.

8 is a sectional view taken along the line H-H 'of FIG.

FIG. 9 is a block diagram showing a schematic configuration of an embodiment of an electronic device according to the present invention.

FIG. 10 is a cross-sectional view illustrating a liquid crystal projector as an example of an electronic apparatus.

FIG. 11 is a front view illustrating a personal computer as another example of the electronic apparatus.

[Description of Signs] 1a: semiconductor layer 1a ': channel region 1b: low-concentration source region (source-side LDD region) 1c: low-concentration drain region (drain-side LDD region) 1d: high-concentration source region 1e: high-concentration drain region 1g: Medium-concentration source region (source-side LDD region) 1h: Medium-concentration drain region (drain-side LDD region) 2: Gate insulating film 3a: Scan line 4: First interlayer insulating film 5: Contact hole 6a: Data line 7: Second interlayer insulating film 8 Contact hole 9a Pixel electrode 10 TFT array substrate 12 Insulating film 16 Alignment film 20 Counter substrate 21 Counter electrode 22 Second light shielding film 23 Alignment film 30 Pixel switching TFT Reference Signs List 50: electro-optical material layer 52: sealing material 53: third light-shielding film 70: storage capacitor 101: data line driving circuit 103: sampler Grayed circuit 104 ... scan line driver circuit

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H092 GA51 HA26 HA27 JA24 JA31 JA32 JA34 JA35 JA37 JA41 JB22 JB31 JB69 KA05 KA10 MA13 MA17 MA27 MA29 NA01 NA24 NA25 PA02 PA06 PA07 PA10 PA11 QA07 QA10 RA05 5F110 AA06 BB02 DD02 DD15 DD24 EE03 EE04 EE06 EE44 FF30 FF31 GG02 GG13 GG25 GG35 GG43 GG45 GG47 HJ01 HJ04 HJ23 HL06 HL23 HM15 NN02 NN23 NN27 NN32 NN73 NN78 PP02 PP03 PP10 PP35

Claims (15)

[Claims] A source / drain region in which an impurity is introduced into a semiconductor layer formed on a substrate;
A method for manufacturing a semiconductor device comprising an LDD region doped with an impurity at a concentration lower than the concentration of an impurity introduced into a drain region, comprising: forming the semiconductor layer on the substrate; At least a portion to be the LDD region and the L
Covering a portion adjacent to the DD region and serving as a medium concentration region with respect to the impurity concentration of the source / drain region with a mask, and introducing a high concentration of impurity into the portion serving as the source / drain region; Is covered with a mask, and an impurity is introduced at a medium concentration in a portion to be a medium concentration region. After the mask in the portion to be the LDD region is removed, the LD
Introducing a low-concentration impurity into a portion to be a D region;
A method for manufacturing a semiconductor device, comprising at least: 2. The method of manufacturing a semiconductor device according to claim 1, wherein said step of introducing impurities at a high concentration is performed before forming a gate insulating film of said semiconductor device. Device manufacturing method. 3. The method of manufacturing a semiconductor device according to claim 1, wherein the step of introducing an impurity into the medium concentration region is performed after forming a gate electrode. 4. The method for manufacturing a semiconductor device according to claim 1, wherein a low concentration impurity is introduced after removing a mask for introducing the impurity into the medium concentration region. Manufacturing method of a semiconductor device. 5. A source / drain region in which an impurity having a first conductivity type is introduced into a semiconductor layer formed on a substrate, and a concentration of the impurity having a first conductivity type introduced into the source / drain region. Of a semiconductor device having an LDD region into which impurities are introduced at a low concentration and a semiconductor device having source / drain regions into which impurities having the second conductivity type are introduced are formed on the same substrate. At least after forming the semiconductor layer on the substrate, a portion of the semiconductor layer to be the LDD region and the L
A portion adjacent to the DD region and serving as a medium concentration region with respect to the impurity concentration of the source / drain region of the first conductivity type and a portion serving as the second conductivity type are covered with a mask. Introducing a conductive type impurity at a high concentration, and covering a portion to be the LDD region with a mask,
At least a step of introducing an impurity that becomes the first conductivity type at a medium concentration, and a step of introducing an impurity that becomes an LDD region at a low concentration after removing the mask of the portion that becomes the LDD. A method for manufacturing a semiconductor device. 6. The method for manufacturing a semiconductor device according to claim 5, wherein the step of introducing the impurity which becomes the first conductivity type at a high concentration at a high concentration is performed before forming a gate insulating film of the semiconductor device. A method of manufacturing a semiconductor device. 7. The method for manufacturing a semiconductor device according to claim 5, wherein at least a gate electrode of the semiconductor device of the second conductivity type is processed, and then the impurities of the second conductivity type are removed from the source / drain. A method for manufacturing a semiconductor device, comprising a step of introducing a semiconductor device into a region to be a region. 8. The method of manufacturing a semiconductor device according to claim 5, wherein the step of introducing the impurity of the first conductivity type into the intermediate concentration region includes at least a gate of the semiconductor device of the second conductivity type. A method of manufacturing a semiconductor device, comprising: after forming an electrode, forming a gate electrode of a semiconductor device of the first conductivity type. 9. The method of manufacturing a semiconductor device according to claim 5, wherein the step of introducing the impurity of the first conductivity type into the intermediate concentration region is performed before removing a mask material for processing a gate electrode. A method of manufacturing a semiconductor device. 10. The method of manufacturing a semiconductor device according to claim 5, wherein the step of introducing an impurity having a first conductivity type into the intermediate concentration region includes forming a gate with respect to a mask material for processing a gate electrode. Set the electrode width to 0.2 in the gate length direction.
A method of manufacturing a semiconductor device, comprising: performing overetching by at least 1.5 μm and before removing the mask. 11. The method of manufacturing a semiconductor device according to claim 5, wherein after removing a mask for introducing an impurity into the intermediate concentration region, the impurity having a first conductivity type is removed from the first conductivity type. A method for manufacturing a semiconductor device, characterized by introducing each gate electrode as a mask into at least both a semiconductor device to be used and a semiconductor device to be the second conductivity type. 12. The method of manufacturing a semiconductor device according to claim 5, wherein the semiconductor device having the first conductivity type is connected to the drain region and extends beyond an extraction electrode connected to the drain region. In a method of manufacturing a semiconductor device in which a capacitance is formed by an electrode or a wiring formed in the same layer as a gate electrode via a gate insulating film and the extension, at least the semiconductor layer of the extension and the semiconductor device A method for manufacturing a semiconductor device, comprising a step of simultaneously introducing impurities of a first conductivity type into a source / drain region. 13. A plurality of scanning lines, a plurality of data lines,
5. An electro-optical device having pixel electrodes and switching elements arranged in a matrix corresponding to intersections of the scanning lines and the data lines, wherein the switching elements are arranged in accordance with claim 1. An electro-optical device formed by a method for manufacturing a semiconductor device. 14. A plurality of scanning lines, a plurality of data lines,
An electro-optical device having pixel electrodes and switching elements arranged in a matrix corresponding to intersections of the scanning lines and the data lines, wherein the switching elements are in any one of claims 5 to 12. An electro-optical device formed by a method for manufacturing a semiconductor device. 15. An electronic apparatus comprising the electro-optical device according to claim 13.