CN107204376A - A kind of thin film transistor (TFT) and its manufacture method, array base palte, display device - Google Patents
A kind of thin film transistor (TFT) and its manufacture method, array base palte, display device Download PDFInfo
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- CN107204376A CN107204376A CN201710382452.4A CN201710382452A CN107204376A CN 107204376 A CN107204376 A CN 107204376A CN 201710382452 A CN201710382452 A CN 201710382452A CN 107204376 A CN107204376 A CN 107204376A
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- 239000010409 thin film Substances 0.000 title claims abstract description 78
- 238000000034 method Methods 0.000 title claims abstract description 38
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 150000002500 ions Chemical class 0.000 claims abstract description 109
- 239000000758 substrate Substances 0.000 claims description 39
- 239000012212 insulator Substances 0.000 claims description 35
- 230000004888 barrier function Effects 0.000 claims description 28
- -1 phosphorus Ion Chemical class 0.000 claims description 19
- 238000005468 ion implantation Methods 0.000 claims description 15
- 230000008569 process Effects 0.000 claims description 11
- 230000015572 biosynthetic process Effects 0.000 claims description 10
- 229910052796 boron Inorganic materials 0.000 claims description 10
- 230000008021 deposition Effects 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 5
- 239000011574 phosphorus Substances 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 3
- 238000000926 separation method Methods 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 89
- 230000000694 effects Effects 0.000 description 20
- 239000010408 film Substances 0.000 description 16
- 238000002347 injection Methods 0.000 description 13
- 239000007924 injection Substances 0.000 description 13
- 239000011229 interlayer Substances 0.000 description 12
- 230000007704 transition Effects 0.000 description 12
- 238000010586 diagram Methods 0.000 description 11
- 238000010884 ion-beam technique Methods 0.000 description 10
- 239000002184 metal Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 238000005036 potential barrier Methods 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 3
- 238000009825 accumulation Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000000903 blocking effect Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 241001269238 Data Species 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000000686 essence Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000005224 laser annealing Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000005622 photoelectricity Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
Abstract
The embodiments of the invention provide a kind of thin film transistor (TFT) and its manufacture method, array base palte, display device, it is related to display technology field.The thin film transistor (TFT) includes active layer, and active layer includes：Channel region, the first doped region and the second doped region；Second doped region is located at side of first doped region away from channel region, and Doped ions concentration of the Doped ions concentration more than the first doped region of the second doped region；Active layer also includes the 3rd doped region, and the 3rd doped region is located between channel region and the second doped region, wherein, the Doped ions concentration of the 3rd doped region is less than the Doped ions concentration of the first doped region.Technical scheme provided in an embodiment of the present invention can solve the problem that in the prior art the problem of the leakage current of thin film transistor (TFT) in the case of high bias voltage is larger.
Description
【Technical field】
The present invention relates to display technology field, more particularly to it is a kind of thin film transistor (TFT) and its manufacture method, array base palte, aobvious
Showing device.
【Background technology】
Because low temperature polycrystalline silicon has the advantages that higher electron mobility, faster response speed, good stability,
At present, using low temperature polycrystalline silicon as active layer more than the thin film transistor (TFT) applied in display device.
Fig. 1 is the structural representation of thin film transistor (TFT) of the prior art, as shown in figure 1, the thin film transistor (TFT) includes setting
The cushion 20 ' being placed on underlay substrate 10 ', is arranged at the active layer 30 ' on cushion 20 ', is arranged on active layer 30 '
Gate insulator 40 ', is arranged at the grid 50 ' on gate insulator 40 ', is arranged at the interlayer insulating film 60 ' on grid 50 ',
And the source electrode 70 ' on interlayer insulating film 60 ' and drain electrode 80 ' are arranged at, source electrode 70 ' and drain electrode 80 ' are respectively by through grid
The via 90 ' of insulating barrier and interlayer insulating film is connected with active layer 30 '.Wherein, active layer 30 ' includes channel region 31 ', positioned at ditch
Two doped regions (LDD, Lightly Doped Drain) 32 ' of the both sides of road area 31 ', and positioned at two doped regions 32 '
The remote side of channel region 31 ' two heavily doped regions 33 ', two heavily doped regions 33 ' be respectively used to and source electrode 70 ' and drain electrode
80 ' connections.
Inventors herein have recognized that, for the thin film transistor (TFT) with said structure, at which when closed mode,
Leakage current is larger in the case of high bias voltage, can influence the display effect of display device.Specifically, the larger main original of leakage current
Because as shown in Figures 2 and 3, Fig. 2 enters the energy level of channel region for the electronics of the interface accumulation between doped regions and channel region
Figure, Fig. 3 enters the energy diagram of channel region for the hole of the interface accumulation between doped regions and channel region, can by Fig. 2 and Fig. 3
Know, interface of the electronics between doped regions and channel region is largely accumulated, in the case where bias voltage is larger, portion of energy
Higher electronics can enter channel region with tunnelling, and the slightly lower electronics of portion of energy can transit to the energy gap defect state energy such as dangling bonds
Take and enter channel region, under similar circumstances, interface of the hole between drain electrode and channel region is largely accumulated, due to hole matter
Amount is heavier, and most of hole enters channel region by transitting to the energy gap such as dangling bonds defect state and can take, so as to cause low temperature many
Polycrystal silicon film transistor is in the case of high bias voltage, and leakage current is larger.
【The content of the invention】
In view of this, the embodiments of the invention provide a kind of thin film transistor (TFT) and its manufacture method, array base palte, display dress
Put, to solve in the prior art the problem of the leakage current of thin film transistor (TFT) in the case of high bias voltage is larger.
In a first aspect, the embodiment of the present invention provides a kind of thin film transistor (TFT), the thin film transistor (TFT) includes：
Active layer, the active layer includes：Channel region, the first doped region and the second doped region；
Second doped region is located at the side of first doped region away from the channel region, and second doped region
Doped ions concentration be more than first doped region Doped ions concentration；
The active layer also includes the 3rd doped region, and the 3rd doped region is located at the channel region and the described second doping
Between area, wherein, the Doped ions concentration of the 3rd doped region is less than the Doped ions concentration of first doped region.
Alternatively, first doped region includes the first sub- doped region and the second sub- doped region, the second sub- doped region
Positioned at the described first sub- doped region towards the side of second doped region,
3rd doped region is located between the described first sub- doped region and the second sub- doped region.
Further, the width of the described first sub- doped region in the first direction is more than the described second sub- doped region along described the
The width in one direction；
Wherein, the first direction is the channel region towards the direction of second doped region.
Alternatively, the 3rd doped region is located between first doped region and second doped region.
Alternatively, the 3rd doped region is located between the channel region and first doped region.
Alternatively, the 3rd doped region includes the 3rd sub- doped region and the 4th sub- doped region, wherein, the 3rd son is mixed
Miscellaneous area is located between the channel region and first doped region, and the 4th sub- doped region is located at first doped region and institute
State between the second doped region.
Alternatively, the 3rd doped region is in the block area of multiple separations in the plane parallel to the channel region surface
Domain.
Alternatively, gate insulator is set between the active layer and the grid, and the gate insulator includes first
Elevated regions；3rd doped region is first elevated regions where the underlay substrate on the direction of plane
Orthographic projection region.
Alternatively, gate insulator is set between the active layer and the grid, and the gate insulator includes second
Elevated regions；The channel region is second elevated regions where the underlay substrate on the direction of plane
Orthographic projection region；Where the underlay substrate on the direction of plane, the orthographic projection of the grid is located at described second
In the orthographic projection of elevated regions.
Alternatively, the Doped ions of first doped region are identical with the Doped ions of the 3rd doped region；Described
The Doped ions of one doped region are different from the Doped ions of second doped region.
Alternatively, the Doped ions of first doped region are phosphonium ion.
Further, the doping concentration of phosphonium ion is 1 × 10 in first doped region13~5 × 1013Individual/cm2；It is described
The doping concentration of phosphonium ion is 5 × 10 in 3rd doped region12~1 × 1013Individual/cm2。
Alternatively, the Doped ions of second doped region are boron ion.
Further, the doping concentration of boron ion is 5 × 10 in second doped region14~1 × 1015Individual/cm2。
Alternatively, the width range of the 3rd doped region in the first direction is：0.3μm—1μm；Wherein, described first
Direction is the channel region towards the direction of second doped region.
Alternatively, the channel region is channel doping polysilicon region.
Second aspect, the embodiment of the present invention provides a kind of array base palte, and the array base palte includes：Underlay substrate and to take up an official post
Thin film transistor (TFT) described in one.
The third aspect, the embodiment of the present invention provides a kind of display device, and the display device includes above-described array base
Plate.
Fourth aspect, the embodiment of the present invention provides a kind of manufacture method of thin film transistor (TFT), and methods described includes：In substrate
Grid, source electrode, drain electrode and active layer are formed on substrate；
Wherein, the method for forming the active layer, including：
By doping process, channel region is formed on the active layer, and, form first in the side of the channel region
Doped region, the second doped region and the 3rd doped region；
Wherein, second doped region is located at the side of first doped region away from the channel region, and described second
Doped ions concentration in doped region is more than the Doped ions concentration in first doped region；
3rd doped region is located between the channel region and second doped region, wherein, the 3rd doped region
In Doped ions concentration be less than first doped region Doped ions concentration.
Further, the doping process is ion implantation technology.
Alternatively, the method for forming the active layer, is specifically included：
Active layer is formed on the underlay substrate；Wherein, the active layer includes：Channel region, first area, the secondth area
Domain and the 3rd region；The second area is located at side of the first area away from the channel region, the 3rd region position
Between the channel region and the second area；
First time ion implanting is carried out, the second doped region is formed at the second area；
Deposition forms gate insulator on the active layer for forming second doped region, and the gate insulator includes the
One elevated regions and the second elevated regions；Wherein, on the direction of plane, described first is convex where the underlay substrate
The orthographic projection and the orthographic projection in the 3rd region for playing region are completely superposed, also, the channel region is second convex area
Domain in the orthographic projection region where the underlay substrate on the direction of plane；
Deposition forms grid in the range of the second elevated regions on the gate insulator so that perpendicular to the substrate
Where substrate on the direction of plane, the orthographic projection of the grid is located in the orthographic projection of second elevated regions；
Second of ion implanting is carried out, the first doped region is formed at the first area, and at the 3rd region
The 3rd doped region is formed, to cause the Doped ions concentration of the 3rd doped region to be less than the Doped ions of first doped region
Concentration, and Doped ions concentration of the Doped ions concentration less than second doped region of first doped region.
Alternatively, the Doped ions of the first time ion implanting are boron ion；The doping of second of ion implanting
Ion is phosphonium ion.
Thin film transistor (TFT) provided in an embodiment of the present invention and its manufacture method, array base palte, display device, the film crystal
Pipe includes active layer, and active layer includes channel region, the first doped region and the second doped region；Second doped region is located at the first doped region
Side away from channel region, and Doped ions concentration of the Doped ions concentration more than the first doped region of the second doped region；It is active
Layer also include the 3rd doped region, the 3rd doped region be located between channel region and the second doped region, and then cause carrier (electronics or
Person hole) before the interface of channel region and the first doped region is reached, it is necessary to first pass through the first doped region and the 3rd doped region
Between interface, due to the 3rd doped region Doped ions concentration be less than the first doped region Doped ions concentration, therefore, current-carrying
Son at the interface between by the first doped region and the 3rd doped region, it is necessary to across a larger potential barrier, and then to current-carrying
Son serves certain barrier effect, can effectively be reduced to the carrier up to channel region, so reduce subsequently through transition and/
Or tunnelling enters the number of the carrier of channel region, play a part of reducing leakage current.
【Brief description of the drawings】
In order to illustrate the technical solution of the embodiments of the present invention more clearly, below will be attached to what is used required in embodiment
Figure is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for this area
For those of ordinary skill, without having to pay creative labor, it can also be obtained according to these accompanying drawings other attached
Figure.
Fig. 1 is the schematic cross-section of thin film transistor (TFT) in the prior art；
Fig. 2 is the energy level that electronics is entered channel region by high-doped zone when thin film transistor (TFT) is closed in the prior art
Figure；
Fig. 3 is the energy level that hole is entered channel region by high-doped zone when thin film transistor (TFT) is closed in the prior art
Figure；
Fig. 4 is the schematic cross-section one of thin film transistor (TFT) in the embodiment of the present invention；
Fig. 5 is the schematic cross-section one of active layer in the embodiment of the present invention；
Fig. 6 be in active layer when thin film transistor (TFT) is closed in the embodiment of the present invention shown in Fig. 5 electronics by
Two doped regions enter the energy diagram of channel region；
Fig. 7 is the schematic cross-section two of active layer in the embodiment of the present invention；
Fig. 8 be in active layer when thin film transistor (TFT) is closed in the embodiment of the present invention shown in Fig. 7 electronics by
Two doped regions enter the energy diagram of channel region；
Fig. 9 is the schematic cross-section three of active layer in the embodiment of the present invention；
Figure 10 be in active layer when thin film transistor (TFT) is closed in the embodiment of the present invention shown in Fig. 9 electronics by
Two doped regions enter the energy diagram of channel region；
Figure 11 is the schematic cross-section four of active layer in the embodiment of the present invention；
Figure 12 be in active layer when thin film transistor (TFT) is closed in the embodiment of the present invention shown in Figure 11 electronics by
Second doped region enters the energy diagram of channel region；
Figure 13 is the top view of the 3rd doped region in the embodiment of the present invention；
Figure 14 is the schematic cross-section two of thin film transistor (TFT) in the embodiment of the present invention；
Figure 15 is the top view of active layer in the embodiment of the present invention；
Figure 16 is the top view of display device in the embodiment of the present invention；
Figure 17 is the method flow diagram of formation active layer in the embodiment of the present invention；
Figure 18 is the corresponding structure chart of each step of formation active layer in the embodiment of the present invention.
【Embodiment】
In order to be better understood from technical scheme, the embodiment of the present invention is retouched in detail below in conjunction with the accompanying drawings
State.
It will be appreciated that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.Base
Embodiment in the present invention, those of ordinary skill in the art obtained under the premise of creative work is not made it is all its
Its embodiment, belongs to the scope of protection of the invention.
The term used in embodiments of the present invention is the purpose only merely for description specific embodiment, and is not intended to be limiting
The present invention." one kind ", " described " and "the" of singulative used in the embodiment of the present invention and appended claims
It is also intended to including most forms, unless context clearly shows that other implications.
It will be appreciated that though XXX may be described using term first, second, third, etc. in embodiments of the present invention, but
These XXX should not necessarily be limited by these terms.These terms are only used for XXX being distinguished from each other out.For example, not departing from implementation of the present invention
In the case of example scope, the first XXX can also be referred to as the 2nd XXX, similarly, and the 2nd XXX can also be referred to as the first XXX.
In a first aspect, the embodiment of the present invention provides a kind of thin film transistor (TFT), specifically, as shown in figure 4, Fig. 4 is the present invention
The schematic cross-section one of thin film transistor (TFT) in embodiment, the thin film transistor (TFT) include active layer 1, active layer 1 include channel region 10,
First doped region 11 and the second doped region 12；Second doped region 12 is located at the first side of the doped region 11 away from channel region 10, and
The Doped ions concentration of second doped region 12 is more than the Doped ions concentration of the first doped region 11；Active layer 1 is also mixed including the 3rd
Miscellaneous area 13, the 3rd doped region 13 is located between the doped region 12 of channel region 10 and second, wherein, the Doped ions of the 3rd doped region 13
Concentration is less than the Doped ions concentration of the first doped region 11.Alternatively, the width range of the 3rd doped region 13 in the first direction is：
0.3μm—1μm；Wherein, first direction is channel region 10 towards the direction of the second doped region 12.
Wherein, the second doped region 12 is used to be attached with source electrode or drain electrode, due in the first doped region the 11~the 3rd
In doped region 13, the doping concentration of the second doped region 12 is maximum, and carrier concentration is maximum, and then can effectively reduce active layer 1
With source electrode or the contact resistance of drain electrode, the performance of thin film transistor (TFT) is lifted；The doping concentration of first doped region 11 is less than second
The doping concentration of doped region 12, carrier concentration is smaller, and resistance is larger, and then can be closed in thin film transistor (TFT)
When, reduce the leakage current of thin film transistor (TFT)；The Doped ions concentration of 3rd doped region 13 be less than the first doped region 11 doping from
Sub- concentration, therefore, carrier (electronics or hole) at the interface between by the first doped region 11 and the 3rd doped region 13,
Need across a larger potential barrier, and then certain barrier effect is served to carrier, can effectively be reduced to up to raceway groove
The carrier in area 10, and then reduce the number for the carrier for entering channel region 10 subsequently through transition and/or tunnelling, play into one
Step reduces the effect of leakage current.
You need to add is that, as shown in figure 4, the thin film transistor (TFT) also includes the cushion 2 being arranged on underlay substrate 0,
Active layer 1 is arranged on cushion 2, is arranged at the gate insulator 3 on active layer 1, is arranged at the grid on gate insulator 3
4, it is arranged at the interlayer insulating film 5 on grid 4, and the source electrode 6 being arranged on interlayer insulating film 5 and drain electrode 7, source electrode 6 and leakage
Pole 7 is connected by two the second doped regions 12 of the via 8 through gate insulator 3 and interlayer insulating film 5 and active layer 1 respectively
Connect.Wherein, the effect of cushion 2 is not only to completely cut off underlay substrate 0 with active layer 1, it is to avoid miscellaneous in underlay substrate 0
Matter enters active layer 1, influences the performance of active layer 1, can also reduce the thermal diffusion between active layer 1 and underlay substrate 0, reduces
The high temperature that the technique (for example, quasi-molecule laser annealing technique) used during active layer 1 is made is produced is to underlay substrate 0
The influence of generation.The material of cushion 2 can be silica or silicon nitride.
Alternatively, as shown in figure 4, the thin film transistor (TFT) also includes light-shielding structure 9, light-shielding structure 9 is located on underlay substrate 0
And it is corresponding with the position of the channel region 11 of active layer 1, cushion 2 is covered on light-shielding structure 9, and light-shielding structure 9 can be effective
Block the light projected by backlight module, it is to avoid because some light is irradiated on channel region 11, channel region 11 is produced photoelectricity
Effect, influence is produced on the electric property of channel region 11.
The embodiment of the present invention includes to active layer 1 below channel region 10, the first doped region 11, the second doped region 12 and
The relative position of 3rd doped region 13 carries out citing description, and those skilled in the art are not paying creative labor based on herein below
The other embodiment obtained on the premise of dynamic, is belonged within the application protection domain.
Example one, as shown in figure 5, Fig. 5 is the schematic cross-section one of active layer in the embodiment of the present invention, the first doped region 11 is wrapped
The first sub- sub- doped region 11b of doped region 11a and second are included, the second sub- doped region 11b is located at the first sub- doped region 11a towards second
The side of doped region 12, the 3rd doped region 13 is located between the first sub- sub- doped region 11b of doped region 11a and second.When active layer 1
During with this structure, when thin film transistor (TFT) is closed, the transition of carrier therein and/tunnelling mode as shown in fig. 6,
Fig. 6 be in active layer when thin film transistor (TFT) is closed in the embodiment of the present invention shown in Fig. 5 electronics by the second doped region
Into the energy diagram of channel region, Fig. 6 only by carrier be electronics exemplified by illustrate, five regions in Fig. 6 from left to right according to
Secondary correspondence channel region 10, the first sub- doped region 11a, the 3rd doped region 13, the second sub- doped region 11b and the second doped region 12, by
Fig. 6 understands that electronics is before channel region 10 is reached, it is necessary to first across the second sub- doped region 11b, the 3rd doped region 13 and the first son
Doped region 11a, the doping concentration of the 3rd doped region 13 is less than the second sub- sub- doped region 11a of doped region 11b and first, and the first son is mixed
The miscellaneous sub- doped region 11b of area 11a and second doping concentration is less than the doping concentration of the second doped region 12, and then causes the 3rd doping
The barrier height in area 13 is higher than the second sub- sub- doped region 11a of doped region 11b and first barrier height, the second sub- doped region 11b
It is higher than the barrier height of the second doped region 12, the 3rd doped region the 13, second son doping with the first sub- doped region 11a barrier height
The sub- doped region 11a of area 11b and first serve certain barrier effect to electronics, wherein the barrier effect of the 3rd doped region 13 is outstanding
To be obvious, the carrier up to channel region 10 can be effectively reduced to, and then reduces and enters raceway groove subsequently through transition and/or tunnelling
The number of the carrier in area 10, plays a part of reducing leakage current.
Further, as shown in figure 5, the first sub- doped region 11a in the first direction x width be more than the second sub- doped region
11b x in the first direction width；Wherein, first direction x is channel region 10 towards the direction of the second doped region 12.It is arranged such
Can cause the 3rd doped region 13 be located between the doped region 12 of channel region 10 and second more in the middle of position, and then cause the
Three doped regions 13 are preferable to the blocking effect of carrier, and the effect for reducing leakage current is preferable.
Example two, as shown in fig. 7, Fig. 7 is the schematic cross-section two of active layer in the embodiment of the present invention, the 3rd doped region 13
Between the first doped region 11 and the second doped region 12.When active layer 1 has this structure, thin film transistor (TFT) is closed
When, the transition of carrier therein and/tunnelling mode are as shown in figure 8, Fig. 8 is that thin film transistor (TFT) is in and closed in the embodiment of the present invention
Electronics is entered the energy diagram of channel region by the second doped region in active layer during closed state shown in Fig. 7, and Fig. 8 is only using carrier as electricity
Illustrated exemplified by son, four regions in Fig. 8 from left to right are corresponding in turn to channel region 10, the first doped region 11, the 3rd doping
The doped region 12 of area 13 and second, as shown in Figure 8, electronics is before channel region 10 is reached, it is necessary to first cross over the He of the 3rd doped region 13
First doped region 11, the doping concentration of the 3rd doped region 13 is less than the first doped region 11, and the doping concentration of the first doped region 11 is small
In the second doped region 12, and then the barrier height of the 3rd doped region 13 is caused to be higher than the barrier height of the first doped region 11, first
The barrier height of doped region 11 is higher than the barrier height of the second doped region 12, and the 3rd doped region 13 and the first doped region 11 are to electronics
Certain barrier effect is served, wherein the barrier effect of the 3rd doped region 13 is particularly evident, can be effectively reduced to up to raceway groove
The carrier in area 10, and then reduce the number for the carrier for entering channel region 10 subsequently through transition and/or tunnelling, play reduction
The effect of leakage current.
Example three, as shown in figure 9, Fig. 9 is the schematic cross-section three of active layer in the embodiment of the present invention, the 3rd doped region 13
Between the doped region 11 of channel region 10 and first.When active layer 1 has this structure, when thin film transistor (TFT) is closed,
As shown in Figure 10, Figure 10 is that thin film transistor (TFT) is in and closed in the embodiment of the present invention for the transition of carrier therein and/tunnelling mode
In active layer during closed state shown in Fig. 9 electronics by the second doped region enter channel region energy diagram, Figure 10 only using carrier as
Illustrated exemplified by electronics, four regions in Figure 10 from left to right are corresponding in turn to channel region 10, the 3rd doped region 13, first mixed
The miscellaneous doped region 12 of area 11 and second, as shown in Figure 10, electronics is before channel region 10 is reached, it is necessary to first cross over the first doped region 11
With the 3rd doped region 13, the doping concentration of the first doped region 11 is less than the doping concentration of the second doped region 12, the 3rd doped region 13
Doping concentration be less than the first doped region 11, and then cause the 3rd doped region 13 barrier height be higher than the first doped region 11 gesture
Height is built, the barrier height of the first doped region 11 is higher than the barrier height of the second doped region 12, and the 3rd doped region 13 and first is mixed
Miscellaneous area 11 serves certain barrier effect to electronics, wherein, the barrier effect of the 3rd doped region 13 is particularly evident, can be effective
The carrier up to channel region 10 is reduced to, and then reduction enters the carrier of channel region 10 subsequently through transition and/or tunnelling
Number, plays a part of reducing leakage current.
Example four, as shown in figure 11, Figure 11 are the schematic cross-section four of active layer in the embodiment of the present invention, the 3rd doped region 13
Including the 3rd sub- sub- doped region 13b of doped region 13a and the 4th, wherein, the 3rd sub- doped region 13a mixes positioned at channel region 10 with first
Between miscellaneous area 11, the 4th sub- doped region 13b is located between the first doped region 11 and the second doped region 12.When active layer 1 has this
During structure, when thin film transistor (TFT) is closed, the transition of carrier therein and/tunnelling mode are as shown in figure 12, Figure 12
It is that electronics is entered by the second doped region in active layer when thin film transistor (TFT) is closed in the embodiment of the present invention shown in Figure 11
Enter the energy diagram of channel region, Figure 12 is only illustrated so that carrier is electronics as an example, five regions in Figure 12 from left to right according to
Secondary correspondence channel region 10, the 3rd sub- doped region 13a, the first doped region 11, the 4th sub- doped region 13b and the second doped region 12, by
Figure 12 understands that electronics is before channel region 10 is reached, it is necessary to first cross over the 4th sub- doped region 13b, the first doped region 11 and the 3rd
Sub- doped region 13a, wherein, the 3rd sub- sub- doped region 13b of doped region 13a and the 4th doping concentration is less than the first doped region 11
With the second doped region 12, and then cause the 3rd sub- sub- doped region 13b of doped region 13a and the 4th barrier height higher than first doping
The barrier height of the doped region 12 of area 11 and second, the 3rd sub- sub- doped region 13b of doped region 13a and the 4th are served necessarily to electronics
Barrier effect, can effectively be reduced to the carrier up to channel region 10, and then reduce and enter subsequently through transition and/or tunnelling
The number of the carrier of channel region 10, plays a part of reducing leakage current.
It should be noted that in the embodiment shown in example two, the second doped region 12 with highest doping concentration with
The 3rd doped region 13 with minimum doping concentration is disposed adjacent, and because doping concentration difference therebetween is larger, resistance is dashed forward
Become very big, and generally the two doping for different elements, and then can make it that the depletion layer of PN junction formed therebetween is too thin, quilt
Carrier is passed through and easily PN junction damaged then, and then cause the performance of active layer 1 to be affected；In the implementation shown in example three
In mode, although the second doped region 12, the first doped region 11 and the 3rd doped region 13 are set gradually, sudden change of resistivity is little, current-carrying
Son will not be damaged after to the PN junction formed the second doped region 12 and the first doped region 11, but the 3rd doped region 13
Set location it is more inclined, and then can cause reduce leakage current effect it is poor；In the embodiment shown in example four, the 3rd doping
Area 13 includes the 3rd sub- sub- doped region 13b of doped region 13a and the 4th, wherein the 3rd sub- sub- doped region 13b of doped region 13a and the 4th
The equal very little of carrier concentration, resistance is very big, and present inventor passes through exploration discovery, sets multiple resistance very big region
When, the reduction of leakage current is only than setting a resistance very big region to have faint advantage, but thin film transistor (TFT) can be in
Operating current during ON state causes larger reduction；And the embodiment in example one can effectively mitigate or avoid above-mentioned various
The appearance of situation, therefore, the embodiment in the embodiment of the present invention in preference one, i.e. the first doped region 11 are mixed including the first son
The miscellaneous sub- doped region 11b of area 11a and second, the second sub- doped region 11b are located at the first sub- doped region 11a towards the second doped region 12
Side, the 3rd doped region 13 is located between the first sub- sub- doped region 11b of doped region 11a and second.
Alternatively, as shown in figure 13, Figure 13 is the top view of the 3rd doped region in the embodiment of the present invention, the 3rd doped region 13
In the boxed area 130 of multiple separations in the plane parallel to channel region surface.Being arranged such can not only to work as film
When transistor is closed, carrier by the 3rd doped region 13 reach channel region 10 during, carrier on
To a boxed area A, its direction of advance will be changed, and then the course of carrier can be increased, and it is reached
The possibility of channel region 10 will be reduced, and can preferably reduce leakage current.
The embodiment of the present invention includes to active layer 1 below channel region 10, the first doped region 11, the second doped region 12 and
The doping way of 3rd doped region 13 carries out citing description, and those skilled in the art are not paying creative labor based on herein below
The other embodiment obtained on the premise of dynamic, is belonged within the application protection domain.
Alternatively, the Doped ions of the first doped region 11 are identical with the Doped ions of the 3rd doped region 13；First doped region
11 Doped ions are different from the Doped ions of the second doped region 12, so as to can not only cause the first doped region 11 and the 3rd to mix
Miscellaneous area 13 can be carried out in a doping process (for example, ion implantation technology), simplify the manufacture craft of thin film transistor (TFT), and
And can also make between the first doped region 11 and the second doped region 12, or, between the 3rd doped region 13 and the second doped region 12
PN junction is formed, setting for the PN junction can not influence it opening while the leakage current of thin film transistor (TFT) in off position is reduced
Operating current during state.
Exemplarily, the Doped ions of the first doped region 11 are phosphorus (P) ion, and the Doped ions of the 3rd doped region 13 are also
Phosphorus (P) ion.The doping concentration of phosphonium ion is 1 × 10 in first doped region13~5 × 1013Individual/cm2.Phosphorus in 3rd doped region 13
The doping concentration of ion is 5 × 1012~1 × 1013Individual/cm2.The first doped region 11 is doped when using ion implantation technology
When, the energy of ion beam is 55Kev, when being doped using ion implantation technology to the 3rd doped region 13, the energy of ion beam
Measure as 55Kev.First doped region 11 and the 3rd doped region 13 can be by being doped acquisition in primary ions injection technology.
Exemplarily, the Doped ions of the second doped region 12 are boron (B) ion.The doping of boron ion in second doped region 12
Concentration is 5 × 1014~1 × 1015Individual/cm2.When being doped using ion implantation technology to the second doped region 12, ion beam
Energy be 25Kev.
Alternatively, channel region 10 is channel doping polysilicon region.Exemplarily, the Doped ions of channel region 10 be B from
Son, doping concentration is 1 × 1012~5 × 1012Individual/cm2, when being doped using ion implantation technology to channel region 10, ion
The energy of beam is 8Kev.
From described above, the first doped region 11 and the 3rd doped region 13 can be by entering in primary ions injection technology
Row doping is obtained, and based on this, the embodiment of the present invention provides a kind of optional technical scheme：As shown in figure 14, active layer 1 and grid
Gate insulator 3 is set between 4, and gate insulator 3 includes the first elevated regions 31；3rd doped region 13 is the first elevated regions
The 31 orthographic projection region on the direction perpendicular to the place plane of underlay substrate 0.So that in ion implantation process, the 3rd
The position of the corresponding gate insulator 3 of doped region 13 is the first elevated regions 31, and the thickness ratio first of the first elevated regions 31 is mixed
The thickness of the corresponding part of gate insulator 3 in miscellaneous area 11 is big so that the stop of the ion of the first 31 pairs of elevated regions injection is more than
Stop of the corresponding part of gate insulator 3 of first doped region 11 to the ion of injection, and then cause the 3rd doped region 13 of injection
Ion amount be less than the first doped region 11 of injection ion amount, realizing the first doped region 11 and the 3rd doped region 13 can be with
By being doped acquisition in primary ions injection technology.
In addition, in order to mitigate in the process by ion implantation technology the first doped region 11 of formation and the 3rd doped region 13
In, influence of the ion beam to channel region 10, alternatively, as shown in figure 14, Figure 14 is thin film transistor (TFT) in the embodiment of the present invention
Schematic cross-section two, sets gate insulator 3 between active layer 1 and grid 4, gate insulator 3 includes the second elevated regions 32；
Channel region 11 is the orthographic projection region on the direction perpendicular to the place plane of underlay substrate 0 of the second elevated regions 32；Hanging down
Directly on the direction of the place plane of underlay substrate 0, the orthographic projection of grid 4 is located in the orthographic projection of the second elevated regions 32.And then
So that the thickness of corresponding second elevated regions 32 of channel region 11 is larger, Jin Erke preferable to the blocking effect of the ion of injection
To mitigate during by ion implantation technology the first doped region 11 of formation and the 3rd doped region 13, ion beam is to channel region
10 influence.
Further optionally, the thin film transistor (TFT) in the embodiment of the present invention can have channel configuration, thin film transistor (TFT)
As shown in figure 15, Figure 15 is the top view of active layer in the embodiment of the present invention to the top view of active layer 1, wherein, active layer 1 includes
Two channel regions 10, the both sides of each channel region 10 are correspondingly arranged on the 3rd doped region 13, the first doped region 11 and second and mixed
Miscellaneous area 12, is arranged such the leakage current that can aid in and further reduce thin film transistor (TFT).
Second aspect, the embodiment of the present invention provides a kind of array base palte, and the array base palte includes：Underlay substrate and to take up an official post
Thin film transistor (TFT) described in one.Array base palte also includes a plurality of grid line laterally set, and longitudinally disposed many datas
Line, the two, which is limited, is provided with a thin film transistor (TFT) and a pixel electrode in multiple pixel cells, each pixel cell,
The source electrode of thin film transistor (TFT) is connected with data wire, and drain electrode is connected with pixel electrode, and grid is connected with grid line.Applied when on a grid line
Plus after scanning signal, its a line thin film transistor (TFT) connected is opened, and the data-signal on each data wire is write to corresponding pixel
In electrode.
The third aspect, the embodiment of the present invention provides a kind of display device, as shown in figure 16, during Figure 16 is the embodiment of the present invention
The top view of display device, the display device includes above-described array base palte 100.The display dress that the embodiment of the present application is provided
Putting can be such as smart mobile phone, wearable intelligent watch, intelligent glasses, tablet personal computer, television set, display, notebook
Any product or portion with display function such as computer, DPF, navigator, Vehicular display device, electrophoretic display device (EPD), e-book
Part.The embodiment of the present application provide display panel and display device can for flexibility, or it is non-flexible, the application to this not
Limit.
Fourth aspect, the embodiment of the present invention provides a kind of manufacture method of thin film transistor (TFT), and methods described includes：In substrate
Grid, source electrode, drain electrode and active layer are formed on substrate；Wherein, the method for forming active layer, including：By doping process, having
Channel region is formed in active layer, and, form the first doped region, the second doped region and the 3rd doped region in the side of channel region；Its
In, as shown in figure 4, the second doped region 12 is located at the first side of the doped region 11 away from channel region 10, and in the second doped region 12
Doped ions concentration be more than the first doped region 11 in Doped ions concentration；3rd doped region 13 is located at channel region 10 and second
Between doped region 12, wherein, the Doped ions concentration in the 3rd doped region 13 is less than the Doped ions concentration of the first doped region 11.
Wherein, the second doped region 12 is used to be attached with source electrode or drain electrode, due in the first doped region the 11~the 3rd
In doped region 13, the doping concentration of the second doped region 12 is maximum, and carrier concentration is maximum, and then can effectively reduce active layer 1
With source electrode or the contact resistance of drain electrode, the performance of thin film transistor (TFT) is lifted；The doping concentration of first doped region 11 is less than second
The doping concentration of doped region 12, carrier concentration is smaller, and resistance is larger, and then can be closed in thin film transistor (TFT)
When, reduce the leakage current of thin film transistor (TFT)；The Doped ions concentration of 3rd doped region 13 be less than the first doped region 11 doping from
Sub- concentration, therefore, carrier (electronics or hole) at the interface between by the first doped region 11 and the 3rd doped region 13,
Need across a larger potential barrier, and then certain barrier effect is served to carrier, can effectively be reduced to up to raceway groove
The carrier of the interface of the doped region 11 of area 10 and first, it is to avoid carrier is in the interface of the doped region 11 of channel region 10 and first
A large amount of accumulation, and then reduce the number for the carrier for entering channel region 10 subsequently through transition and/or tunnelling, play further
Reduce the effect of leakage current.
Alternatively, above-mentioned doping process is ion implantation technology.Ion implantation technology refers in a vacuum, under low temperature, make
Doped ions accelerate to form ion beam, ion beam directive is treated doped structure, and ion beam is mapped to after doped structure, is treated
The resistance of doped structure and speed slowly lowers, and eventually settle at and treat in doped structure.Ion implantation technology has energy
Accumulated dose, depth profile and the surface uniformity of accurate control impurity, and be that low temperature process (can prevent spreading again for original impurity
Deng), while the advantage of self-aligned technology (to reduce capacity effect) can be realized.
Alternatively, as shown in Figure 17 and Figure 18, Figure 17 is the method flow diagram of formation active layer in the embodiment of the present invention, figure
18 be the corresponding structure chart of each step of formation active layer in the embodiment of the present invention, and the method for above-mentioned formation active layer is specifically wrapped
Include：
Step S1, active layer is formed on underlay substrate；Wherein, active layer includes：Channel region 10, first area A, second
Region B and the 3rd region C；Second area B is located at sides of the first area A away from channel region 10, and the 3rd region C is located at channel region
Between 10 and second area B.
Step S2, progress first time ion implanting, form the second doped region 12 at second area B.
Step S3, formed the second doped region 12 active layer 1 on deposition form gate insulator 3, gate insulator 3 is wrapped
Include the first elevated regions 31 and the second elevated regions 32；Wherein, on the direction perpendicular to the place plane of underlay substrate 0, first
The orthographic projection of elevated regions 31 and the 3rd region C orthographic projection are completely superposed, also, channel region 10 is the second elevated regions 32
Orthographic projection region on the direction perpendicular to the place plane of underlay substrate 0.
In the range of the second elevated regions 32 on step S4, gate insulator 3 deposition form grid 4 so that perpendicular to
On the direction of the place plane of underlay substrate 0, the orthographic projection of grid 4 is located in the orthographic projection of the second elevated regions 32.
Step S5, second of ion implanting of progress, form the first doped region 11 at the A of first area, and in the 3rd region C
Place forms the 3rd doped region 13, to cause the Doped ions concentration of the 3rd doped region 13 to be less than the Doped ions of the first doped region 11
Concentration, and Doped ions concentration of the Doped ions concentration less than the second doped region 12 of the first doped region 11.In the second secondary ion
In injection process, the position of the corresponding gate insulators 3 of the 3rd region C is the first elevated regions 31, the first elevated regions 31
The thickness of the corresponding parts of gate insulator 3 of thickness ratio first area A is big so that the ion of the first 31 pairs of elevated regions injection
Stop and be more than stop of the A corresponding parts of gate insulator 3 in first area to the ion of injection, and then cause the 3rd region of injection
The amount of C ion is less than the amount of injection first area A ion, and then forms the first doped region 11 and the 3rd doped region 13, and
The Doped ions concentration of 3rd doped region 13 is less than the Doped ions concentration of the first doped region 11.
Alternatively, the Doped ions of first time ion implanting are boron ion；The Doped ions of second of ion implanting are phosphorus
Ion.Exemplarily, the energy of first time ion implantation technology intermediate ion beam is boron in 25Kev, the second doped region 12 of formation
The doping concentration of ion is 5 × 1014~1 × 1015Individual/cm2；The energy of second of ion implantation technology intermediate ion beam is 55Kev,
The doping concentration of phosphonium ion is 1 × 10 in the first doped region formed13~5 × 1013Individual/cm2, in the 3rd doped region 13 of formation
The doping concentration of phosphonium ion is 5 × 1012~1 × 1013Individual/cm2。
You need to add is that, described from before, as shown in figure 4, thin film transistor (TFT) includes being arranged on underlay substrate 0
Light-shielding structure 9, the cushion 2 on light-shielding structure 9, active layer 1 is arranged on cushion 2, is arranged on active layer 1
Gate insulator 3, is arranged at the grid 4 on gate insulator 3, is arranged at the interlayer insulating film 5 on grid 4, and be arranged at
Source electrode 6 and drain electrode 7 on interlayer insulating film 5, source electrode 6 and drain electrode 7 are respectively by through gate insulator 3 and interlayer insulating film 5
Via 8 be connected with two the second doped regions 12 of active layer 1, light-shielding structure 9 is relative with the position of the channel region 11 of active layer 1
Should.For the thin film transistor (TFT) with said structure, exemplarily, its manufacture method can specifically include：On underlay substrate
Light shield layer is formed, light shield layer is patterned, light-shielding structure is formed；Form cushion；Form active layer；Form gate insulator
Layer；Gate metal layer is formed, gate metal layer is patterned, grid is formed；Form interlayer insulating film；Formed and run through grid
Two vias of insulating barrier and interlayer insulating film；Source-drain electrode metal level is formed, source-drain electrode metal level is patterned, source is formed
Pole and drain electrode, source electrode and drain electrode pass through two second of the via through gate insulator and interlayer insulating film and active layer respectively
Doped region is connected.
Thin film transistor (TFT) provided in an embodiment of the present invention and its manufacture method, array base palte, display device, the film crystal
Pipe includes active layer, and active layer includes channel region, the first doped region and the second doped region；Second doped region is located at the first doped region
Side away from channel region, and Doped ions concentration of the Doped ions concentration more than the first doped region of the second doped region；It is active
Layer also include the 3rd doped region, the 3rd doped region be located between channel region and the second doped region, and then cause carrier (electronics or
Person hole) before the interface of channel region and the first doped region is reached, it is necessary to first pass through the first doped region and the 3rd doped region
Between interface, due to the 3rd doped region Doped ions concentration be less than the first doped region Doped ions concentration, therefore, electronics
Or hole at the interface between by the first doped region and the 3rd doped region, it is necessary to across a larger potential barrier, and then
Certain barrier effect is served to carrier, the carrier up to channel region can be effectively reduced to, so reduce subsequently through
Transition and/or tunnelling enter the number of the carrier of channel region, play a part of reducing leakage current.
The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention
God is with principle, and any modification, equivalent substitution and improvements done etc. should be included within the scope of protection of the invention.
Claims (22)
1. a kind of thin film transistor (TFT), it is characterised in that including：
Active layer, the active layer includes：Channel region, the first doped region and the second doped region；
Second doped region is located at the side of first doped region away from the channel region, and second doped region is mixed
Heteroion concentration is more than the Doped ions concentration of first doped region；
The active layer also includes the 3rd doped region, the 3rd doped region be located at the channel region and second doped region it
Between, wherein, the Doped ions concentration of the 3rd doped region is less than the Doped ions concentration of first doped region.
2. thin film transistor (TFT) according to claim 1, it is characterised in that
First doped region includes the first sub- doped region and the second sub- doped region, and the second sub- doped region is located at described first
Sub- doped region towards the side of second doped region,
3rd doped region is located between the described first sub- doped region and the second sub- doped region.
3. thin film transistor (TFT) according to claim 2, it is characterised in that
The width of the first sub- doped region in the first direction is more than width of the described second sub- doped region along the first direction；
Wherein, the first direction is the channel region towards the direction of second doped region.
4. thin film transistor (TFT) according to claim 1, it is characterised in that
3rd doped region is located between first doped region and second doped region.
5. thin film transistor (TFT) according to claim 1, it is characterised in that
3rd doped region is located between the channel region and first doped region.
6. thin film transistor (TFT) according to claim 1, it is characterised in that the 3rd doped region includes the 3rd sub- doped region
With the 4th sub- doped region, wherein,
The 3rd sub- doped region is located between the channel region and first doped region, and the 4th sub- doped region is located at institute
State between the first doped region and second doped region.
7. the thin film transistor (TFT) according to claim 1-6, it is characterised in that the 3rd doped region is parallel to the ditch
It is in the boxed area of multiple separations in the plane on Dao Qu surfaces.
8. thin film transistor (TFT) according to claim 1, it is characterised in that grid are set between the active layer and the grid
Pole insulating barrier, the gate insulator includes the first elevated regions；
3rd doped region be first elevated regions where the underlay substrate on the direction of plane just
View field.
9. thin film transistor (TFT) according to claim 1, it is characterised in that grid are set between the active layer and the grid
Pole insulating barrier, the gate insulator includes the second elevated regions；
The channel region is second elevated regions in the positive throwing where the underlay substrate on the direction of plane
Shadow zone domain；
Where the underlay substrate on the direction of plane, the orthographic projection of the grid is located at second elevated regions
Orthographic projection in.
10. thin film transistor (TFT) according to claim 1, it is characterised in that the Doped ions of first doped region and institute
The Doped ions for stating the 3rd doped region are identical；The Doped ions of the Doped ions of first doped region and second doped region
It is different.
11. thin film transistor (TFT) according to claim 10, it is characterised in that the Doped ions of first doped region are phosphorus
Ion.
12. thin film transistor (TFT) according to claim 11, it is characterised in that the doping of phosphonium ion in first doped region
Concentration is 1 × 1013~5 × 1013Individual/cm2；The doping concentration of phosphonium ion is 5 × 10 in 3rd doped region12~1 × 1013
Individual/cm2。
13. thin film transistor (TFT) according to claim 10, it is characterised in that the Doped ions of second doped region are boron
Ion.
14. thin film transistor (TFT) according to claim 13, it is characterised in that the doping of boron ion in second doped region
Concentration is 5 × 1014~1 × 1015Individual/cm2。
15. thin film transistor (TFT) according to claim 1, it is characterised in that the width of the 3rd doped region in the first direction
Spending scope is：0.3μm—1μm；
Wherein, the first direction is the channel region towards the direction of second doped region.
16. thin film transistor (TFT) according to claim 1, it is characterised in that the channel region is channel doping multi-crystal silicon area
Domain.
17. a kind of array base palte, it is characterised in that the array base palte includes：Underlay substrate and such as claim 1 to 16 are any
Thin film transistor (TFT) described in.
18. a kind of display device, it is characterised in that the display device includes array base palte as claimed in claim 17.
19. a kind of manufacture method of thin film transistor (TFT), it is characterised in that methods described includes：On underlay substrate formed grid,
Source electrode, drain electrode and active layer；
Wherein, the method for forming the active layer, including：
By doping process, channel region is formed on the active layer, and, form first in the side of the channel region and adulterate
Area, the second doped region and the 3rd doped region；
Wherein, second doped region is located at the side of first doped region away from the channel region, and second doping
Doped ions concentration in area is more than the Doped ions concentration in first doped region；
3rd doped region is located between the channel region and second doped region, wherein, in the 3rd doped region
Doped ions concentration is less than the Doped ions concentration of first doped region.
20. method according to claim 19, it is characterised in that the doping process is ion implantation technology.
21. method according to claim 20, it is characterised in that the method for the formation active layer, is specifically included：
Active layer is formed on the underlay substrate；Wherein, the active layer includes：Channel region, first area, second area and
3rd region；The second area is located at side of the first area away from the channel region, and the 3rd region is located at institute
State between channel region and the second area；
First time ion implanting is carried out, the second doped region is formed at the second area；
Deposition forms gate insulator on the active layer for forming second doped region, and it is convex that the gate insulator includes first
Play region and the second elevated regions；Wherein, where the underlay substrate on the direction of plane, first convex area
The orthographic projection in domain and the orthographic projection in the 3rd region are completely superposed, also, the channel region is second elevated regions
In the orthographic projection region where the underlay substrate on the direction of plane；
Deposition forms grid in the range of the second elevated regions on the gate insulator so that perpendicular to the underlay substrate
On the direction of place plane, the orthographic projection of the grid is located in the orthographic projection of second elevated regions；
Second of ion implanting is carried out, the first doped region is formed at the first area, and formed at the 3rd region
3rd doped region, to cause the Doped ions concentration of the 3rd doped region dense less than the Doped ions of first doped region
Degree, and Doped ions concentration of the Doped ions concentration less than second doped region of first doped region.
22. method according to claim 21, it is characterised in that the Doped ions of the first time ion implanting be boron from
Son；The Doped ions of second of ion implanting are phosphonium ion.
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109449210A (en) * | 2018-09-19 | 2019-03-08 | 云谷（固安）科技有限公司 | Drive thin film transistor (TFT) and preparation method, array substrate and display device |
| CN110416286A (en) * | 2019-07-30 | 2019-11-05 | 京东方科技集团股份有限公司 | A kind of display panel, its production method and display device |
| CN110867459A (en) * | 2019-11-27 | 2020-03-06 | 厦门天马微电子有限公司 | Display panel, manufacturing method thereof and display device |
| CN113113354A (en) * | 2021-03-18 | 2021-07-13 | 武汉华星光电技术有限公司 | Optical device, preparation method thereof and display panel |
| WO2023168749A1 (en) * | 2022-03-10 | 2023-09-14 | 广州华星光电半导体显示技术有限公司 | Array substrate and display panel |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001085693A (en) * | 1999-09-10 | 2001-03-30 | Seiko Epson Corp | Method for manufacturing semiocnductor device, electro- optical device and electronic apparatus |
| US20040126955A1 (en) * | 2001-12-28 | 2004-07-01 | Han-Wook Hwang | Poly-crystalline thin film transistor and fabrication method thereof |
| CN100505310C (en) * | 2004-04-21 | 2009-06-24 | 三菱电机株式会社 | Semiconductor device and image display device |
| CN104241390A (en) * | 2013-06-21 | 2014-12-24 | 上海和辉光电有限公司 | Thin film transistor, active matrix organic light emitting diode assembly and manufacturing method |
-
2017
- 2017-05-26 CN CN201710382452.4A patent/CN107204376B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001085693A (en) * | 1999-09-10 | 2001-03-30 | Seiko Epson Corp | Method for manufacturing semiocnductor device, electro- optical device and electronic apparatus |
| US20040126955A1 (en) * | 2001-12-28 | 2004-07-01 | Han-Wook Hwang | Poly-crystalline thin film transistor and fabrication method thereof |
| CN100505310C (en) * | 2004-04-21 | 2009-06-24 | 三菱电机株式会社 | Semiconductor device and image display device |
| CN104241390A (en) * | 2013-06-21 | 2014-12-24 | 上海和辉光电有限公司 | Thin film transistor, active matrix organic light emitting diode assembly and manufacturing method |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109449210A (en) * | 2018-09-19 | 2019-03-08 | 云谷（固安）科技有限公司 | Drive thin film transistor (TFT) and preparation method, array substrate and display device |
| CN110416286A (en) * | 2019-07-30 | 2019-11-05 | 京东方科技集团股份有限公司 | A kind of display panel, its production method and display device |
| CN110416286B (en) * | 2019-07-30 | 2023-07-18 | 京东方科技集团股份有限公司 | Display panel, manufacturing method thereof and display device |
| CN110867459A (en) * | 2019-11-27 | 2020-03-06 | 厦门天马微电子有限公司 | Display panel, manufacturing method thereof and display device |
| CN110867459B (en) * | 2019-11-27 | 2022-12-09 | 厦门天马微电子有限公司 | Display panel, manufacturing method thereof and display device |
| CN113113354A (en) * | 2021-03-18 | 2021-07-13 | 武汉华星光电技术有限公司 | Optical device, preparation method thereof and display panel |
| WO2023168749A1 (en) * | 2022-03-10 | 2023-09-14 | 广州华星光电半导体显示技术有限公司 | Array substrate and display panel |
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